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1

SHUKLA, SOUMITRA, BAHNIMAN GHOSH, and MOHAMMAD WASEEM AKRAM. "1-BIT FULL ADDER IMPLEMENTATION USING SINGLE SPIN LOGIC PARADIGM." SPIN 02, no. 02 (2012): 1250012. http://dx.doi.org/10.1142/s2010324712500129.

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This paper presents the implementation of important full adder circuits using quantum dots (QDs) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A fair comparison among these adders shows that the mirror adder implementation in SSL paradigm does not carry any advantage over the CMOS adder in terms of complexity and number of QDs, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, static and dynamic Manchester carry gate adders in SSL reduces the complexity and number of QDs, in harmony w
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2

N Md, Bilal, Bhaskara Rao K, and Mohan Das S. "Energy Efficient GDI Based Full Adders For Computing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 5–9. http://dx.doi.org/10.46647/ijetms.2020.v04i06.002.

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This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and e
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3

Singh, Shiwani, Tripti Sharma, K. G. Sharma, and B. P. Singh. "PMOS based 1-Bit Full Adder Cell." International Journal of Computer Applications 42, no. 15 (2012): 8–18. http://dx.doi.org/10.5120/5766-7984.

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4

Upadhyay, Rahul Mani, R. K. Chauhan, and Manish Kumar. "Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 11, no. 4 (2023): 475–88. http://dx.doi.org/10.14201/adcaij.28558.

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The need for a low power system on a chip for embedded systems has increased enormously for human to machine interaction. The primary constraint of such embedded system is to consume less power and improve the battery performance of the device. We propose energy efficient, low power hybrid 1-bit full adder circuit in this paper, which may be integrated on chip to improve the overall performance of embedded systems. The proposed 1-bit hybrid full adder circuit designed at 130 nm technology was simulated using Mentor Graphics EDA tool. Further, a comparison is made with the previously proposed f
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5

Ram, L. Adithya, V. Ajay Kumar, H. Karthik, and Sudhir Dakey. "Analysis of 1-bit Full Adders in Cadence 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 5836–44. http://dx.doi.org/10.22214/ijraset.2024.62995.

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Abstract: A full adder is a digital circuit that performs the arithmetic operation of addition on three binary digits, producing a sum and a carry output. Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the in
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6

Melnyk, Oleksandr, Maksym Kravets, and Valerii Kravets. "Four-bit Nanoadder Controlled by Five-Inputs Majority Elements." Electronics and Control Systems 4, no. 74 (2022): 67–72. http://dx.doi.org/10.18372/1990-5548.74.17310.

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This paper presents a nano circuit of a full one-bit adder on the proposed five-input majority element. This innovative full adder design is used to development of a four-bit adder based on it. We offer a new single-bit full adder and a four-bit adder nano circuit in quantum-dot cellular automata technology. The proposed design four-bit adder utilizes only 231 quantum cells in a 0.49 µm2 area. It has a reduction in the number of cells, delay and energy dissipation at 1 K compared to the existing works. The QCADdesigner version 2.0.3 tool implements the developed quantum-dot cellular automata f
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7

Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power
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8

K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power
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9

Vinay, M. "Design and Implementation of 1-bit Full Subtractor Using FinFET." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 768–75. http://dx.doi.org/10.22214/ijraset.2024.63208.

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Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cou
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10

S, Haroon Rasheed, Mohan Das S, and Samba Sivudu Gaddam. "DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 15–18. http://dx.doi.org/10.46647/ijetms.2020.v04i06.004.

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This paper presents an energy efficient 1-bit full adder designed with a low voltage and high performance internal logic cells which leads to have abridged Power Delay Product (PDP). The customized XNOR and XOR gates, a necessary entity, are also presented. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 1-bit adder cell is compared with various trendy adders based on speed, power consumption and energy (PDP). The proposed adder schemes with modified internal entity cells achieve significant
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11

Ghabri, H., Issa D. Ben, and H. Samet. "Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor." Engineering, Technology & Applied Science Research 9, no. 6 (2019): 4933–36. https://doi.org/10.5281/zenodo.3566169.

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The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistor
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12

Reddy Eamani, Ramakrishna, Vinodhkumar Nallathambi, and Sasikumar Asaithambi. "A low-power high speed full adder cell using carbon nanotube field effect transistors." Indonesian Journal of Electrical Engineering and Computer Science 31, no. 1 (2023): 134. http://dx.doi.org/10.11591/ijeecs.v31.i1.pp134-142.

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The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model
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13

RamakrishnaReddy, Eamani, Nallathambi Vinodhkumar, and Asaithambi Sasikumar. "A low-power high speed full adder cell using carbon nanotube field effect transistors." A low-power high speed full adder cell using carbon nanotube field effect transistors 31, no. 1 (2023): 134–42. https://doi.org/10.11591/ijeecs.v31.i1.pp134-142.

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The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model
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14

PRITI, SAHU, and TIWARI RAVI. "IMPLEMENTATION OF FINFET BASED 1-BIT FULL ADDER." i-manager’s Journal on Electronics Engineering 9, no. 4 (2019): 32. http://dx.doi.org/10.26634/jele.9.4.16251.

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15

Sarada Musala. "Analysis of Energy Efficient Differential Fault Tolerant Adders with Minimized Nonlinearities." Communications on Applied Nonlinear Analysis 32, no. 5s (2024): 69–77. https://doi.org/10.52783/cana.v32.2968.

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In this paper, two 1-bit Differential fault tolerant Full Adder circuits (1b-FA)proposed focusing on reducing nonlinearities to improve performance and reliability in modern electronic systems, using Carbon Nano FETs (CNFETs).Transmission gate logic and pass transistor logic is being used in proposed adders to improve energy and fault tolerant characteristics of Full Adder. Fault detection and fault correction mechanisms are proposed in outputs of 1-bit differential full adder. The proposed fault detection can detect only single error and proposed error correction can correct it. By using Cade
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16

Yaminikumari, Jampani, and Gudla Bhanu Gupta. "Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (2022): 4974–82. http://dx.doi.org/10.22214/ijraset.2022.46097.

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Abstract: In this work, we have implemented 1-bit Full Adder Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high-speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The 1-bit Full Adder Circuit has been performed and obtained I-V characteristics and power for sum and carry were calculated. The effect of scaling on the overall performance is also analysed through the performance evaluation of 1-bit full adder circuit. Simulation results have been performed on LT Spice tool simulator a
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17

S., Kaviya, and Kumar D. "Design of an Efficient Multiplier Using Transistor Level Modified Adders." Journal of VLSI Design and Signal Processing 5, no. 2 (2019): 17–27. https://doi.org/10.5281/zenodo.2837838.

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<em>The endless improvement of modern mobile, compact devices and applications has caused an enormous effect for ultralow power circuit design. Various methods and techniques have been applied successfully to the power, performance region of the design spectrum for lower power consumption. In some applications wherever ultralow power consumption is that the primary requirement and performance is of secondary importance, a more aggressive approach is secure. The new applications mainly depend on the transistor count of circuit with longer economical battery life. The minimum energy point is obt
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18

Hajare, Raju, and C. Lakshminarayana. "Design and software characterization of finFET based full adders." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 1 (2019): 51. http://dx.doi.org/10.11591/ijres.v8.i1.pp51-60.

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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at
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19

Ghabri, H., D. Ben Issa, and H. Samet. "Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor." Engineering, Technology & Applied Science Research 9, no. 6 (2019): 4933–36. http://dx.doi.org/10.48084/etasr.3156.

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The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistor
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20

Raju, Hajare, and Lakshminarayana C. "Design and software characterization of finFET based full adders." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 1 (2019): 51–60. https://doi.org/10.11591/ijres.v8.i1.pp51-60.

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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET&rsquo;s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET&rsquo;s were continuously scaled down. Further scaling below 45nm, MOSFET&rsquo;s suffers from Short Channel Effects (SCE&rsquo;s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and
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21

SinghChandel, Dhyanendra, Sachin Bandewar, and Anand Kumar Singh. "Low Power 10T XOR based 1 Bit Full Adder." International Journal of Computer Applications 121, no. 1 (2015): 13–16. http://dx.doi.org/10.5120/21503-4019.

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22

DAS, S. MOHAN, GANESH KUMAR M, and BHASKARA RAO K. "Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder." International Journal of Engineering Technology and Management Sciences 5, no. 1 (2021): 1–7. http://dx.doi.org/10.46647/ijetms.2021.v05i01.001.

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This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal l
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23

Fahrezi, Tommy Fadel, and Yoana Nurul Asri. "Pembuatan Alat Simulasi Trainer Adder dan Subtractor." Jurnal Pendidikan Fisika dan Sains (JPFS) 2, no. 2 (2019): 72–79. http://dx.doi.org/10.52188/jpfs.v2i2.72.

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Pada dunia pendidikan khususnya elektronika memerlukan alat penunjang praktik seperti alat praktik rangkaian digital salah satunya ialah trainer. Dasar dari pembentukan sistem digital trainer adalah gerbang logika. Rangkaian digital terdiri dari sekelompok gerbang logika, yang beroperasi dalam bilangan biner. Untuk membuat trainer ini di butuhkan gerbang logika. Gerbang logika yang dipergunakan untuk membuat trainer adder dan subtractor yaitu: Inverting Gate, AND Gate, OR Gate, dan Exclusive-OR Gate. Untuk menjalankan trainer adder dan subtractor ini dibutuhkan tegangan 220 VAC dan menghasilka
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24

Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.

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The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), T
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25

Shylashree, N., and D. S. Mahesh. "Latency and throughput analysis of a pipelined GDI ripple carry adder." International Journal of Engineering & Technology 7, no. 2.21 (2018): 123. http://dx.doi.org/10.14419/ijet.v7i2.21.11848.

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Latency and Throughput are deemed parameters of prime importance that determine the speed of an Adder Circuit. Ongoing research in the field of Digital Signal Processing involves optimizing an Adder regarding these parameters. This article picks up the study of a ripple carry adder and presents the use of two methods towards ameliorating the performance of an adder – viz., the use of GDI (Gate Diffusion Input) technology for reduced Latency, and implementation of a pipelined architecture towards increasing the throughput. In this paper, we have dileneated the function of a basic GDI cell, with
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26

Salama, H., B. Saman, R. Gudlavalleti, et al. "Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (2020): 2040013. http://dx.doi.org/10.1142/s0129156420400133.

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This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.
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27

Gnilenko, Alexey. "LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC." System technologies 1, no. 126 (2020): 46–53. http://dx.doi.org/10.34185/1562-9945-1-126-2020-05.

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The full adder is a key element of any arithmetic logic units used in microprocessor systems. For microprocessor components created for modern mobile digital devices, compact layout design on the silicone chip is of great importance. In this paper an area effective layout design on the chip is proposed for 4-bit ripple carry adder based on pass transistor logic. The full adder is simulated using EDA tool and output signal waveforms are obtained to demonstrate the functionality of the design. It is shown that 1-bit full adder based on pass transistor logic and composed of two 3T XOR gates and o
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28

Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.

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In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-
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29

Et. al., A. S. Keerthi Nayani. "Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 5720–25. http://dx.doi.org/10.17762/turcomat.v12i3.2247.

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The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hard
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30

Subramaniam, Shahmini, Ajay Kumar Singh, and Gajula Ramana Murthy. "Design of power efficient stable 1-bit full adder circuit." IEICE Electronics Express 15, no. 14 (2018): 20180552. http://dx.doi.org/10.1587/elex.15.20180552.

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31

Shams, A. M., and M. A. Bayoumi. "A novel high-performance CMOS 1-bit full-adder cell." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47, no. 5 (2000): 478–81. http://dx.doi.org/10.1109/82.842117.

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32

Swati, Narang. "PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 8 (2017): 200–208. https://doi.org/10.5281/zenodo.839170.

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In this paper, a hybrid low power and high speed 1-bit full adder design employing both complimentary metal oxide (CMOS) logic and transmission gate logic is reported. The design was implemented for 1 bit. The circuit was implemented using Mentor tanner tool in 180 and 90 nm technology. Performance parameters such as power, delay and transistor count were compared with existing designs such as complimentary pass transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS logic output drive full adder , and so on. For 1.8-V supply at 180-nm technol
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33

Woo, Wei Kai, binti Ahmad Nabihah, and Hairol bin Jabbar Mohamad. "Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (2017): 3010–19. https://doi.org/10.11591/ijece.v7i6.pp3010-3019.

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The static power consumption is an important parameter concern in IC design due to t for a higher integration numbers of transistor to achieve greater performance in a single chip. Leakage current is the main issues for static power dissipation in standby mode as the size of transistor been scale. Therefore, the subthreshold leakage current rises due to threshold voltage scaling and gate leakage current increases due to scale down of oxide thickness. In this paper, a Variable Body Biasing (VBB) technique was applied to reduce static power consumption in VLSI design. The VBB technique used a DC
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34

Lamani, Deepa Suranam, and Dr H. V. Ravish Aradhya. "Design of Low Power 64-Bit Hybrid Full Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (2023): 2200–2205. http://dx.doi.org/10.22214/ijraset.2023.55554.

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Abstract: In the realm of Computer Science, integrated circuits (ICs) have propelled microprocessor and digital signal processor development, hinging on the 1-bit full adder's significance for mathematical tasks. To amplify overall efficiency, enhancing this adder is pivotal. As demand surges for power-efficient devices like smartphones and MP3 players, maintaining a balance between speed, size, and power usage becomes imperative. Engineers tackle this challenge while bridging battery technology gaps. We propose advanced 1-bit full adder designs, evaluated via Cadence Virtuoso. A hybrid versio
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35

Kumar, Raushan, Sahadev Roy, and C. T. Bhunia. "Low-Power High-Speed Double Gate 1-bit Full Adder Cell." International Journal of Electronics and Telecommunications 62, no. 4 (2016): 329–34. http://dx.doi.org/10.1515/eletel-2016-0045.

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Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and fr
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36

V.P, Visanthi. "FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA." International Journal Of Trendy Research In Engineering And Technology 07, no. 01 (2023): 46–48. http://dx.doi.org/10.54473/ijtret.2023.7109.

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A CMOS Full Adder is designed using Tanner EDA Tool based on 0.25µm CMOS Technology. In the arithmetic logic unit (ALU), the full adder cell is one of the most frequently utilized digital circuit components and the fundamental functional unit of all computational circuits. Right now, a lot of work has been done to improve the architecture and functionality of full adder circuit designs. In this research, two innovative 1-bit full adder cell designs are developed using ten transistors and 0.25mm CMOS technology (10-T). Tanner software tools will be used in the design of the CMOS full adder to s
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Kumar, Pankaj, and Rajender Kumar Sharma. "An Energy Efficient Logic Approach to Implement CMOS Full Adder." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750084. http://dx.doi.org/10.1142/s0218126617500840.

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An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool wi
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Parameshwara, M. C., and H. C. Srinivasaiah. "Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750014. http://dx.doi.org/10.1142/s0218126617500141.

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A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipa
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Erniyazov, Sarvarbek, and Jun Cheol Jeon. "Implementation of Full Adder Using 5-Input Majority Gate." International Journal of Engineering & Technology 7, no. 4.4 (2018): 17. http://dx.doi.org/10.14419/ijet.v7i4.4.19598.

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In this paper full adder was created employing five-input majority gate according to Quantum-Dot Cellular Automata (QCA) innovation. We used the QCA logic in our modified structure to reduce the delay. That report details the structure furthermore investigate associated with QCA dependent 1-bit full adder design for minimal energy purposes. This method permits decreasing energy expenditure, delay, additionally location involving electronic circuits.
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Tirumalasetty, Venkata Rao, K. Babulu, and G. Appala Naidu. "Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design." WSEAS TRANSACTIONS ON SYSTEMS 23 (April 9, 2024): 141–48. http://dx.doi.org/10.37394/23202.2024.23.16.

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CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exc
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Maeen, Mehrdad, Vahid Foroutan, and Keivan Navi. "On the design of low power 1-bit full adder cell." IEICE Electronics Express 6, no. 16 (2009): 1148–54. http://dx.doi.org/10.1587/elex.6.1148.

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Kratikatiyar and Praveen Kumar. "Performances Analysis of High-Speed Low-Power 1-bit Full Adder." INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING AND MANAGEMENT 2, no. 5 (2017): 106. http://dx.doi.org/10.24999/ijoaem/02050027.

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Shams, A. M., T. K. Darwish, and M. A. Bayoumi. "Performance analysis of low-power 1-bit CMOS full adder cells." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10, no. 1 (2002): 20–29. http://dx.doi.org/10.1109/92.988727.

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Naghizadeh, Hamid Reza, Mohammad Sarvghad Moghadam, Saber Izadpanah Tous, and Abbas Golmakani. "Design of Two High Performance 1-Bit CMOS Full Adder Cells." International Journal of Computing and Digital Systems 2, no. 1 (2013): 47–52. http://dx.doi.org/10.12785/ijcds/020106.

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45

Verma, Preeti, Ajay K. Sharma, Arti Noor, and Vinay S. Pandey. "SDTSPC-technique for low power noise aware 1-bit full adder." Analog Integrated Circuits and Signal Processing 92, no. 2 (2017): 303–14. http://dx.doi.org/10.1007/s10470-017-0994-3.

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Wei Kai, Woo, Nabihah binti Ahmad, and Mohamad Hairol Bin Jabbar. "Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (2017): 3010. http://dx.doi.org/10.11591/ijece.v7i6.pp3010-3019.

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The static power consumption is an important parameter concern in IC design due to t for a higher integration numbers of transistor to achieve greater performance in a single chip. Leakage current is the main issues for static power dissipation in standby mode as the size of transistor been scale. Therefore, the subthreshold leakage current rises due to threshold voltage scaling and gate leakage current increases due to scale down of oxide thickness. In this paper, a Variable Body Biasing (VBB) technique was applied to reduce static power consumption in VLSI design. The VBB technique used a DC
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47

Murthy, G. Ramana, C. Senthilpari, P. Velrajkumar, and T. S. Lim. "Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process." Applied Mechanics and Materials 284-287 (January 2013): 2580–89. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2580.

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This paper presents a 1-bit full adder by using as few as six transistors per bit in its design. It is designed with a combination of multiplexing control input and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-transistor adder cell. The design adopts Multiplexing with Control input technique to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. The proposed design successfully embeds the buffering circuit in the full adder design a
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48

M., Balal Siddiqui, T. Beg M., and N. Ahmad S. "Implementation of GA with Position Based Crossover-PX Technique for Size Optimization of BDD Mapped Adder Circuits." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 4215–18. https://doi.org/10.35940/ijeat.C6358.029320.

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Binary Decision Diagrams or BDD are data structure used to represent single and multi-output digital circuits. BDD mapped adder circuits are used to represent different adder functions in a digital system. Optimization of adder circuits are done by optimizing the corresponding BDDs. In this work the optimization of BDD Mapped adder circuits are proposed by using genetic algorithm with position-based crossover-PX technique. The main feature of position-based crossover technique is that it is suitable for order-based solution formation. We compared our result with other existing variable order m
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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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50

Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas
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