Journal articles on the topic '1-bit full adder'
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SHUKLA, SOUMITRA, BAHNIMAN GHOSH, and MOHAMMAD WASEEM AKRAM. "1-BIT FULL ADDER IMPLEMENTATION USING SINGLE SPIN LOGIC PARADIGM." SPIN 02, no. 02 (2012): 1250012. http://dx.doi.org/10.1142/s2010324712500129.
Full textN Md, Bilal, Bhaskara Rao K, and Mohan Das S. "Energy Efficient GDI Based Full Adders For Computing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 5–9. http://dx.doi.org/10.46647/ijetms.2020.v04i06.002.
Full textSingh, Shiwani, Tripti Sharma, K. G. Sharma, and B. P. Singh. "PMOS based 1-Bit Full Adder Cell." International Journal of Computer Applications 42, no. 15 (2012): 8–18. http://dx.doi.org/10.5120/5766-7984.
Full textUpadhyay, Rahul Mani, R. K. Chauhan, and Manish Kumar. "Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 11, no. 4 (2023): 475–88. http://dx.doi.org/10.14201/adcaij.28558.
Full textRam, L. Adithya, V. Ajay Kumar, H. Karthik, and Sudhir Dakey. "Analysis of 1-bit Full Adders in Cadence 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 5836–44. http://dx.doi.org/10.22214/ijraset.2024.62995.
Full textMelnyk, Oleksandr, Maksym Kravets, and Valerii Kravets. "Four-bit Nanoadder Controlled by Five-Inputs Majority Elements." Electronics and Control Systems 4, no. 74 (2022): 67–72. http://dx.doi.org/10.18372/1990-5548.74.17310.
Full textEt.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.
Full textK Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.
Full textVinay, M. "Design and Implementation of 1-bit Full Subtractor Using FinFET." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 768–75. http://dx.doi.org/10.22214/ijraset.2024.63208.
Full textS, Haroon Rasheed, Mohan Das S, and Samba Sivudu Gaddam. "DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 15–18. http://dx.doi.org/10.46647/ijetms.2020.v04i06.004.
Full textGhabri, H., Issa D. Ben, and H. Samet. "Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor." Engineering, Technology & Applied Science Research 9, no. 6 (2019): 4933–36. https://doi.org/10.5281/zenodo.3566169.
Full textReddy Eamani, Ramakrishna, Vinodhkumar Nallathambi, and Sasikumar Asaithambi. "A low-power high speed full adder cell using carbon nanotube field effect transistors." Indonesian Journal of Electrical Engineering and Computer Science 31, no. 1 (2023): 134. http://dx.doi.org/10.11591/ijeecs.v31.i1.pp134-142.
Full textRamakrishnaReddy, Eamani, Nallathambi Vinodhkumar, and Asaithambi Sasikumar. "A low-power high speed full adder cell using carbon nanotube field effect transistors." A low-power high speed full adder cell using carbon nanotube field effect transistors 31, no. 1 (2023): 134–42. https://doi.org/10.11591/ijeecs.v31.i1.pp134-142.
Full textPRITI, SAHU, and TIWARI RAVI. "IMPLEMENTATION OF FINFET BASED 1-BIT FULL ADDER." i-manager’s Journal on Electronics Engineering 9, no. 4 (2019): 32. http://dx.doi.org/10.26634/jele.9.4.16251.
Full textSarada Musala. "Analysis of Energy Efficient Differential Fault Tolerant Adders with Minimized Nonlinearities." Communications on Applied Nonlinear Analysis 32, no. 5s (2024): 69–77. https://doi.org/10.52783/cana.v32.2968.
Full textYaminikumari, Jampani, and Gudla Bhanu Gupta. "Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (2022): 4974–82. http://dx.doi.org/10.22214/ijraset.2022.46097.
Full textS., Kaviya, and Kumar D. "Design of an Efficient Multiplier Using Transistor Level Modified Adders." Journal of VLSI Design and Signal Processing 5, no. 2 (2019): 17–27. https://doi.org/10.5281/zenodo.2837838.
Full textHajare, Raju, and C. Lakshminarayana. "Design and software characterization of finFET based full adders." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 1 (2019): 51. http://dx.doi.org/10.11591/ijres.v8.i1.pp51-60.
Full textGhabri, H., D. Ben Issa, and H. Samet. "Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor." Engineering, Technology & Applied Science Research 9, no. 6 (2019): 4933–36. http://dx.doi.org/10.48084/etasr.3156.
Full textRaju, Hajare, and Lakshminarayana C. "Design and software characterization of finFET based full adders." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 1 (2019): 51–60. https://doi.org/10.11591/ijres.v8.i1.pp51-60.
Full textSinghChandel, Dhyanendra, Sachin Bandewar, and Anand Kumar Singh. "Low Power 10T XOR based 1 Bit Full Adder." International Journal of Computer Applications 121, no. 1 (2015): 13–16. http://dx.doi.org/10.5120/21503-4019.
Full textDAS, S. MOHAN, GANESH KUMAR M, and BHASKARA RAO K. "Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder." International Journal of Engineering Technology and Management Sciences 5, no. 1 (2021): 1–7. http://dx.doi.org/10.46647/ijetms.2021.v05i01.001.
Full textFahrezi, Tommy Fadel, and Yoana Nurul Asri. "Pembuatan Alat Simulasi Trainer Adder dan Subtractor." Jurnal Pendidikan Fisika dan Sains (JPFS) 2, no. 2 (2019): 72–79. http://dx.doi.org/10.52188/jpfs.v2i2.72.
Full textAbdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.
Full textShylashree, N., and D. S. Mahesh. "Latency and throughput analysis of a pipelined GDI ripple carry adder." International Journal of Engineering & Technology 7, no. 2.21 (2018): 123. http://dx.doi.org/10.14419/ijet.v7i2.21.11848.
Full textSalama, H., B. Saman, R. Gudlavalleti, et al. "Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (2020): 2040013. http://dx.doi.org/10.1142/s0129156420400133.
Full textGnilenko, Alexey. "LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC." System technologies 1, no. 126 (2020): 46–53. http://dx.doi.org/10.34185/1562-9945-1-126-2020-05.
Full textRao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.
Full textEt. al., A. S. Keerthi Nayani. "Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 5720–25. http://dx.doi.org/10.17762/turcomat.v12i3.2247.
Full textSubramaniam, Shahmini, Ajay Kumar Singh, and Gajula Ramana Murthy. "Design of power efficient stable 1-bit full adder circuit." IEICE Electronics Express 15, no. 14 (2018): 20180552. http://dx.doi.org/10.1587/elex.15.20180552.
Full textShams, A. M., and M. A. Bayoumi. "A novel high-performance CMOS 1-bit full-adder cell." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47, no. 5 (2000): 478–81. http://dx.doi.org/10.1109/82.842117.
Full textSwati, Narang. "PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 8 (2017): 200–208. https://doi.org/10.5281/zenodo.839170.
Full textWoo, Wei Kai, binti Ahmad Nabihah, and Hairol bin Jabbar Mohamad. "Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (2017): 3010–19. https://doi.org/10.11591/ijece.v7i6.pp3010-3019.
Full textLamani, Deepa Suranam, and Dr H. V. Ravish Aradhya. "Design of Low Power 64-Bit Hybrid Full Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (2023): 2200–2205. http://dx.doi.org/10.22214/ijraset.2023.55554.
Full textKumar, Raushan, Sahadev Roy, and C. T. Bhunia. "Low-Power High-Speed Double Gate 1-bit Full Adder Cell." International Journal of Electronics and Telecommunications 62, no. 4 (2016): 329–34. http://dx.doi.org/10.1515/eletel-2016-0045.
Full textV.P, Visanthi. "FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA." International Journal Of Trendy Research In Engineering And Technology 07, no. 01 (2023): 46–48. http://dx.doi.org/10.54473/ijtret.2023.7109.
Full textKumar, Pankaj, and Rajender Kumar Sharma. "An Energy Efficient Logic Approach to Implement CMOS Full Adder." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750084. http://dx.doi.org/10.1142/s0218126617500840.
Full textParameshwara, M. C., and H. C. Srinivasaiah. "Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750014. http://dx.doi.org/10.1142/s0218126617500141.
Full textErniyazov, Sarvarbek, and Jun Cheol Jeon. "Implementation of Full Adder Using 5-Input Majority Gate." International Journal of Engineering & Technology 7, no. 4.4 (2018): 17. http://dx.doi.org/10.14419/ijet.v7i4.4.19598.
Full textTirumalasetty, Venkata Rao, K. Babulu, and G. Appala Naidu. "Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design." WSEAS TRANSACTIONS ON SYSTEMS 23 (April 9, 2024): 141–48. http://dx.doi.org/10.37394/23202.2024.23.16.
Full textMaeen, Mehrdad, Vahid Foroutan, and Keivan Navi. "On the design of low power 1-bit full adder cell." IEICE Electronics Express 6, no. 16 (2009): 1148–54. http://dx.doi.org/10.1587/elex.6.1148.
Full textKratikatiyar and Praveen Kumar. "Performances Analysis of High-Speed Low-Power 1-bit Full Adder." INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING AND MANAGEMENT 2, no. 5 (2017): 106. http://dx.doi.org/10.24999/ijoaem/02050027.
Full textShams, A. M., T. K. Darwish, and M. A. Bayoumi. "Performance analysis of low-power 1-bit CMOS full adder cells." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10, no. 1 (2002): 20–29. http://dx.doi.org/10.1109/92.988727.
Full textNaghizadeh, Hamid Reza, Mohammad Sarvghad Moghadam, Saber Izadpanah Tous, and Abbas Golmakani. "Design of Two High Performance 1-Bit CMOS Full Adder Cells." International Journal of Computing and Digital Systems 2, no. 1 (2013): 47–52. http://dx.doi.org/10.12785/ijcds/020106.
Full textVerma, Preeti, Ajay K. Sharma, Arti Noor, and Vinay S. Pandey. "SDTSPC-technique for low power noise aware 1-bit full adder." Analog Integrated Circuits and Signal Processing 92, no. 2 (2017): 303–14. http://dx.doi.org/10.1007/s10470-017-0994-3.
Full textWei Kai, Woo, Nabihah binti Ahmad, and Mohamad Hairol Bin Jabbar. "Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (2017): 3010. http://dx.doi.org/10.11591/ijece.v7i6.pp3010-3019.
Full textMurthy, G. Ramana, C. Senthilpari, P. Velrajkumar, and T. S. Lim. "Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process." Applied Mechanics and Materials 284-287 (January 2013): 2580–89. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2580.
Full textM., Balal Siddiqui, T. Beg M., and N. Ahmad S. "Implementation of GA with Position Based Crossover-PX Technique for Size Optimization of BDD Mapped Adder Circuits." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 4215–18. https://doi.org/10.35940/ijeat.C6358.029320.
Full textSandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.
Full textDr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.
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