Journal articles: '1 dB compression point'

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Alleva, Vincenzo, Andrea Bettidi, Walter Ciccognani, Marco De Dominicis, Mauro Ferrari, Claudio Lanzieri, Ernesto Limiti, and Marco Peroni. "High-power monolithic AlGaN/GaN high electron mobility transistor switches." International Journal of Microwave and Wireless Technologies 1, no. 4 (June 19, 2009): 339–45. http://dx.doi.org/10.1017/s1759078709990183.

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This work presents the design, fabrication, and test of X-band and 2–18 GHz wideband high-power single pole double throw (SPDT) monolithic microwave integrated circuit (MMIC) switches in microstrip gallium nitride (GaN) technology. Such switches have demonstrated state-of-the-art performances and RF fabrication yields better than 65%. In particular, the X-band switch exhibits 1 dB insertion loss, better than 37 dB isolation, and a power handling capability better than 39 dBm at a 1 dB insertion loss compression point; the wideband switch shows an insertion loss lower than 2.2 dB, better than 25 dB isolation, and an insertion loss compression of 1 dB at an input drive higher than 38.5 dBm in the entire bandwidth.

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Le, Phong Dai, Vu Duy Thong, and Pham Le Binh. "Broadband GaAs pHemt LNA design for T/R module application." Vietnam Journal of Science and Technology 54, no. 5 (October 19, 2016): 584. http://dx.doi.org/10.15625/0866-708x/54/5/6978.

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In this paper, a three stages monolithic low noise amplifier (LNA) for T/R module application is presented. This LNA is fully integrated on 0.15-um pHEMT GaAs technology and achieves a wide bandwidth from 6 GHz to 11 GHz. Within this band, the LNA has the minimum of 1.3 dB noise figure and over 25 dB small signal gain. The output third order interception point (OIP3) is over 30 dBm and the 1 dB compression point (P1 dB) is 16 dBm at the output.

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Al-kanan, Haider, Xianzhen Yang, and Fu Li. "Improved estimation for Saleh model and predistortion of power amplifiers using 1-dB compression point." Journal of Engineering 2020, no. 1 (January 1, 2020): 13–18. http://dx.doi.org/10.1049/joe.2019.0973.

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Tannir, Dani A. "Computation of the 1-dB compression point in radio frequency amplifier circuits using moments analysis." International Journal of RF and Microwave Computer-Aided Engineering 25, no. 1 (May 20, 2014): 10–20. http://dx.doi.org/10.1002/mmce.20818.

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Budnyaev, Vadim, and Valeriy Vertegel. "A SiGe 3-stage LNA for automotive radar application from 76 to 81 GHz." ITM Web of Conferences 30 (2019): 01004. http://dx.doi.org/10.1051/itmconf/20193001004.

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This paper presents the simulation results of the W-band 3-stage low noise amplifier which is designed in 0.13 μm SiGe BiCMOS technology. The LNA achieves a peak S21 of 24.1 dB and noise figure of 6 dB at 80 GHz with 3 dB bandwidth of 14 GHz from 73 to 87 GHz. S11 is better than 11 dB. The simulated input 1 dB compression point is –23 dBm at 80 GHz with low power consumption of 26 mW from 1.2 V voltage supply. Layout area is 0.36 mm2.

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Mehta, Shilpa. "A UWB CMOS Transceiver." Advanced Materials Research 403-408 (November 2011): 4965–67. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.4965.

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A direct-conversion ultra-wideband (UWB) trans-ceiver for Mode 1 OFDM applications employs three resonant networks and three phase-locked loops. Using a common-gate input stage, the receiver allows direct sharing of the antenna with the transmitter. Designed in 0.13- m CMOS technology, the transceiver provides a total gain of 69–73 dB and a noise figure of 6.5–8.4 dB across three bands, and a TX 1-dB compression point of 10 dBm. The circuit consumes 105 mW from a 1.5-V supply.

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Senadeera, P. M., Zhijian Xie, and Numan S. Dogan. "TWO STAGE ON OFF KEYING CLASS A RF POWER AMPLIFIER IN 0.18μm CMOS TECHNOLOGY." International Journal of Research -GRANTHAALAYAH 8, no. 11 (November 20, 2020): 15–21. http://dx.doi.org/10.29121/granthaalayah.v8.i11.2020.2067.

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A novel architecture for the On Off Keying (OOK) modulator with high gain and high data rate power amplifier (PA) operating at 11.6 GHz IBM 0.18-µm RF CMOS technology is presented for a X-band passive RFID tag. Currently used low frequency switching techniques such as multiplexers were not functioning in the high frequency X-band architectures. In this novel approach OOK modulator with power amplifier, a CMOS switch was used to transmit ‘1’ and ‘0’ coming from the digital signal unlike in the existing low frequency architectures. Both the load and driver in this proposed PA were class A operation supplied by a single ended 1.83V source. The important design considerations include output power, 1 dB compression point and linearity. The fabricated results of the amplifier have a 1 dB compression point of 1.2 dBm and input power of 5.19 dBm at 9.2 GHz.

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Ehsanian, Mehdi, and Masoud Askari-Raad. "A Built-In Self-Test structure for measuring gain and 1-dB compression point of Power Amplifier." AEU - International Journal of Electronics and Communications 86 (March 2018): 47–54. http://dx.doi.org/10.1016/j.aeue.2018.01.019.

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Vu, Tuan Anh. "A 60 GHz CMOS Power Amplifier for Wireless Communications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 2 (April 1, 2018): 926. http://dx.doi.org/10.11591/ijece.v8i2.pp926-932.

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This paper presents a 60 GHz power amplifier (PA) suitable for wireless communications. The two-stage wideband PA is fabricated in 55 nm CMOS. Measurement results show that the PA obtains a peak gain of 16 dB over a -3 dB bandwidth from 57 GHz to 67 GHz. It archives an output 1 dB compression point (OP1dB) of 4 dbm and a peak power added efficiency (PAE) of 12.6%. The PA consumes a total DC power of 38.3 mW from a 1.2 V supply voltage while its core occupies a chip area of 0.45 mm2.

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Zhang, Yin Sheng, Jia Qiang Li, Hui Lin Shan, and Jie Zhou. "Design of a down-Conversion Mixer for Four Sub-Harmonic in W-Band." Applied Mechanics and Materials 130-134 (October 2011): 3284–88. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.3284.

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This paper presents principles of a down-converted mixer for four sub-harmonic designed by ADS software. The LO and RF frequencies are 23GHz, 92-94GHz respectively. The structure of ridge waveguide to microstrip transitions is optimized by CST simulation software, and W-band signals are directed to mixer RF side. The simulation results show that this mixer achieves higher 1 dB compression point, loss of frequency conversion less than 15 dB and good linearity.

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Vu, Tuan Anh, Kyoya Takano, and Minoru Fujishima. "Low-Power D-Band CMOS Amplifier for Ultrahigh-Speed Wireless Communications." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 2 (April 1, 2018): 933. http://dx.doi.org/10.11591/ijece.v8i2.pp933-938.

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This paper presents a low-power D-Band amplifier suitable for ultrahigh-speed wireless communications. The three-stage fully differential amplifier with capacitive neutralization is fabricated in 40 nm CMOS provided by TSMC. Measurement results show that the D-band amplifier obtains a peak gain of 9.6 dB over a -3 dB bandwidth from 138 GHz to 164.5 GHz. It exhibits an output 1 dB compression point (OP1dB) of 1.5 dbm at the center frequency of 150 GHz. The amplifier consumes a low power of 27.3 mW from a 0.7 V supply voltage while its core occupies a chip area of 0.06 mm2.

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Mehta, Shilpa, Xue-Jun Li, and Massimo Donelli. "Design and Analysis of a Reconfigurable Gilbert Mixer for Software-Defined Radios." Sensors 21, no. 8 (April 12, 2021): 2711. http://dx.doi.org/10.3390/s21082711.

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A reconfigurable gm-boosted, image-rejected downconversion mixer is presented in this paper using the SiGe 8 HP technology. The proposed mixer operates within 0.9–13.5 GHz that is suitable for software-defined radio applications. The conversion mixer comprises of resistive biased radio frequency (RF) section, double balanced Gilbert cell mixer core sections divided as per I and Q stages for image-rejection purpose, inductively peaked gm-boosting section and tunable filter section, respectively. In comparison to previous works in the scientific literature, the design shows enhanced conversion gain (CG), noise figure (NF), and image-rejection ratio (IRR). For the entire band of operation, the mixer attains a good return loss |S11| of <−10 dB. Additionally, the design accomplishes an excellent CG of 22 dB, NF of 2.5 dB, and an image-rejection ratio of 30.2 dB at maximum frequency. Finally, a third-order intercept point (IP3) of −3.28 dBm and 1 dB compression point (CP1) of −13 dBm, respectively, shows moderate linearity performance.

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Chun Lee, Ler, Abu Khari bin A'ain, and Albert Victor Kordesch. "Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor." VLSI Design 2008 (February 28, 2008): 1–6. http://dx.doi.org/10.1155/2008/479173.

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A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA) has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA). A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

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Adabi, Ehsan, and Ali M. Niknejad. "Analysis and Design of Transformer-Based mm-Wave Transmit/Receive Switches." International Journal of Microwave Science and Technology 2012 (July 26, 2012): 1–11. http://dx.doi.org/10.1155/2012/302302.

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Transformer-based shunt single pole, double-throw (SPDT) switches are analyzed, and design equations are provided. A mm-wave transformer-based SPDT shunt switch prototype was designed and fabricated in 90 nm digital CMOS process. It has a minimum insertion loss of 3.4 dB at 50 GHz from the single pole to the ON-thru port and a leakage of 19 dB from the single pole to the OFF-thru port. The isolation is 13.7 dB between the two thru ports. Large signal measurements verify that the switch is capable of handling +14 dBm of input power at its 1 dB compression point. The fabricated SPDT switch has a minute active area size of 60 μm×60 μm.

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Bakkali, Moustapha El, Said Elkhaldi, Intissar Hamzi, Abdelhafid Marroun, and Naima Amar Touhami. "UWB-MMIC Matrix Distributed Low Noise Amplifier." Proceedings 63, no. 1 (December 25, 2020): 52. http://dx.doi.org/10.3390/proceedings2020063052.

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In this paper, a 3.1–11 GHz ultra-wideband low noise amplifier with low noise figure, high power gain S21, low reverse gain S12, and high linearity using the OMMIC ED02AH process, which employs a 0.18 μm Pseudomorphic High Electron Mobility Transistor is presented. This Low Noise Amplifier (LNA) was designed with the Advanced Design System simulator in distributed matrix architecture. For the low noise amplifier, four stages were used obtaining a good input/output matching. An average power gain S21 of 11.6 dB with a gain ripple of ±0.6 dB and excellent noise figure of 3.55 to 4.25 dB is obtained in required band with a power dissipation of 48 mW under a supply voltage of 2 V. The input compression point 1 dB and third-order input intercept point are −1.5 and 23 dBm respectively. The core layout size is 1.8 × 1.2 mm2.

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Malmqvist, R., C. Samuelsson, A. Gustafsson, P. Rantakari, S. Reyaz, T. Vähä-Heikkilä, A. Rydberg, J. Varis, D. Smith, and R. Baggen. "A K-Band RF-MEMS-Enabled Reconfigurable and Multifunctional Low-Noise Amplifier Hybrid Circuit." Active and Passive Electronic Components 2011 (2011): 1–7. http://dx.doi.org/10.1155/2011/284767.

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A K-band (18–26.5 GHz) RF-MEMS-enabled reconfigurable and multifunctional dual-path LNA hybrid circuit (optimised for lowest/highest possible noise figure/linearity, resp.) is presented, together with its subcircuit parts. The two MEMS-switched low-NF (higher gain) and high-linearity (lower gain) LNA circuits (paths) present 16.0 dB/8.2 dB, 2.8 dB/4.9 dB and 15 dBm/20 dBm of small-signal gain, noise figure, and 1 dB compression point at 24 GHz, respectively. Compared with the two (fixed) LNA subcircuits used within this design, the MEMS-switched LNA circuit functions show minimum 0.6–1.3 dB higher NF together with similar values ofP1 dBat 18–25 GHz. The gain of one LNA circuit path is reduced by 25–30 dB when the MEMS switch and active circuitry used within in the same switching branch are switched off to select the other LNA path and minimise power consumption.

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Ramiah, Harikrishnan, U. Eswaran, and J. Kanesan. "A high gain and high linearity class-AB power amplifier for WCDMA applications." Microelectronics International 31, no. 1 (December 20, 2013): 1–7. http://dx.doi.org/10.1108/mi-09-2012-0069.

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Purpose – The purpose of this paper is to design and realize a high gain power amplifier (PA) with low output back-off power using the InGaP/GaAs HBT process for WCDMA applications from 1.85 to 1.91 GHz. Design/methodology/approach – A three stages cascaded PA is designed which observes a high power gain. A 100 mA of quiescent current helps the PA to operate efficiently. The final stage device dimension has been selected diligently in order to deliver a high output power. The inter-stage match between the driver and main stage has been designed to provide maximum power transfer. The output matching network is constructed to deliver a high linear output power which meets the WCDMA adjacent channel leakage ratio (ACLR) requirement of −33 dBc close to the 1 dB gain compression point. Findings – With the cascaded topology, a maximum 31.3 dB of gain is achieved at 1.9 GHz. S11 of less than −18 dB is achieved across the operating frequency band. The maximum output power is indicated to be 32.7 dBm. An ACLR of −33 dBc is achieved at maximum linear output power of 31 dBm. Practical implications – The designed PA is an excellent candidate to be employed in the WCDMA transmitter chain without the aid of additional driver amplifier and linearization circuits. Originality/value – In this work, a fully integrated GaAs HBT PA has been implemented which is capable to operate linearly close to its 1 dB gain compression point.

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Dietz, Marco, Andreas Bauch, Klaus Aufinger, Robert Weigel, and Amelie Hagelauer. "A 1 to 32 GHz broadband multi-octave receiver for monolithic integrated vector network analyzers in SiGe technology." International Journal of Microwave and Wireless Technologies 10, no. 5-6 (June 2018): 717–28. http://dx.doi.org/10.1017/s175907871800079x.

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AbstractA multi-octave receiver chain is presented for the use in a monolithic integrated vector network analyzer. The receiver exhibits a very wide frequency range of 1–32 GHz, where the gain meets the 3 dB-criterion. The differential receiver consists of an ultra-wideband low noise amplifier, an active mixer and an output buffer and exhibits a maximum conversion gain (CG) of 16.6 dB. The main design goal is a very flat CG over five octaves, which eases calibration of the monolithic integrated vector network analyzer. To realize variable gain functionality, without losing much input matching, an extended gain control circuit with additional feedback branch is shown. For the maximum gain level, a matching better than −10 dB is achieved between 1–28 GHz, and up to 30.5 GHz the matching is better than −8.4 dB. For both, the input matching and the gain of the LNA, the influence of the fabrication tolerances are investigated. A second gain control is implemented to improve isolation. The measured isolations between RF-to-LO and LO-to-RF are better than 30 dB and 60 dB, respectively. The LO-to-IF isolation is better than 35 dB. The noise figure of the broadband receiver is between 4.6 and 5.8 dB for 4–32 GHz and the output referred 1-dB-compression-point varies from 0.1 to 4.3 dBm from 2–32 GHz. The receiver draws a current of max. 66 mA at 3.3 V.

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Vitee, Nandini, Harikrishnan Ramiah, Wei-Keat Chong, Gim-Heng Tan, Jeevan Kanesan, and Ahmed Wasif Reza. "50 MHz–10 GHz Low-Power Resistive Feedback Current-Reuse Mixer with Inductive Peaking for Cognitive Radio Receiver." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/683971.

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A low-power wideband mixer is designed and implemented in 0.13 µm standard CMOS technology based on resistive feedback current-reuse (RFCR) configuration for the application of cognitive radio receiver. The proposed RFCR architecture incorporates an inductive peaking technique to compensate for gain roll-off at high frequency while enhancing the bandwidth. A complementary current-reuse technique is used between transconductance and IF stages to boost the conversion gain without additional power consumption by reusing the DC bias current of the LO stage. This downconversion double-balanced mixer exhibits a high and flat conversion gain (CG) of 14.9 ± 1.4 dB and a noise figure (NF) better than 12.8 dB. The maximum input 1-dB compression point (P1dB) and maximum input third-order intercept point (IIP3) are −13.6 dBm and −4.5 dBm, respectively, over the desired frequency ranging from 50 MHz to 10 GHz. The proposed circuit operates down to a supply headroom of 1 V with a low-power consumption of 3.5 mW.

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Shan, Hui Lin, and Yin Sheng Zhang. "Research on Electronic Materials with Design of a Down-Conversion Mixer Based on Particle Swarm Optimization Algorithm." Advanced Materials Research 771 (September 2013): 173–77. http://dx.doi.org/10.4028/www.scientific.net/amr.771.173.

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This paper presents principles of a down-converted mixer for four sub-harmonic and proposes a particle swarm optimization algorithm as a global search algorithm, and the performance equation is used as the assessment of the mixer circuit optimization method. Dielectric substrate adopts Electronic Materials with RF/Duroid 5880 whose dielectric constant is 2.20 and 5mil in thickness. The optimization algorithm can quickly get optimal results. The simulation results show that this mixer achieves higher 1 dB compression point, loss of frequency conversion which is less than 15 dB and good linearity.

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Carls, Joerg, Frank Ellinger, Yulin Zhang, Udo Joerges, and Silvan Wehrli. "Analysis and design of an efficient, fully integrated 1–8 GHz traveling wave power amplifier in 180 nm CMOS." International Journal of Microwave and Wireless Technologies 1, no. 5 (September 8, 2009): 415–22. http://dx.doi.org/10.1017/s1759078709990511.

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Traveling wave amplifiers (TWAs) offer the advantage of broadband amplification and a closed set of equations that allow deriving the RF gain by means of treating TWAs as discrete transmission line approximations. Up to now, however, the significant losses associated with CMOS integrated inductors have been neglected. This work presents a new approach for determining the transmission line losses and phase constants that will bring about an enhanced gain prediction accuracy. The theory is verified by means of a realized design example. The working principle of the integrated DC supply inductor is discussed, whose performance is based on the inductors self-resonance effect. When applying a supply voltage Vdd of 2.4 V, the measured compression point P1 dB and the power added efficiency PAE at 2.4 GHz amount to 16.9 dBm and 19.6%, respectively. At 5.5 GHz, a value of 16.6 dBm for P1 dB and an associated PAE of 13.9% are achieved. The peak RF gain for these output power values reaches 11 dB, and values greater than 8 dB are obtained up to 7 GHz.

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Parisi, Alessandro, Giuseppe Papotto, Egidio Ragonese, and Giuseppe Palmisano. "A 1-V 7th-Order SC Low-Pass Filter for 77-GHz Automotive Radar in 28-nm FD-SOI CMOS." Electronics 10, no. 12 (June 18, 2021): 1466. http://dx.doi.org/10.3390/electronics10121466.

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This paper presents a switched capacitor low-pass filter in a 28-nm fully depleted silicon on insulator CMOS technology for 77-GHz automotive radar applications. It is operated at a power supply as low as 1 V and guarantees 5-dB in-band voltage gain while providing out-of-band attenuation higher than 36 dB and a programmable passband up to 30 MHz. A double sampling technique is adopted, which allows high operating frequency to be achieved while saving power. Moreover, low-voltage biasing and common-mode feedback circuits are exploited to guarantee an almost rail-to-rail output voltage swing. The proposed filter provides an output 1-dB compression point as high as 8.7 dBm with a power consumption of 9 mW. To the authors’ knowledge, this is the first SC-based implementation of a low pass filter for automotive radar applications.

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Esposito, Martina, Joseph Rahamim, Andrew Patterson, Matthias Mergenthaler, James Wills, Giulio Campanaro, Takahiro Tsunoda, et al. "Development and characterization of a flux-pumped lumped element Josephson parametric amplifier." EPJ Web of Conferences 198 (2019): 00008. http://dx.doi.org/10.1051/epjconf/201919800008.

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Josephson parametric amplification is a tool of paramount importance in circuit-QED especially for the quantum-noise-limited single-shot read-out of superconducting qubits. We developed a Josephson parametric amplifier (JPA) based on a lumped-element LC resonator, in which the inductance L is composed by a geometric inductance and an array of 4 superconducting quantum interference devices (SQUIDs). We characterized the main figures of merit of the device, obtaining a −3 dB bandwidth BW = 15 MHz for a gain G = 21 dB and a 1 dB compression point P1dB = −115 dBm. The obtained results are promising for the future use of such JPA as the first stage of amplification for single-shot readout of superconducting qubits.

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Pace, Lorenzo, Sergio Colangeli, Walter Ciccognani, Patrick Ettore Longhi, Ernesto Limiti, Remy Leblanc, Marziale Feudale, and Fabio Vitobello. "Design and Validation of 100 nm GaN-On-Si Ka-Band LNA Based on Custom Noise and Small Signal Models." Electronics 9, no. 1 (January 13, 2020): 150. http://dx.doi.org/10.3390/electronics9010150.

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In this paper a GaN-on-Si MMIC Low-Noise Amplifier (LNA) working in the Ka-band is shown. The chosen technology for the design is a 100 nm gate length HEMT provided by OMMIC foundry. Both small-signal and noise models had been previously extracted by the means of an extensive measurement campaign, and were then employed in the design of the presented LNA. The amplifier presents an average noise figure of 2.4 dB, a 30 dB average gain value, and input/output matching higher than 10 dB in the whole 34–37.5 Ghz design band, while non-linear measurements testify a minimum output 1 dB compression point of 23 dBm in the specific 35–36.5 GHz target band. This shows the suitability of the chosen technology for low-noise applications.

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Kiela, Karolis, Marijan Jurgo, Vytautas Macaitis, and Romualdas Navickas. "Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions." Electronics 10, no. 6 (March 19, 2021): 734. http://dx.doi.org/10.3390/electronics10060734.

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This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

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Elkhouly, Mohamed, Chang-Soon Choi, Srdjan Glisic, Frank Ellinger, and J. Christoph Scheytt. "A 60 GHz eight-element phased-array receiver front-end in 0.25 µm SiGe BiCMOS technology." International Journal of Microwave and Wireless Technologies 4, no. 6 (September 20, 2012): 579–94. http://dx.doi.org/10.1017/s1759078712000591.

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This paper presents the design of an eight-element 60 GHz phased-array receiver chip with interference mitigation capability, fabricated in 0.25 μm SiGe BiCMOS technology. Each receiver element contains a low noise amplifier (LNA) and a vector-modulator that supports high-resolution amplitude and phase control. A fully differential power combining network follows the eight elements. The chip also includes an active power divider, a down conversion mixer, and fully integrated 48 GHz PLL to demonstrate the IF down-conversion. With LNA, a phase shifter and hybrid active and passive power combining network, each receiver path achieves 18 dB of gain, 360° phase shift in steps less than 3°, 20 dB amplitude control, and 4 GHz 3 dB-bandwidth and input referred 1 dB compression point P1 dB of each element is of −22 dBm. Each receiver element dissipates in total 132 mW. The phased-array receiver shows more than 25 dB of signal to interference noise ratio, by means of amplitude and phase control.

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PANTOLI, LEONARDO, VINCENZO STORNELLI, and GIORGIO LEUZZI. "TUNABLE ACTIVE FILTERS FOR RF AND MICROWAVE APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 06 (May 14, 2014): 1450088. http://dx.doi.org/10.1142/s0218126614500881.

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In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ≈ 200), a shape factor (30–3 dB) of 2.5, and can be tuned in the range 1800–2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a P1dB compression point of -5 dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4 mW power consumption with a 1.2 V power supply voltage.

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Isikhan, M., and A. Richter. "CMOS low noise amplifiers for 1.575 GHz GPS applications." Advances in Radio Science 7 (May 18, 2009): 145–50. http://dx.doi.org/10.5194/ars-7-145-2009.

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Abstract. This paper presents Low Noise Amplifier (LNA) versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of 1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.

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Öjefors, Erik, Johannes Borngräber, Falk Korndörfer, and Ullrich Pfeiffer. "A subharmonic front-end in SiGe:C technology for 94-GHz imaging arrays." International Journal of Microwave and Wireless Technologies 1, no. 4 (June 22, 2009): 361–68. http://dx.doi.org/10.1017/s1759078709990365.

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The design of a subharmonic downconverter for 94-GHz imaging arrays in SiGe:C technology is presented. A three-stage differential low-noise amplifier (LNA) with lumped matching networks is used together with a subharmonic mixer driven by a single-pole local-oscillator poly-phase network to form the front-end. The LNA yields 15 dB gain at 94 GHz, while the mixer provides 5 dB conversion gain over a 10 GHz IF bandwidth. The integrated downconverter provides 20 dB conversion gain at 94 GHz with an input 1-dB compression point of −31 dBm and has a current consumption of 45 mA at a 3.3 V supply voltage. The total required die area of the complete downconverter (excluding pad frame) is 0.1 mm, thus making it particularly suitable as a front-end in multi-channel receiver systems.

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Michaelsen, Rasmus S., Tom K. Johansen, Kjeld M. Tamborg, Vitaliy Zhurbenko, and Lei Yan. "An X-band Schottky diode mixer in SiGe technology with tunable Marchand balun." International Journal of Microwave and Wireless Technologies 9, no. 5 (September 28, 2016): 965–76. http://dx.doi.org/10.1017/s1759078716001069.

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In this paper, we propose a double balanced mixer with a tunable Marchand balun. The circuit is designed in a SiGe BiCMOS process using Schottky diodes. The tunability of the Marchand balun is used to enhance critical parameters for double balanced mixers. The local oscillator-IF isolation can be changed from –51 to –60.5 dB by tuning. Similarly, the IIP2can be improved from 41.3 to 48.7 dBm at 11 GHz, while the input referred 1-dB compression point is kept constant at 8 dBm. The tuning have no influence on conversion loss, which remains at 8.8 dB at a LO power level of 11 dBm at the center frequency of 11 GHz. The mixer has a 3 dB bandwidth from 8 to 13 GHz, covering the entire X-band. The full mixer has a size of 2050 μm × 1000 μm.

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WANG, SAN-FU, JAN-OU WU, YANG-HSIN FAN, and JHEN-JI WANG. "A MULTI-BAND LOW NOISE AMPLIFIER WITH GAIN FLATNESS AND BANDWIDTH ENHANCEMENT." Journal of Circuits, Systems and Computers 23, no. 02 (February 2014): 1450017. http://dx.doi.org/10.1142/s0218126614500170.

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In this paper, a differential multi-band CMOS low noise amplifier (LNA) is proposed that is operated within a range of 1500–2700 MHz with input matching capacitor switching and gain flatness performance enhancement technique. Traditional multi-band LNAs have poor performances on gain flatness performance. Therefore, we propose a new multi-band LNA which obtain good gain flatness performance by integrating the characteristics of the transistor trans-conductance and LC resonant load. The new LNA can also achieve a tunable frequency at different matching capacitance conditions. The post-layout simulation results shows that the voltage gain is between 19.3 dB and 22.4 dB, the NF is less than 2.5 dB, and the 1-dB compression point is about -5.1 dBm. The LNA consumes 17.79 mW under 1.8 V supply voltage in TSMC 0.18-um RF CMOS process.

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Leite, Bernardo, Eric Kerhervé, and Didier Belot. "12 dBm OCP1dB Millimeter-wave 28 nm CMOS Power Amplifier using Integrated Transformers." Journal of Integrated Circuits and Systems 11, no. 2 (December 28, 2016): 97–105. http://dx.doi.org/10.29292/jics.v11i2.434.

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This paper describes the design of mm-wave integrated transformers and their application within a power amplifier (PA) in a 28 nm CMOS technology. The PA presents a 2-stage common-source differential topology and uses one transformer at the input and another at the output to perform single-ended to differential conversion, as well as another transformer to perform interstage matching. The baluns are sized to provide low insertion losses and high common-mode rejection rate (CMRR) as well as integrating the input and output matching networks. The designed baluns achieve minimum insertion losses better than 0.8 dB and CMRR superior to 27 dB. The output-stage transistors have a measured 1 dB output compression point (OCP1dB) of 10.2 dBm, 10.1 dB gain and peak power added efficiency (PAE) as high as 35%. Thanks to the transformers, the PA presents a compact implementation, occupying only 0.037 mm² on silicon. The fabricated PA achieves 12 dBm OCP1dB, 15.3 dB gain and peak PAE better than 20%.

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Zhang, Wei Jia, and Bo Wang. "A SiGe HBT Variable Gain Amplifier for Wireless Receiver System with On-Chip Filter." Applied Mechanics and Materials 155-156 (February 2012): 167–70. http://dx.doi.org/10.4028/www.scientific.net/amm.155-156.167.

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A using SiGe HBT variable gain amplifier (VGA) with filtering for wireless receiver system is presented in this paper. The VGA consists of three stages. The first stage is the gain control stage, and the second stage is the fixed gain stage. The third is the GM-C filter. The VGA is driven by a 3.3-V power supply, and linear gain control range varying is from 26 dB to 62dB. When control voltage varies from 0 to 1.8V. The input 1-dB compression point is -4dBm at minimum gain. The VGA is fabricated in a 0.5 μm = 80GHz and =90GHz silicon germanium heterojunction transistor technology.

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Zhu, Chen, Huang, Wang, and Yu. "A High-Efficiency K-band MMIC Linear Amplifier Using Diode Compensation." Electronics 8, no. 5 (April 30, 2019): 487. http://dx.doi.org/10.3390/electronics8050487.

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This paper describes the design and measured performance of a high-efficiency and linearity-enhanced K-band MMIC amplifier fabricated with a 0.15 μm GaAs pHEMT processing technology. The linearization enhancement method utilizing a parallel nonlinear capacitance compensation diode was analyzed and verified. The three-stage MMIC operating at 20–22 GHz obtained an improved third-order intermodulation ratio (IM3) of 20 dBc at a 27 dBm per carrier output power while demonstrating higher than a 27 dB small signal gain and 1-dB compression point output power of 30 dBm with 33% power added efficiency (PAE). The chip dimension was 2.00 mm × 1.40 mm.

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Lioe, De Xing, Suhaidi Shafie, Harikrishnan Ramiah, and Gim Heng Tan. "Low Power Upconversion Mixer for Medical Remote Sensing." Scientific World Journal 2014 (2014): 1–5. http://dx.doi.org/10.1155/2014/923893.

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This work presents the design of a low power upconversion mixer adapted in medical remote sensing such as wireless endoscopy application. The proposed upconversion mixer operates in ISM band of 433 MHz. With the carrier power of −5 dBm, the proposed mixer has an output inferred 1 dB compression point of −0.5 dBm with a corresponding output third-order intercept point (OIP3) of 7.1 dBm. The design of the upconversion mixer is realized on CMOS 0.13 μm platform, with a current consumption of 594 μA at supply voltage headroom of 1.2 V.

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Öjefors, Erik, Franck Pourchon, Pascal Chevalier, and Ullrich R. Pfeiffer. "A 160-GHz low-noise downconversion receiver front-end in a SiGe HBT technology." International Journal of Microwave and Wireless Technologies 3, no. 3 (March 15, 2011): 347–53. http://dx.doi.org/10.1017/s1759078711000201.

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A 160-GHz SiGe-HBT (Heterojunction Bipolar Transistor) down-conversion receiver front-end for use in active millimeter-wave imaging arrays and D-band communication applications is presented. The monolithic front-end consists of a three-stage low-noise amplifier providing 24 dB of gain and a Gilbert-cell mixer capable of operating from a −8-dBm LO signal. A fully differential architecture compatible with balanced on or off-chip antennas is used to avoid the need for on-chip baluns in antenna-integrated applications. The implemented downconversion front-end consumes 50 mA from a 3.3 V supply and requires a 0.1 mm2 die area (excl. pads) per channel. With a 160-GHz input signal and an Intermediate Frequency (IF) of 1 GHz, the implemented front-end yields a 25-dB conversion gain, a −30-dBm input compression point, and a 9-dB/7-dB (with/without auxiliary on-chip input balun) system noise figure.

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Sakalas, Mantas, Niko Joram, and Frank Ellinger. "A 1.5–40 GHz frequency modulated continuous wave radar receiver front-end." International Journal of Microwave and Wireless Technologies 13, no. 6 (February 18, 2021): 532–42. http://dx.doi.org/10.1017/s1759078721000118.

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AbstractThis study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$.

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Forstner, Hans Peter, Markus Ortner, Ludger Verweyen, and Herbert Knapp. "A homodyne transceiver MMIC using SiGe:C technology for 60 GHz wireless applications." International Journal of Microwave and Wireless Technologies 3, no. 2 (April 2011): 147–55. http://dx.doi.org/10.1017/s1759078711000390.

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A highly integrated transceiver microwave monolithic integrated circuit (MMIC) manufactured in a 200-GHz SiGe:C production technology is presented, applicable for sensing- and broadband communication applications. To simplify the analog frontend, the fully differential design is based on a homodyne architecture. It comprises an LO signal generation unit based on a wideband 60 GHz fundamental Voltage Controlled Oscillator (VCO) and an on-chip prescaler, covering the full operational frequency band of 57–64 GHz. Within this bandwidth, the upconverter exhibits an upconversion gain of 23.6–26.4 dB and a maximum output-referred 1-dB compression point of 14 dBm. The downconverter provides a Double Sideband (DSB) noise figure of 9–12 dB with a downconversion gain of 37–71 dB. On chip AC-coupling of the receiver IF-output with a lower −3 dB cut-off frequency as low as 16 kHz eliminates mixer DC-offsets and enables on-chip Intermediate Frequency (IF) amplification. The whole transceiver MMIC draws a current of 415 mA from a single 3.3 V supply and requires few components externally to the chip.

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Li, Kang, Guo Dong Huang, Xiao Feng Yang, Qian Feng, Chao Xian Zhu, and Chi Liu. "A Fully Integrated S-Band Power Amplifier in 0.35um-SiGe BiCMOS Technology." Advanced Materials Research 403-408 (November 2011): 2481–84. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.2481.

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A fully integrated S-band high efficiency power amplifier using the TSMC 0.35 um SiGe BiCMOS technology is presented. The two-stage power amplifier has been optimized for the whole S-band covering 2 GHz to 4 GHz frequency band for higher 1-dB compression point and efficiency. The input and output matching networks are designed on chip. From the simulate result, the two-stage power amplifier achieves high PAE of 28% and saturation output power of 23.3 dBm at 3 GHz, with the small signal gain of 18.7 dB. Besides, this PA realizes the PAE within the band of 2.4GHz to 4GHz exceed 25%, and the highest PAE of 30.6% at 3.4 GHz.

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40

Lahiji, Rosa R., Linda P. B. Katehi, and Saeed Mohammadi. "A wideband CMOS distributed amplifier with slow-wave shielded transmission lines." International Journal of Microwave and Wireless Technologies 3, no. 1 (November 15, 2010): 59–66. http://dx.doi.org/10.1017/s1759078710000772.

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A four-stage distributed amplifier utilizing low-loss slow-wave shielded (SWS) transmission lines is implemented in a standard 0.13 μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The amplifier when biased in its high current operating mode of IDtotal = 46 mA (at Vdd = 2.2 V, Pdiss = 101 mW) provides a forward transmission gain of 11.3 ± 1.5 dB with a 3-dB bandwidth of 17 GHz and a gain-bandwidth product of 74 GHz. The noise figure (NF) under the same bias condition is better than 8.5 dB up to 10 GHz. The measured output-referred 1-dB compression point is higher than +2 dBm. The amplifier is also measured under low-bias condition of IDtotal = 18 mA (at Vdd = 1.15 V, Pdiss = 20.7 mW). It provides a transmission gain of 6.6 ± 1 dB, a 3-dB bandwidth of 14.8 GHz, a gain-bandwidth product of 35.5 GHz, and a NF of better than 8.6 dB up to 10 GHz. Despite using a simple four-stage cascode design, this distributed amplifier achieves very high-gain-bandwidth product at a relatively low DC power compared to the state of the art CMOS distributed amplifiers reported in the literature. This is due to the incorporation of low-loss SWS coplanar waveguide (CPW) transmission lines with a loss factor of nearly 50% of that of standard transmission lines on CMOS-grade Si substrate.

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Qi, Tian, Songbai He, Cheng Zhong, and Zhitao Zhu. "Design of a Ku-band MMIC LNA with a Simple T-type Input Matching Network." Journal of Circuits, Systems and Computers 29, no. 11 (January 6, 2020): 2020006. http://dx.doi.org/10.1142/s0218126620200066.

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In this paper, the design of a wideband monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) fabricated in 0.13-[Formula: see text]m GaAs pHEMT process is presented. A simple T-type input matching network (IMN) and a source feedback structure are employed to achieve low noise figure (NF). The MMIC LNA, which operates across 12–18[Formula: see text]GHz, can be used for satellite applications. Experimental results show an NF around 1.5[Formula: see text]dB in 12–17.5[Formula: see text]GHz and a minimum NF of 1.21[Formula: see text]dB at 16.5[Formula: see text]GHz. In addition, a flat small-signal gain of [Formula: see text][Formula: see text]dB is achieved at 13.5–17.5[Formula: see text]GHz. The input return loss is lower than [Formula: see text] dB at 12–14.5[Formula: see text]GHz and the output return loss is lower than [Formula: see text] dB at 12–17[Formula: see text]GHz. The power consumed is lower than 0.3[Formula: see text]W and the [Formula: see text] (1-dB compression point) output power is around 13[Formula: see text]dBm.

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Hiemstra, S. Reza, Brannon M. Kerrigan, and Dong S. Ha. "A High Temperature Linear Wideband Power Amplifier for a Downhole Communication System." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, HiTEN (July 1, 2017): 000114–17. http://dx.doi.org/10.4071/2380-4491.2017.hiten.114.

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Abstract In order to reach previously untapped wells, the oil and gas industry continues to drill deeper, resulting in extreme operating temperatures for electronic systems. It is essential for electronic circuits and systems to be able to withstand extreme temperatures. The proposed power amplifier (PA) intends for a downhole communication system operating at an ambient temperature of 230 °C. The proposed PA is designed with Qorvo T2G6003028-FL GaN on SiC HEMT, which offers a high junction temperature. The proposed PA can operate reliably up to an ambient temperature of 230 °C with the operation frequency from 228 MHz to 263 MHz. At 230 °C, it achieves maximum output power of 1.66 W, the peak gain of 24 dB, peak PAE (power added efficiency) of 25%, OP1dB (output 1-db compression point) of 32 dBm, and OIP3 (output third intercept point) of 37.9 dBm..

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Zheng, Chun-Yi, Wen-Jung Chiang, Yeong-Lin Lai, Edward Y. Chang, Shen-Li Chen, and K. B. Wang. "Characteristics of GaAs Power MESFETs with Double Silicon Ion Implantations for Wireless Communication Applications." Open Materials Science Journal 10, no. 1 (June 15, 2016): 29–36. http://dx.doi.org/10.2174/1874088x01610010029.

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GaAs power metal-semiconductor field-effect transistors (MESFETs) were fabricated using direct double silicon (Si) ion implantation technology for wireless communication applications. A 150-µm MESFET had a saturation drain current of 238 mA/mm after Si3N4passivation. A 15-mm MESFET, when measured under a class-AB condition with a biased drain voltage of 3.4 V and a quiescent drain current of 600 mA, delivered a maximum output power (Pout) of 31.1 dBm and a maximum power-added efficiency (PAE) of 58.0% at a frequency of 1.88 GHz. The MESFET exhibited aPoutof 29.2 dBm with a PAE of 45.0% at the 1-dB gain compression point. The MESFET, when measured under a deep class-B condition with a biased drain voltage of 4.7 V and a quiescent drain current of 50 mA, achieved a maximumPoutof 33.1 dBm and a maximum PAE of 55.9% at 1.88 GHz. The MESFET operating at 4.7 V and 1.88 GHz exhibited aP1dBof 31.8 dBm and an associated PAE of 47.1% at the 1-dB gain compression point. When tested by IS-95 code-division multiple access (CDMA) standard signals and biased at 4.7 V under the deep class-B condition, the MESFET with aPoutof 28 dBm demonstrated an adjacent channel power rejection (ACPR) of –31.2 dBc at +1.25 MHz apart from the 1.88 GHz center frequency and –45.7 dBc at +2.25 MHz.

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44

Choe, Young-Joe, Hyohyun Nam, and Jung-Dong Park. "A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology." Electronics 8, no. 9 (September 17, 2019): 1043. http://dx.doi.org/10.3390/electronics8091043.

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We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push–pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Ω load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm2 without pads.

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45

Michaelsen, Rasmus S., Tom K. Johansen, Kjeld M. Tamborg, and Vitaliy Zhurbenko. "Design of a broadband passive X-band double-balanced mixer in SiGe HBT technology." International Journal of Microwave and Wireless Technologies 6, no. 3-4 (March 12, 2014): 235–42. http://dx.doi.org/10.1017/s1759078714000191.

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In this paper, a passive double-balanced mixer in SiGe HBT technology is presented. Owing to lack of suitable passive mixing elements in the technology, the mixing elements are formed by diode-connected HBTs. The mixer uses lumped element Marchand baluns on both the local oscillator (LO) and the radio frequency (RF) port. A break out of the Marchand balun is measured. This demonstrates good phase and magnitude match of 0.7° and 0.11 dB, respectively. The Marchand baluns are broadband with a measured 3 dB bandwidth of 6.4 GHz, while still having a magnitude imbalance better than 0.4 dB and a phase imbalance better than 5°. Unfortunately with a rather high loss of 2.5 dB, mainly due to the low Q-factor of the inductors used. The mixer is optimized for use in doppler radars and is highly linear with a 1 dB compression point above 12 dBm IIP2of 66 dBm. The conversion gain at the center frequency of 8.5 GHz is −9.8 dB at an LO drive level of 15 dBm. The whole mixer is very broadband with 3 dB bandwidth from 7 to 12 GHz covering the entire X-band. The LO–IF, RF–IF, and RF–LO isolation is better than 46, 36, and 36 dB, respectively, in the entire band of operation.

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46

Galaviz-Aguilar, Jose Alejandro, Cesar Vargas-Rosales, José Ricardo Cárdenas-Valdez, Yasmany Martínez-Reyes, Everardo Inzunza-González, Yuma Sandoval-Ibarra, and José Cruz Núñez-Pérez. "A Weighted Linearization Method for Highly RF-PA Nonlinear Behavior Based on the Compression Region Identification." Applied Sciences 11, no. 7 (March 25, 2021): 2942. http://dx.doi.org/10.3390/app11072942.

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In this paper, we present an adaptive modeling and linearization algorithm using the weighted memory polynomial model (W-MPM) implemented in a chain involving the indirect learning approach (ILA) as a linearization technique. The main aim of this paper is to offer an alternative to correcting the undesirable effect of spectral regrowth based on modeling and linearization stages, where the 1-dB compression point (P1dB) of a nonlinear device caused by memory effects within a short time is considered. The obtained accuracy is tested for a highly nonlinear behavior power amplifier (PA) properly measured using a field-programmable gate array (FPGA) system. The adaptive modeling stage shows, for the two PAs under test, performances with accuracies of −32.72 dB normalized mean square error (NMSE) using the memory polynomial model (MPM) compared with −38.03 dB NMSE using the W-MPM for the (i) 10 W gallium nitride (GaN) high-electron-mobility transistor (HEMT) radio frequency power amplifier (RF-PA) and of −44.34 dB NMSE based on the MPM and −44.90 dB NMSE using the W-MPM for (ii) a ZHL-42W+ at 2000 MHz. The modeling stage and algorithm are suitably implemented in an FPGA testbed. Furthermore, the methodology for measuring the RF-PA under test is discussed. The whole algorithm is able to adapt both stages due to the flexibility of the W-MPM model. The results prove that the W-MPM requires less coefficients compared with a static model. The error vector magnitude (EVM) is estimated for both the static and adaptive schemes, obtaining a considerable reduction in the transmitter chain. The development of an adaptive stage such as the W-MPM is ideal for digital predistortion (DPD) systems where the devices under test vary their electrical characteristics due to use or aging degradation.

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47

Ho, Stanley S. K., and Carlos E. Saavedra. "A 5.4 GHz Fully-Integrated Low-Noise Mixer." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 18–24. http://dx.doi.org/10.29292/jics.v6i1.334.

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An active mixer using a Gilbert-cell topology that incorporates a low-noise RF transconductance stage is presented in this paper. The chip operates at a frequency of 5.4 GHz and was fabricated in 180 nm CMOS technology. A current-bleeding circuit is used to provide different dc bias currents to the LO switching stage and the RF transconductors. The transconductor, designed using the power constrained simultaneous noise and input match technique, together with the bleeding circuit enables the mixer to have a measured single-sideband noise figure of 7.8 dB and a power conversion gain of 13.1 dB. The measured input-referred 1-dB compression point, IP1dB is -17.8 dBm while its OP1dB is -5 dBm. A two-tone test was carried out and the mixer exhibits an IIP3 of -6.2 dBm and an OIP3 of +6.9 dBm. All of the inductors are on-chip and the size of the mixer core is only 380 μm x 350 μm (0.133 mm2).

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48

Aikio, Janne P., Alok Sethi, Mikko Hietanen, Jere Rusanen, Timo Rahkonen, and Aarno Pärssinen. "Ka-Band Stacked Power Amplifier Supporting 3GPP New Radio FR2 Band n258 Implemented Using 45 nm CMOS SOI." Applied Sciences 11, no. 15 (July 22, 2021): 6708. http://dx.doi.org/10.3390/app11156708.

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This paper presents a fully integrated, four-stack, single-ended, single stage power amplifier (PA) for millimeter-wave (mmWave) wireless applications that was fabricated and designed using 45 nm complementary metal oxide semiconductor silicon on insulator (CMOS SOI) technology. The frequency of operation is from 20 GHz to 30 GHz, with 13.7 dB of maximum gain. The maximum RF (radio frequency) output power (Pout), power-added efficiency (PAE) and output 1 dB compression point are 20.5 dBm, 29% and 18.8 dBm, respectively, achieved at 24 GHz. The error vector magnitude (EVM) of 12.5% was measured at an average channel power of 14.5 dBm at the center of the the 3GPP/NR (third generation partnership project/new radio) FR2 band n258—i.e., 26 GHz—using a 100 MHz 16-quadrature amplitude modulation (QAM) 3GPP/NR orthogonal frequency division modulation (OFDM) signal.

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Wu, Tianxiang, Jipeng Wei, Hongquan Liu, Shunli Ma, Yong Chen, and Junyan Ren. "A Sub-6G SP32T Single-Chip Switch with Nanosecond Switching Speed for 5G Applications in 0.25 μm GaAs Technology." Electronics 10, no. 12 (June 19, 2021): 1482. http://dx.doi.org/10.3390/electronics10121482.

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This paper presents a single-pole 32-throw (SP32T) switch with an operating frequency of up to 6 GHz for 5G communication applications. Compared to the traditional SP32T module implemented by the waveguide package with large volume and power, the proposed switch can significantly simplify the system with a smaller size and light weight. The proposed SP32T scheme utilizing tree structure can dramatically reduce the dc power and enhance isolation between different output ports, which makes it suitable for low-power 5G communication. A design methodology of a novel transmission (ABCD) matrix is proposed to optimize the switch, which can achieve low insertion loss and high isolation simultaneously. The average insertion loss and the isolations are 1.5 and 35 dB at 6 GHz operating frequency, respectively. The switch exhibits the measured input return loss which is better than 10 dB at 6 GHz. The 1 dB input compression point of SP32T is 15 dBm. The prototype is designed in 5 V 0.25 μm GaAs technology and occupies a small area of 12 mm2.

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Xue, Jiawen, Li Yin, Zehua Lan, Mingzhu Long, Guolin Li, Zhihua Wang, and Xiang Xie. "3D DCT Based Image Compression Method for the Medical Endoscopic Application." Sensors 21, no. 5 (March 5, 2021): 1817. http://dx.doi.org/10.3390/s21051817.

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This paper proposes a novel 3D discrete cosine transform (DCT) based image compression method for medical endoscopic applications. Due to the high correlation among color components of wireless capsule endoscopy (WCE) images, the original 2D Bayer data pattern is reconstructed into a new 3D data pattern, and 3D DCT is adopted to compress the 3D data for high compression ratio and high quality. For the low computational complexity of 3D-DCT, an optimized 4-point DCT butterfly structure without multiplication operation is proposed. Due to the unique characteristics of the 3D data pattern, the quantization and zigzag scan are ameliorated. To further improve the visual quality of decompressed images, a frequency-domain filter is proposed to eliminate the blocking artifacts adaptively. Experiments show that our method attains an average compression ratio (CR) of 22.94:1 with the peak signal to noise ratio (PSNR) of 40.73 dB, which outperforms state-of-the-art methods.

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Journal articles on the topic '1 dB compression point'

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