Academic literature on the topic '10-bit'
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Journal articles on the topic "10-bit"
Sugimoto, Y., and S. Mizoguchi. "An experimental BiCMOS video 10 bit ADC." IEEE Journal of Solid-State Circuits 24, no. 4 (1989): 997–99. http://dx.doi.org/10.1109/4.34083.
Full textFarr, W., L. B. Levit, and U. A. Uhmeyer. "100 MHz 10-Bit Image Chamber Analyzers." IEEE Transactions on Nuclear Science 32, no. 1 (1985): 636–39. http://dx.doi.org/10.1109/tns.1985.4336912.
Full textZhang, Yulin, Guiliang Guo, Yuepeng Yan, and Tao Yang. "Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network." International Journal of Computer Theory and Engineering 6, no. 6 (December 2014): 443–46. http://dx.doi.org/10.7763/ijcte.2014.v6.906.
Full textTsai, C. C., C. H. Lai, W. T. Lee, and J. O. Wu. "10-bit switched-current digital-to-analogue converter." IEE Proceedings - Circuits, Devices and Systems 152, no. 3 (2005): 287. http://dx.doi.org/10.1049/ip-cds:20040562.
Full textGAO Yuan, 高原, 魏廷存 WEI Ting-cun, and 李博 LI Bo. "Design of 10-bit TFT-LCD Source Driver Circuit." Chinese Journal of Liquid Crystals and Displays 26, no. 6 (2011): 808–12. http://dx.doi.org/10.3788/yjyxs20112606.0808.
Full textSon, Jisu, Han-Yeol Lee, Yeong-Woong Kim, and Young-Chan Jang. "A 10-bit 10-MS/s SAR ADC with a Reference Driver." Journal of the Korea Institute of Information and Communication Engineering 20, no. 12 (December 31, 2016): 2317–25. http://dx.doi.org/10.6109/jkiice.2016.20.12.2317.
Full textLee, Byunghun, Ki-Duk Kim, Yong-Joon Jeon, Sung-Woo Lee, Jin-Yong Jeon, Seung-Chul Jung, Jun-Hyeok Yang, Kyu-Sung Park, and Gyu-Hyeong Cho. "27.2: A Buffer Amplifier with Embodied 4-Bit Interpolation for 10-Bit AMLCD Column Drivers." SID Symposium Digest of Technical Papers 40, no. 1 (2009): 371. http://dx.doi.org/10.1889/1.3256790.
Full textLu, Chih-Wen, Ching-Min Hsiao, Yo-Sheng Lin, and Mau-Chung Frank Chang. "A 10-Bit DAC With 1.6-Bit Interpolation Cells for Compact LCD Column Driver ICs." Journal of Display Technology 9, no. 3 (March 2013): 176–83. http://dx.doi.org/10.1109/jdt.2012.2236679.
Full textWoo, Jong-Kwan, Dong-Yong Shin, Won-Jun Choe, Deog-Kyoon Jeong, and Suhwan Kim. "58.4: 10-Bit Column Driver with Split-DAC Architecture." SID Symposium Digest of Technical Papers 39, no. 1 (2008): 892. http://dx.doi.org/10.1889/1.3069817.
Full textShehata, Khaled, Saleh Eisa, Hani Fikry, and Tarif Elshafiey. "DESIGN OF A 10-BIT NON-LINEAR INTERPOLATION DAC." International Conference on Electrical Engineering 5, no. 5 (May 1, 2006): 1–7. http://dx.doi.org/10.21608/iceeng.2006.33530.
Full textDissertations / Theses on the topic "10-bit"
Verma, Ashutosh. "A 10-Bit 500-MHz 55-mW CMOS ADC." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=1835634861&sid=3&Fmt=2&clientId=1564&RQT=309&VName=PQD.
Full textKommareddy, Jeevani. "10-bit C2C DAC Design in 65nm CMOS Technology." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1565538915029852.
Full textGuo, Wei. "A low-power 10-bit 50 MS/s CMOS successive approximation register ADC." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43200.
Full textChung, Hong-Yi, and 鐘鴻儀. "A 10-bit Successive Approximation ADC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57183272659084856815.
Full text國立暨南國際大學
電機工程學系
98
Propose a fully differentially successive approximation ADC with a binary-weighted capacitor array networks. Add bootstrapped switches to accelerate charging to the capacitor networks in front of this architecture, and decrease the settling time of capacitor array. Also keep circuit operate correctly under low supply voltage driving switches. Use asynchronous control logic to generate the necessary clock signals internally, rather then provide clocks by external clock generator. Unit capacitors of the capacitor array are laid out in a common-centroid scheme to reduce the undercutting effect, for achieving the correct ratio of capacitor array. According to the result of simulation , the proposed ADC is designed to operate at 5Ms/s.Signal-to-noise and distortion ratio is 58.696dB, under the frequency of input signal is 2.5Mhz, the effective number of bit is 9.458 bit. The integral nonlinearity (INL) is 1.9 LSB. The differential nonlinearity (DNL) is 1.85 LSB. The power consumption is 5.3mW. Layout area of this architecture is 1080um * 880um.
Huang, Ju-Lin, and 黃筑琳. "Design of 6-bit Flash ADC and 10-bit voltage-segmented DAC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/48178620065010904456.
Full text國立暨南國際大學
電機工程學系
98
Two converters are proposed in this thesis. The first one is a 6-bit flash analog-to-digital converter (ADC), and the second one is a 10-bit voltage-type digital-to-analog converter (DAC) for Thin Film Transistor Liquid Crystal Display (TFT-LCD) source driver. The 6-bit flash ADC is designed in TSMC 0.18μm process technology. The sampling rate is 2GSapmle/s, and the supply voltage is 1.8 Volt. In this work, the “fully differential” structure is adopted and each sub-circuit is well-designed (sophisticated designed) to get more benefit of the overall performance, including a track-and-hold circuit with better linearity, preamplifiers with the reset switches, and the comparator with diode-connected transistors added at the output to limit the output swing. The second circuit, a 10-bit DAC, is designed in TSMC 0.35μm process technology. A new voltage-segmented DAC which combines a 4-bit DAC embedded operational amplifier is proposed. Two adjacent voltage levels, VH and VL, are selected from two 6-bit tree decoders, and then the 4-bit DAC embedded operational amplifier divides this voltage range into 16 segments. As a result, the 10-bits resolution can be achieved by this architecture. The source driver of LCD displayers implemented with the proposed 10-bit DAC shrinks the layout by more than 50% and greatly reduces costs.
Jian-Feng, Shiu. "A 10-bit 250MS/s pipelined ADC." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-3101200716423100.
Full textChao, Hao-tsun, and 趙浩淳. "A 10-Bit Area-Efficient SAR ADC." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/69383844125227169450.
Full text國立暨南國際大學
電機工程學系
100
In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref±ΔV for reducing dramatically the ADC’s area. The 2N resolution is achieved by the N bit SAR ADC. In order to resolve the kickback noise, a cascode common gate amplifier is used in the comparator. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ADC simulation achieves a SNDR of 60.6dB and ENOB of 9.767 bit when operating at 14MS/s. The measured SNDR is 29.79dB, the ENOB is 4.66.
Tseng, Hua-Wei, and 曾華偉. "2b/cycle-Assisted 10-bit SAR ADCs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/p7ddqf.
Full text國立臺灣科技大學
電子工程系
106
This thesis presents 2b/cycle-assisted 10-bit successive approximation register (SAR) analog-to-digital converters (ADCs). By applying 2b/cycle-assisted architecture, it reduces the number of conversion cycles and thus speeds up the ADC operation. The proposed dynamic register (MdREG) circuit cuts down the delay from the comparator output to the DAC switches. It also helps the ADC operate at higher sampling rates. Dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. It also reduces the total capacitance of the digital-to-analog converter (DAC). The offset calibration scheme is proposed to effectively alleviate the degradation of the ADC linearity. Two ADCs were implemented based on the proposed 2b-1b/cycle configuration. A 10-bit 100-MS/s SAR ADC was fabricated using a 180 nm CMOS technology. This ADC occupies an active area of 0.07 mm2. Operating at 100-MS/s, the ADC consumes 7.4 mW from a 1.9 V supply. The peak DNL and INL are -0.56/+0.67 LSB and -0.75/+0.79 LSB respectively. The measured Nyquist SNDR and SFDR are 52.2 dB and 75.2 dB respectively. Another 10-bit 500-MS/s ADC was implemented in 40nm CMOS. Operating at 500-MS/s, the ADC consumes 1.84 mW from a 0.9 V supply. The simulated Nyquist SNDR and SFDR are 59.6 dB and 76 dB respectively.
Lo, Wei-Lun, and 羅偉綸. "An 8-Bit 10-GS/s DAC." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/h4p9k2.
Full text國立交通大學
電子研究所
106
In communication systems, most of data stream is performed in the digital domain, but the signal carrying data stream must be transmitted by analog signals. As a result, digital-to-analog(DA) and analog-to-digital(AD) converters are necessary to be utilized. The quality of data converters usually limits the accuracy and speed of overall system. Therefore, if data converters are equiped with the characteristics of high wide band and high dynamic range, communication system will transmit data in high-end quality and high speed. This thesis focuses on the Digital-to-Analog Converters(DACs). The current-steering structure has been widely used in high-speed DACs because its can be easily achieved in high sampling speed. However, the nonideal switching limits the bandwidth of spurious-free dynamic range(SFDR). SFDR reduces rapidly while input frequency increases. Therefore, conventional current-steering structure are optimized and applied to maintain high SFDR at high sampling rate frequency. In this work, a CMOS 8-BIT 10GS/s was fabricated in a 28nm CMOS technology. In post-simulation, the DAC achieves a SFDR better than 50dB for a sinewave input frequency 1.5GHz, and better than 40 dB up to 4.5GHz. Its power consumption is roughly 140mW of power. In the design of high-accuracy current-steering DACs, current sources with high matching property are required but the penalty is large area. Larger area of current sources will enhence the value of intrinsic and parasitic capacitor loading and cause the degradation of signl bandwidth. The way to reduce capacitor loading is utilize compact current cells but compact ones have larger mismatch properties. Therefore, practical simulation is necessary to find and fit the size of current sources with high-quality matching properties and low intrinsic capacitor loading.
Hsu, Chia-Hao, and 許家豪. "A 10-bit High-Speed Subrange ADC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/74555666386339650556.
Full text國立臺灣大學
電子工程學研究所
102
A low-noise phase-detector-based (PD-based) comparator is proposed for subrange analog-to-digital converters (ADCs) in this thesis. It can reduce the thermal-induced noise as well as the probability of the metastability. The 10-bit subrange ADC is composed of a 3.9-bit flash ADC and a 7-bit SAR ADC. The proposed ADC was fabricated in a 40-nm LP CMOS technology. The ADC achieves 54.41-dB SNDR at 160MS/s under a 1.1V supply voltage and consumes 2.7mW. The figure-of-merit (FOM) is 39.4 fJ/conversion-step. The active area is 0.0475 mm2.
Books on the topic "10-bit"
Hamedi-Hagh, Sotoudeh. A 10 bit, 50 MS/s, low-power pipelined A/D converter for cable modem applications. Ottawa: National Library of Canada, 2001.
Find full textPapanikolaou, Vaskis. A comparator and track and hold for use in a 1 GS/s, 10 bit analog to digital converter. Ottawa: National Library of Canada, 1999.
Find full textRéunion, du BIT/PECTA des planificateurs africains de l'emploi (1990 Lagos Nigeria). Relancer le développement à visage humain: Agenda pour l'afrique au cours des années 90 : rapport de la deuxième réunion biennale BIT/PECTA des planificateurs africains de l'emploi, Lagos (Nigeria) 10-14 December 1990. Addis Abéba: Programme des emplois et des compétences techniques pour l'Afrique, 1992.
Find full textWang, Robert. A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology. 2004.
Find full textGupta, Shivani. A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate. 1995.
Find full textGupta, Shivani. A 1-m W, 14-bit [sigma] [delta] A/D converter with 10-KHz conversion rate. 1995.
Find full textNotebook, Hippo. Notebook: Pixel Video Game Hippopotamus Gaming 16 Bit Kids - 50 Sheets, 100 Pages - 8 X 10 Inches. Independently Published, 2020.
Find full textST 2036-4:2015: Ultra High Definition Television — Multi-link 10 Gb/s Signal/Data Interface Using 12-Bit Width Container. 3 Barker Avenue., White Plains, NY 10601: The Society of Motion Picture and Television Engineers SMPTE, 2015. http://dx.doi.org/10.5594/smpte.st2036-4.2015.
Full textJournals, Royal. Little Bit Older and a Lot More Fabulous Happy 44th Birthday: Lined Journal / Notebook 44th Birthday Gift, Cute Design and Funny Present under 10 Dollars for 44 Years Old Women, Girl, Sister, Daughter, Wife, 120 Pages, 6 X 9, Soft Cover, Matt Finish. Independently Published, 2020.
Find full textBook chapters on the topic "10-bit"
Hsieh, Chin-Fa, Chun-Sheng Chen, and Jimmy Lin. "10 Bit 1.5b/Stage Pipeline ADC Design for Video Application." In Lecture Notes in Electrical Engineering, 601–7. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-04573-3_75.
Full textHaas, M. "Hochgenaue CMOS A/D-Umsetzer mit 8 und 10 bit Auflösung." In Mikroelektronik 87, 40–45. Vienna: Springer Vienna, 1987. http://dx.doi.org/10.1007/978-3-7091-8940-5_6.
Full textGuiard, Yves, Frédéric Bourgeois, Denis Mottet, and Michel Beaudouin-Lafon. "Beyond the 10-bit Barrier: Fitts’ Law in Multi-Scale Electronic Worlds." In People and Computers XV—Interaction without Frontiers, 573–87. London: Springer London, 2001. http://dx.doi.org/10.1007/978-1-4471-0353-0_36.
Full textBult, Klaas, and Aaron Buchwald. "An Embedded 170-mW 10-Bit 50-MS/s CMOS ADC in 1-mm2." In Analog Circuit Design, 49–63. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2602-2_3.
Full textSin, Sai-Weng, Seng-Pan U, and Rui Paulo Martins. "Design of a 1.2 V, 10-bit, 60–360 MHz Time-Interleaved Pipelined ADC." In Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters, 75–95. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9710-1_5.
Full textBrandt, Brian, and Joseph Lutsky. "A 10-bit, 20–30 MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist." In Analog Circuit Design, 75–94. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-3198-9_4.
Full textHosur, Kalmeshwar N., Girish V. Attimarad, Harish M. Kittur, Gopalkrishna G. Mane, and S. S. Kerur. "Design and Analysis of 10-bit, 2 MS/s SAR ADC Using Nonredundant SAR and Split DAC." In Lecture Notes in Electrical Engineering, 803–10. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8234-4_65.
Full textKhanoyan, K., F. Behbahani, and A. A. Abidi. "A 400-MHz, 10-bit Charge Domain CMOS D/A Converter for Low-Spurious Frequency Synthesis." In Analog Circuit Design, 233–46. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/0-306-47950-8_12.
Full textAlshimaysawe, Ihsan A., Hayder Fadhil Abdulsada, Saif H. Abdulwahed, Mohannad A. M. Al-Ja’afari, and Ameer H. Ali. "Comparison of Several Data Representations for a Single-Channel Optic System with 10 Gbps Bit Rate." In Research in Intelligent and Computing in Engineering, 89–98. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-7527-3_9.
Full textMekkattillam, Yadukrishnan, Satyajit Mohapatra, and Nihar R. Mohapatra. "Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications." In Communications in Computer and Information Science, 590–604. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8_49.
Full textConference papers on the topic "10-bit"
Donkor, Eric, J. J. Green, Michael J. Hayduk, and Rebecca J. Bussjager. "10 GSPS 10-bit optical analog-to-digital converter." In AeroSense 2002, edited by Eric Donkor, Michael J. Hayduk, Andrew R. Pirich, and Edward W. Taylor. SPIE, 2002. http://dx.doi.org/10.1117/12.477437.
Full textGrimaldi, R. L., S. Rodriguez, and A. Rusu. "A 10-bit 5kHz level-crossing ADC." In 2011 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2011. http://dx.doi.org/10.1109/ecctd.2011.6043596.
Full textMurshed, Alfakhri M., K. Lokesh Krishna, M. Abdullah Saif, and K. Anuradha. "A 10-bit high speed pipelined ADC." In 2018 2nd International Conference on Inventive Systems and Control (ICISC). IEEE, 2018. http://dx.doi.org/10.1109/icisc.2018.8399006.
Full textYenuchenko, Mikhail S., Mikhail M. Pilipko, and Dmitry V. Morozov. "A 10-bit segmented M-string DAC." In 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2018. http://dx.doi.org/10.1109/eiconrus.2018.8317081.
Full textVogt, A. W., and I. J. Dedic. "A 10-bit high speed CMOS CAS macrocell." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56703.
Full textBin Li, Yue Xu, and RuiMing Luo. "A 10 bit analog counter in SPAD pixel." In 2017 China Semiconductor Technology International Conference (CSTIC). IEEE, 2017. http://dx.doi.org/10.1109/cstic.2017.7919886.
Full textHashim, Mohamad-Faizal, Yuzman Yusoff, and Mohd Rais Ahmad. "A 10-Bit 50-MSPS Pipelined CMOS ADC." In 2006 IEEE International Conference on Semiconductor Electronics. IEEE, 2006. http://dx.doi.org/10.1109/smelec.2006.381103.
Full textRahman, Md Tanvir, and Torsten Lehmann. "A 10 bit cryogenic CMOS D/A converter." In 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2014. http://dx.doi.org/10.1109/mwscas.2014.6908339.
Full textKuo, Hsuan-Lun, Chih-Wen Lu, Shuw-Guann Lin, and Da-Chiang Chang. "A 10-bit 10 MS/s SAR ADC with the reduced capacitance DAC." In 2016 5th International Symposium on Next-Generation Electronics (ISNE). IEEE, 2016. http://dx.doi.org/10.1109/isne.2016.7543361.
Full textZhai, Zhenjun, Guoqiang Zhao, and Houjun Sun. "Design of a Wideband 1-bit 10 × 10 Reconfigurable Transmitarray in Ku Band." In 2020 International Conference on Microwave and Millimeter Wave Technology (ICMMT). IEEE, 2020. http://dx.doi.org/10.1109/icmmt49418.2020.9386787.
Full textReports on the topic "10-bit"
Atiya, M., D. Padrazo, Y. Zhao, R. Sumner, U. Untermeyer, B. Carlson, and Z. Zheng. Development of a 10-bit 500 Msample/sec Waveform Digitizcr. Office of Scientific and Technical Information (OSTI), September 1996. http://dx.doi.org/10.2172/770467.
Full textYu, Haichao, Haoxiang Li, Honghui Shi, Thomas S. Huang, and Gang Hua. Any-Precision Deep Neural Networks. Web of Open Science, December 2020. http://dx.doi.org/10.37686/ejai.v1i1.82.
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