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1
Verma, Ashutosh. "A 10-Bit 500-MHz 55-mW CMOS ADC." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=1835634861&sid=3&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Kommareddy, Jeevani. "10-bit C2C DAC Design in 65nm CMOS Technology." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1565538915029852.
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Guo, Wei. "A low-power 10-bit 50 MS/s CMOS successive approximation register ADC." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43200.
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An analog-to-digital converter (ADC) with a medium sampling rate (a few MS/s to a few tens of MS/s) and a medium resolution (8 to 14 bits) is a critical building block for data communication, imaging, and video systems. With the rapid growth in the number of portable devices, low-power design with higher performance is desired to increase the battery longevity as well as meeting the ever increasing performance requirement, which impose significant challenges to the ADC design. Successive approximation register (SAR) ADCs are one of the candidate structures for low power ADCs, and due to the advancements in the fabrication technologies they have been able to achieve medium sampling rates with a resolution of 10 bit. In this work, an ultra low-power 10-bit 50-MS/s SAR ADC is presented. To reduce the power and area, the monotonic switching procedure is combined with a parasitic-compensated split-capacitor digital-to-analog converter (DAC) that also has an improved capacitor matching. The nonlinearity of the conventional split-capacitor DAC due to parasitic capacitance and capacitor mismatch is improved by modifying the capacitor bank so that the bridge capacitor is an integer multiple of the unit capacitor (as opposed to fractional multiple in the conventional circuits) and by including two dummy unit capacitors connected to ground. The proposed 10-bit ADC is designed and simulated using a 90-nm CMOS technology. Post-layout simulation results show that at 1.0-V supply and 50 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 60.10 dB and consumes 0.32 mW with an input capacitance of 0.48 pF, resulting in a figure of merit (FoM) of 8.44 fJ/conversion-step. A proof-of-concept prototype is fabricated in 90-nm CMOS technology and is tested. The ADC core occupies an active area of 215×215 μm². Due to an unexpected problem with the measurement setup, at-speed testing was not possible and the test was done at 1 MS/s. The ADC achieves an ENOB of 7.51 with a power consumption of 51 μW. The reasons for subpar performance of the prototype design and potential solutions to improve it are discussed in detail.
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Chung, Hong-Yi, and 鐘鴻儀. "A 10-bit Successive Approximation ADC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57183272659084856815.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
98
Propose a fully differentially successive approximation ADC with a binary-weighted capacitor array networks. Add bootstrapped switches to accelerate charging to the capacitor networks in front of this architecture, and decrease the settling time of capacitor array. Also keep circuit operate correctly under low supply voltage driving switches. Use asynchronous control logic to generate the necessary clock signals internally, rather then provide clocks by external clock generator. Unit capacitors of the capacitor array are laid out in a common-centroid scheme to reduce the undercutting effect, for achieving the correct ratio of capacitor array. According to the result of simulation , the proposed ADC is designed to operate at 5Ms/s.Signal-to-noise and distortion ratio is 58.696dB, under the frequency of input signal is 2.5Mhz, the effective number of bit is 9.458 bit. The integral nonlinearity (INL) is 1.9 LSB. The differential nonlinearity (DNL) is 1.85 LSB. The power consumption is 5.3mW. Layout area of this architecture is 1080um * 880um.
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Huang, Ju-Lin, and 黃筑琳. "Design of 6-bit Flash ADC and 10-bit voltage-segmented DAC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/48178620065010904456.
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碩士國立暨南國際大學
電機工程學系
98
Two converters are proposed in this thesis. The first one is a 6-bit flash analog-to-digital converter (ADC), and the second one is a 10-bit voltage-type digital-to-analog converter (DAC) for Thin Film Transistor Liquid Crystal Display (TFT-LCD) source driver. The 6-bit flash ADC is designed in TSMC 0.18μm process technology. The sampling rate is 2GSapmle/s, and the supply voltage is 1.8 Volt. In this work, the “fully differential” structure is adopted and each sub-circuit is well-designed (sophisticated designed) to get more benefit of the overall performance, including a track-and-hold circuit with better linearity, preamplifiers with the reset switches, and the comparator with diode-connected transistors added at the output to limit the output swing. The second circuit, a 10-bit DAC, is designed in TSMC 0.35μm process technology. A new voltage-segmented DAC which combines a 4-bit DAC embedded operational amplifier is proposed. Two adjacent voltage levels, VH and VL, are selected from two 6-bit tree decoders, and then the 4-bit DAC embedded operational amplifier divides this voltage range into 16 segments. As a result, the 10-bits resolution can be achieved by this architecture. The source driver of LCD displayers implemented with the proposed 10-bit DAC shrinks the layout by more than 50% and greatly reduces costs.
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Jian-Feng, Shiu. "A 10-bit 250MS/s pipelined ADC." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-3101200716423100.
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Chao, Hao-tsun, and 趙浩淳. "A 10-Bit Area-Efficient SAR ADC." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/69383844125227169450.
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碩士國立暨南國際大學
電機工程學系
100
In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref±ΔV for reducing dramatically the ADC’s area. The 2N resolution is achieved by the N bit SAR ADC. In order to resolve the kickback noise, a cascode common gate amplifier is used in the comparator. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ADC simulation achieves a SNDR of 60.6dB and ENOB of 9.767 bit when operating at 14MS/s. The measured SNDR is 29.79dB, the ENOB is 4.66.
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Tseng, Hua-Wei, and 曾華偉. "2b/cycle-Assisted 10-bit SAR ADCs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/p7ddqf.
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碩士國立臺灣科技大學
電子工程系
106
This thesis presents 2b/cycle-assisted 10-bit successive approximation register (SAR) analog-to-digital converters (ADCs). By applying 2b/cycle-assisted architecture, it reduces the number of conversion cycles and thus speeds up the ADC operation. The proposed dynamic register (MdREG) circuit cuts down the delay from the comparator output to the DAC switches. It also helps the ADC operate at higher sampling rates. Dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. It also reduces the total capacitance of the digital-to-analog converter (DAC). The offset calibration scheme is proposed to effectively alleviate the degradation of the ADC linearity. Two ADCs were implemented based on the proposed 2b-1b/cycle configuration. A 10-bit 100-MS/s SAR ADC was fabricated using a 180 nm CMOS technology. This ADC occupies an active area of 0.07 mm2. Operating at 100-MS/s, the ADC consumes 7.4 mW from a 1.9 V supply. The peak DNL and INL are -0.56/+0.67 LSB and -0.75/+0.79 LSB respectively. The measured Nyquist SNDR and SFDR are 52.2 dB and 75.2 dB respectively. Another 10-bit 500-MS/s ADC was implemented in 40nm CMOS. Operating at 500-MS/s, the ADC consumes 1.84 mW from a 0.9 V supply. The simulated Nyquist SNDR and SFDR are 59.6 dB and 76 dB respectively.
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Lo, Wei-Lun, and 羅偉綸. "An 8-Bit 10-GS/s DAC." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/h4p9k2.
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碩士國立交通大學
電子研究所
106
In communication systems, most of data stream is performed in the digital domain, but the signal carrying data stream must be transmitted by analog signals. As a result, digital-to-analog(DA) and analog-to-digital(AD) converters are necessary to be utilized. The quality of data converters usually limits the accuracy and speed of overall system. Therefore, if data converters are equiped with the characteristics of high wide band and high dynamic range, communication system will transmit data in high-end quality and high speed. This thesis focuses on the Digital-to-Analog Converters(DACs). The current-steering structure has been widely used in high-speed DACs because its can be easily achieved in high sampling speed. However, the nonideal switching limits the bandwidth of spurious-free dynamic range(SFDR). SFDR reduces rapidly while input frequency increases. Therefore, conventional current-steering structure are optimized and applied to maintain high SFDR at high sampling rate frequency. In this work, a CMOS 8-BIT 10GS/s was fabricated in a 28nm CMOS technology. In post-simulation, the DAC achieves a SFDR better than 50dB for a sinewave input frequency 1.5GHz, and better than 40 dB up to 4.5GHz. Its power consumption is roughly 140mW of power. In the design of high-accuracy current-steering DACs, current sources with high matching property are required but the penalty is large area. Larger area of current sources will enhence the value of intrinsic and parasitic capacitor loading and cause the degradation of signl bandwidth. The way to reduce capacitor loading is utilize compact current cells but compact ones have larger mismatch properties. Therefore, practical simulation is necessary to find and fit the size of current sources with high-quality matching properties and low intrinsic capacitor loading.
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Hsu, Chia-Hao, and 許家豪. "A 10-bit High-Speed Subrange ADC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/74555666386339650556.
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碩士國立臺灣大學
電子工程學研究所
102
A low-noise phase-detector-based (PD-based) comparator is proposed for subrange analog-to-digital converters (ADCs) in this thesis. It can reduce the thermal-induced noise as well as the probability of the metastability. The 10-bit subrange ADC is composed of a 3.9-bit flash ADC and a 7-bit SAR ADC. The proposed ADC was fabricated in a 40-nm LP CMOS technology. The ADC achieves 54.41-dB SNDR at 160MS/s under a 1.1V supply voltage and consumes 2.7mW. The figure-of-merit (FOM) is 39.4 fJ/conversion-step. The active area is 0.0475 mm2.
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Shiu, Jian-Feng, and 許健豐. "A 10-bit 250MS/s pipelined ADC." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/21997672588403173162.
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碩士國立臺灣大學
電子工程學研究所
95
In recent years, the improvement in wireless communication equipments speeds up the progress of digital life. Cell phone is an obvious example: everyone has a cell phone. The function of the cell phone tends to be versatile; it is not only used in internet but also used in taking care of home security. Thus, the WiMax protocol in wireless communication is always used. The Wimax needs high speed data rate and a high speed and high resolution ADC is required in the protocol. Due to the portable equipments, low power is an important issue. But it conflicts between high speed and low power. Thus, it is an interesting topic to research in high speed and low power ADC. Pipelined ADC is always used in ADC with resolution larger than 10 bits and speed higher than 200MS/s. We wish to design a 1.2V 10-bit 250MS/s ADC, thus, a time-interleaved pipelined ADC architecture is chosen. Chapter 1 reviews the pipelined ADC architecture and introduces the errors in pipelined ADC. Chapter 2 discusses the time-interleaved ADC and the mismatch effects in time-interleaved ADC. A proposed architecture to increase conversion speed is given in Chapter 3 and the building blocks are also explained. Chapter 4 presents the test setup and measurement result. Final is a conclusion.
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Huang, lung Chen, and 黃龍誠. "A 10-bit TFT-LCD Source Driver." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/82242492176430365119.
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碩士國立暨南國際大學
電機工程學系
93
In this dissertation, a 10-bit source driver for the application of SXGA TFT-LCD is proposed. This source driver uses two complementary differential buffers in driving a pair of data lines to achieve the rail-to-rail driving. As for the 10-bit DAC, it is handled into two sections. At first, the electric voltage is fetched from R-string two group resistance string of DAC of 7-bit. Then, the corresponding voltage of the digit signal would be manifested through the 3-bit charge sharing DAC.
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Tseng, Huan-Chieh, and 曾煥傑. "A 1.2V 10-bit High-Speed Pipelined ADC." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/92358876564535883847.
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碩士國立臺灣大學
電子工程學研究所
96
This thesis presents a 1.2V 10-bit CMOS two-channel time-interleaved pipelined ADC in a standard 0.13-μm CMOS process. For high conversion speed, the first stage with divided residue gain is proposed to increase the feedback factor of the MDAC. In order to reduce the mismatch-effects, opamp-sharing technique is applied between two channels, and the proposed clock generator is designed to suppress the sampling-time mismatch. According to the measurement results, the prototype ADC exhibits a DNL of -0.49/+0.43LSB and an INL of -1.05/+0.86LSB at the sampling rate of 50MS/s. For 1MHz input frequency, the SNDR and SFDR achieve 56.53dB and 68.38dB at 50MS/s. The SNDR and SFDR are reduced to 37.63dB and 41.61dB at 250MS/s for 1MHz input. The power consumption is 106mW at the conversion rate of 250MS/s. The chip with pads occupies 1.3mm2. Chapter 1 introduces the pipelined ADC architecture. Chapter 2 discusses the channel mismatch effects in the time-interleaved ADC system. A proposed architecture to increase conversion speed and to reduce mismatch effects is given in Chapter 3. Detail circuit implementation and simulation result are shown in Chapter 4. Chapter 5 presents the test setup and measurement results. Finally, conclusions are summarized in Chapter 6.
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Tseng, Huan-Chieh. "A 1.2V 10-bit High-Speed Pipelined ADC." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200820291300.
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Lee, Nan-Ye, and 李南曄. "10-bit 125MHz Digital Transmitter for Gigabit Ethernet." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/62c79j.
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碩士國立臺北科技大學
電機工程系研究所
97
This thesis describes the implementation of a 125 MHz CMOS digital transmitter, which is composed of a 10-bit, 125 MHz digital to analog converter, and a fully differential current-mode line dirver, which is based on Gigabit Ethernet system specification. The digital transmitter had been fabricated with the TSMC 0.18 μm 1P6M CMOS technology. For high-speed application, the digital to analog converter adopts the current switch mode architecture. In order to reduce the current error and threshold-voltage variation, we use a current-source biasing technique. Buffers are used to isolate the output of digital circuit and glitch on current source could be reduced. Furthermore, in the cause of achieve smaller layout area, reduce the complexity of digital circuit and decrease the differential nonlinearity error (DNL). The digital-to-analog converter consists of 8-bit thermometer-encoding architecture. For the line driver achieve, in order to got high power efficiency, the utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. Furthermore, the capacitive feed-forward path is used to reduce the crossover distortion and the current-feedback circuit is added to line driver to increase linearity. The line driver over a 100 Ω differential load at 1.8V power supply and in 125 MHz operating frequency, the output voltage swing of the line driver is 2 VPP.
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Li, Hsiu-Chuan, and 李修全. "Design of a 10-bit 100MHz Pipelined ADC." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/10045794525214944702.
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碩士中原大學
電子工程研究所
102
This paper describes a 10-bit 100Msample/s pipelined analog-to-digital converter (ADC) fabricated in TSMC 0.18um 1P6M CMOS technology. By amplifier sharing technique, the converter is realized using only four amplifiers in front of eight stage to reduce the chip area and power consumption. This converter achieves 53.3-dB signal-to-noise ratio, 8.56 effective number of bits for a Nyquist frequency input at full sampling rate, and consumes 42.6mW from a 1.8-V supply. The FOM is 1.129pJ/conversion.
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Liu, Te-Hsiang, and 劉德祥. "A Low-power 10-bit Successive Approximation ADC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/93018442633893142862.
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碩士國立暨南國際大學
電機工程學系
101
A low-power 10-bit successive approximation ADC for wireless sensor networks is proposed in this thesis. In order to achieve low power consumption, the chip operating voltage is 0.7 V, and the input is single-ended rail-to-rail voltage signals. The digital-to-analog converter employed in the ADC, using binary-weighted multilayered sandwich capacitor array, can effectively reduce the overall capacitance value and power consumption. The low-power 10-bit successive approximation ADC proposed in this thesis is designed and implemented by using TSMC 0.18 μm CMOS process provided by Chip Implementation Center (CIC). The core area of the chip is 201 μm × 180 μm (0.03618 mm2), and the total area including pads is 680 μm × 680 μm (0.4624 mm2). From the measurement results at 0.7 V supply voltage, 2.4 MHz operating frequency, 200 kS/s sampling rate, and 1 kHz input frequency, an SNDR of 52.95 dB (ENOB of 8.5 bits) is achieved with 1.624 μW power consumption. The FOM is 22.4 fJ/conversion, and its ERBW is up to Nyquist rate.
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Yang, Jhih-Jing, and 楊智景. "A 10-bit source driver for LCD application." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/51115061228462142110.
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碩士國立暨南國際大學
電機工程學系
94
In this thesis, a 10-bit source driver for the application of SXGA TFT-LCD is proposed. For the high resolution demand, two types of digital to analog converter are combined to realize a 10-bit resolution application. At first stage, a pair of neighboring voltages are fetched from 7-bit R-string DAC. At second stage, the corresponding voltage to input digital code can be obtained by the 3-bit charge sharing DAC. The circuit uses piecewise linear conversion to implement a column driver, and uses two complementary differential buffers which drive a pair of data line to achieve the rail-to-rail driving.
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Nan-YuanWang and 王南元. "A 10-bit 110-MS/s SAR ADC with 2.5-bit Predictive Capacitor Switching Procedure." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/04638073732065532377.
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Bayoumy, Mostafa Elsayed. "A study of 10-bit, 100Msps pipeline ADC and the implementation of 1.5-bit stage." Thesis, 2013. http://hdl.handle.net/2152/24010.
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The demand on high resolution and high speed analog-to-digital converters (ADC’s) has been growing in today’s market. The pipeline ADC’s present advantages compared to flash or successive approximation ADC techniques. The high-resolution, high-speed requirements can relatively easier be achieved using pipelined architecture ADC’s than other implementations of ADC’s of the same requirements. Because the stages work simultaneously, the number of stages needed to obtain a certain resolution is not constrained by the required throughput rate. Latency is a result of a multistage concurrent operation of any pipelined system. But luckily enough, latency isn’t considered to be a problem in many ADC applications. In this work, a 1.5-bit stage in the pipeline ADC is completely implemented including its two voltage comparators, a DAC with three possible output voltages, and a multiplying digital to analog (MDAC) blocks. Only ideal components were used for clocking operation. At the end of design, a total harmonic distortion (THD) of less than -70 dB was achieved.text
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杜家銘. "A 10-bit CMOS pipelined analog-to-digital converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/95782567930742763991.
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Ku, Cheng-Yuan, and 古正雍. "10-bit 100MS/s Pipeline Analog to Digital Converter." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/10637408303357482521.
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碩士中原大學
電子工程研究所
100
A low power and small area pipeline ADC has been designed. The proposed ADC achieve 10-bit resolution and 100 MHz sampling rate by removing the SHA and only using four operational amplifiers, reducing the chip area and power consumption. The ADC is implemented in TSMC 0.18um process and occupied 1.2 mm2 with PAD, and the core area is 0.57 mm2 without PAD. Under 100MHz sampling rate, the static simulation shows DNL and INL are ±0.48LSB and ±0.65LSB. In dynamic simulation, when the input is Nyquist frequency, the SFDR is 65dB, SNDR is 53.7dB, and achieved 8.63ENOB. The proposed pipeline ADC under 1.8 V power supply, the power consumption is 46.76mW, where the analog circuit part consumes 37.44mW, and the digital circuit part consumes 9.35mW. The FOM is 1.181pJ⁄Conversion.
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Zheng, Hao-Yuan, and 鄭皓元. "10-bit Source Driver Circuits Design for TFT-LCD." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/09786332037154803401.
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碩士國立成功大學
電機工程學系碩博士班
97
The area of a DAC and the offset of a buffer are the main issues to be resolved for high resolution source drivers. In this thesis, area-efficient R-C DACs with low-offset push-pull output buffers for a 10-bit source driver are proposed. The 10-bit R-C DAC adopts a two-stage structure, which composes of a R-string and a weighted capacitor array. Comparing to a conventional 10-bit R DAC, the 10-bit R-C DAC has a smaller area. The output buffer adopts a modified opamp, based on a conventional two-stage Class-A opamp. A conventional Class-A opamp only has a charge or a discharge ability according to its type of input differential pair so it is not suitable for a low power driving mode (e.g. two-dot inversion). Therefore, a positive current feedback path is used to improve the insufficient charge (discharge) ability of a conventional two-stage Class-A opamp so that it is suitable for a low power driving mode. An offset averaging method is used for the offset of the output buffer. By using several switches and a control signal, the polarity of the offset is reversed periodically so the offset is averaged at the output of the output buffer. The offset averaging method needs no extra capacitors so it is cost-effective. The chip is fabricated using the TSMC 0.35μm 2P4M CMOS process and its area is 1704 x 262 μm2. The measured settling time of the output buffer is under 7.8μs. The maximum offset after averaging is 0.57LSB. The maximum DNL and INL are 3.09LSB and 5.69LSB respectively.
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Lin, Wan-Ru, and 林宛儒. "A 10-bit 250MS/s Digital-to-Analog Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/49715346785499917611.
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Wu, Geng-Han, and 吳庚翰. "Design of the 100 MHz 10 Bit Digital Transmitter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/4p324j.
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碩士國立臺北科技大學
電機工程系所
96
This thesis presents the design and implementation of a 1.8 V, 100 MHz CMOS digital transmitter. The digital transmitter consists of a 10-bit 100 MHz digital-to-analog converter (DAC), a low-pass filter, and a fully differential current-mode line-driver, which has been fabricated with the TSMC 0.18 μm 1P6M CMOS technology. To increase the operating speed, the design digital-to-analog converter is based on the current-switch mode. Furthermore, we use a new current-source biasing technique to reduce the current error caused by inevitable threshold-voltage variation. It deserves noticing that the digital-to-analog converter consists of 8-bit thermometer-encoding and 2-bit binary-encoding. The goal is to achieve smaller layout area, to reduce the complexity of digital circuit, and to decrease the differential nonlinearity error (DNL). For the design of line driver, this thesis focuses on the impedance-matching scheme and low-voltage architecture to achieve high power efficiency. The utilization of impedance synthesis is to eliminate the matching resistor which works with extra power consumption. A low-voltage class-AB output structure is also demonstrated. Furthermore, the capacitive feedforward path is used to reduce the crossover distortion and the current-feedback circuit is added to line driver to increase linearity. The simulated results show that the output voltage swing of the line driver is 2 VPP. Over a 100 Ω differential load, and the THD is -48 dB with the operating frequency of 100 MHz at 1.8 V power supply.
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Kao, You-De, and 高有德. "Design of 10-Bit Pipelined Analog-to-Digital Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/87214225695648168808.
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碩士國立暨南國際大學
電機工程學系
95
Recently, as portable multimedia develops rapidly, the low power issue for analog design is more and more important. However, with the advance of the deep submicron technique, for the analog design, we faces some problems that the decreases of signal dynamic range and dynamic performance, if we want to enhance the performance to suppress the noise and distortion which suffers from nonlinearity, we will make so large current that the low power design has a challenge. In this thesis, we design a 10-bit 66.6MS/s pipelined Analog-to-Digital converter with TSMC 0.18μm CMOS 1P6M process at 1.8V supply, and adopt eight conversion stages which 1.5-bit per stage has low noise and low power dissipation advantages, there are all 9 stages. We use the modified op-amp architecture for S/H and MDAC circuit, and take four kind of different specifications for low power design. Simultaneously, for the switch design, we reduce the nonlinearity of the switch by using the voltage-bootstrapped circuit. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit, which can reduce the demand of the comparator and let it tolerate ±125mv of offset voltage. In this design result, when input signal frequency at 1MHz, we get SFDR/SNR/SNDR is 58.81dB/55.62dB/51.85dB, the effective number of bit(ENOB) is 8.32bit, total power dissipation is76.36mW, and total chip area is 1mm2.
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Wang, Wei-Ren, and 王偉仁. "A 10-BIT 5MS/S LOW-VOLTAGE PIPELINE ADC." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/45741108962271869327.
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碩士大同大學
電機工程研究所
94
In this thesis, we design a 10-bits 5 Msample/s low-voltage pipeline ADC. Because the threshold voltage of transistors does not scale with the technology, circuits used in the pipeline ADC in the past could not obtain the desired dynamic range in low voltage. Several solutions have been proposed to overcome the problem. In this thesis, the pipeline ADC is design by opamp-reset switching technique. In addition, the comparison between different solutions has been made. We also analyze the operational amplifier requirement to meet the necessary accuracy.
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Kuo, Han-Sung, and 郭漢松. "10 Bit 250MSample/s Interpolation Digital to Analog Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/61148796589144378670.
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碩士國立臺灣大學
電子工程學研究所
93
The requirements on today’s wireless communications equipment are very hard. Most of the signal processing is done in the digital domain, but the information has to be transferred with analog signals, and therefore analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are crucial building blocks. In this thesis, a 10-bit 250MSample/s current-steering DAC is presented for 802.11a transceiver, with interpolation function for frequency domain applications. For 802.11a transceiver standard, the channel bandwidth is 20MHz. Thus the input bandwidth of DAC can be defined 20MHz. 64 QAM which be used modulation has to need 8~10 bit. So, the input bit number is defined 10 bit to increate the resolution. Using interpolation function is to release the specification of filter in the transceiver. The special technique of layout and circuit of switch current source are employed to improve the performances and size of the current source matrix. Deglitch circuit is used to eliminate the digital data asynchronous effects. In order to increate accuracy of the DAC, nonlinearity and linearity effects can be estimated before to tape out the chip. This interpolation DAC uses mix mode 0.35μm CMOS technology and power consumption is 60.2mW. The die area is 2.25mm2.
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Hwang, Shan-Chun, and 黃善君. "The Design and Realization of Digital Calibration in 10-bit 10 MSPS Pipelined ADC." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/59693826365920488412.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
89
The goal of this thesis is to understand the calibration in capacitor’s mismatch error for pipelined ADC, one precision multiply-by-2 circuit is made from Switch-Capacitor, the capacitor’s mismatch error will reduce the Differential Nonlinearity(DNL), for increasing the pipelined ADC’s Signal-to-Noise ratio, we first have to understand the calibration algorithm in capacitor’s mismatch. This thesis is divided six chapters, chapter 1 and chapter 2 is the introduction and the classification in ADC. In chapter 5 is the layout and test , chapter 6 is the conclusion. The followings are chapter 3 and 4’s brief description: In chapter 3, the calibration method is divided two domain, analog-domain and digital-domain. The analog-domain used in calibration for pipelined ADC are larger in area and complex in design. If we use the digital-domain, the area will be smaller and the design is simpler. In this thesis, the improvement in SNR is about 1.5~2 bit under 1% capacitor error mismatch. In chapter 4, we described the detailed circuit buliding block in pipelined ADC, containing operational amplifier, multipling DAC, fully differential comparator, and sample and hold circuit. The operation speed in pipelined ADC is the design in opamp. and MDAC, we described some design issues in the operational amplifier.
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Chia-HsinLee and 李佳欣. "A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC with Digital Code Error Correction." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/64442107517566871093.
Full textAbstract:
碩士國立成功大學
電機工程學系
104
This thesis presents a single-channel 2.5-bit/cycle 10-bit 160-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with the conventional 2.5-bit/cycle SAR ADC, the proposed input level shifting technique saves one sub-digital-to-analog converter (sub-DAC) and relaxes the requirement on resolution for the other sub-DACs. In addition, the proposed digital code error correction provides a wider error tolerance range by a compact digital design. The proposed ADC was fabricated in TSMC 90-nm CMOS standard 1P9M process, and occupies 262.8 μm × 420 μm active area. At 1-V supply and 160-MS/s sampling rate, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.23 dB. The resultant effective number of bits is 8.55 bits with power consumption of 1.97 mW. The figure-of-merit (FoM) is 32.9 fJ/conversion-step.
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Rengachari, Thirumalai. "A 10 bit algorithmic A/D converter for a biosensor." Thesis, 2004. http://hdl.handle.net/1957/28871.
Full textAbstract:
This thesis presents a novel algorithmic A/D converter to be used in a biosensor.
The converter is capable of a conversion rate of 1.5 bits/phase and hence the
required conversion time is reduced. The proposed architecture is analyzed for non-ideal
effects and compared with existing algorithmic A/D architectures. The
converter needs only one op-amp, 4 comparators and 3 capacitors. Power reduction
techniques are discussed with respect to the biosensor and the ADC. The ADC is
designed for fabrication in a CMOS 0.18μm process.Graduation date: 2004
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Shih-Lin, Huang. "A 10-bit 50MSample/s Pipelined Analog-to-Digital Converter." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0002-2206200511255900.
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Ying, Cheng-Ming, and 應振明. "Design of 10-bit 50MHz Pipelined Analog-to-Digital Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/53234619478334172285.
Full textAbstract:
碩士淡江大學
電機工程學系
91
Recently, Imaging applications are proliferating, with an annual market growth in excess 35%. Products include video cameras, camcorders, professional video, and document scanners. Charge-coupled devices (CCDs) are one primary form of the imaging sensor. The analog-to-digital converter (ADC) is a performance-critical component in the CCD system. In order to achieve resolution and sampling frequency, a pipelined ADC is suitable for this purpose. In this thesis, a 10-bit 50MHz sampling rate pipelined ADC is designed. The nonlinearity in the sub-ADC is due to comparator offset or reference voltage errors; therefore we utilize a sub-ADC with 1.5 bit/stage with error correction to overcome this problem, and fully differential structure is used to reduce the common-mode noise. According to HSPICE simulation result, the resolution of this ADC is 10-bit, the sampling rate is 50MHz, and the power consumption is 75mW in 2.5V supply voltage. DNL is between -0.4LSB to 0.4LSB; INL is between —0.2LSB to 0.4LSB, and SNDR is 56.7dB when input frequency is 11.11MHz and sampling rate is 50MS/s. The operation voltage range is 0.75V~1.75V. The differential input range is from —1V to 1V. This ADC is designed with TSMC 1p5m 0.25um CMOS process. The chip area is around 1474×1009um2.
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Huang, Shih-Sing, and 黃世興. "10-BIT 40-MS/S PIPELINE ANALOG TO DIGITAL CONVERTER." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/46937665823288754411.
Full textAbstract:
碩士大同大學
電機工程學系(所)
97
In this thesis, we design a 10-bit 40MSample/s pipelined analog-to-digital converter (ADC) by TSMC 0.18μm 1P6M mixed signal process technology. The supply voltage is 1.8V. The ADC architecture is nine stage pipelined ADC in this design, we adopt 1.5-bit/per stage architecture and a 2-bit flash ADC in the last stage. In order to decrease noise interference, the whole circuit is designed by fully differential structure. The ADC is simulated by HSPICE using TSMC 0.18μm 1P6M mixed signal process technology. The proposed ADC has the following performances: For 0.5078125MHz sine wave input, the SNR is 57.8dB, the ENOB is 9.32bits, and the power consumption is 117mW at the maximum conversion rate.
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Chen, Pohsien, and 陳柏憲. "The Study of 10-bit Asymmetric Analog-to-Digital Converter." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/66946129718925211638.
Full textAbstract:
碩士聖約翰科技大學
電子工程系碩士班
100
In the recent, several researches investigated the performance improvement to analog-to-digital converters (ADC), the most novel ADC are completed and improved via the flash or pipelined ADC to improve the converter’s performance. On the reason, it drives we the idea to combine the flash- and pipelined-ADC to accomplish two-stage architecture of ADC, which is a novel and feasible analog-to-digital converter to work in high speed world. In this thesis, the hybrid ADC has 10-bit and works at 150 MHz when the voltage is 3.3V. For the performance analysis, we simulate different kinds of structure in the various rations of bits for flash- vs. pipelined-ADC, respectively such as 6:4, 5:5, and 4:6. For 10-bit analog to digital converter, taking into consideration the circumstances, the 6-bit pipelined ADC and 4-bit flash ADC architecture is better, because the transistors required the least number. Does not consider it, the 5-bit pipelined ADC and 5-bit flash ADC architecture is best, because it conversion speed is faster than the 6-bit pipelined ADC and 4-bit flash ADC architecture.
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Chiou, Yi-Hao, and 邱奕豪. "A 10-bit 20MS/s SAR Analog to Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/85616808753267165639.
Full textAbstract:
碩士中原大學
電子工程研究所
101
As the science and the manufactures growth the wireless network has been becoming mature. However, the consumed power and the operational time turn to be the main issues for the wireless sensors and the portable devices. Therefore, for considering lowering the power consumed to extends the battery life is the top priority, and the area of it is also important as well. In this work, a 10-bit 20MS/s SAR ADC is proposed by using monotonic capacitor switching procedure. In the previous designs, SAR ADC cannot operate in high speed because the unit of capacitance is too large which slows down the charging speed. To solve this problem, this work provides an approach by using MOM capacitances, each of which 5 fF, and the MOM capacitances are not only reducing the unit of capacitances but also shorting the charging period. Furthermore, the structure of switching procedure in conventional SAR ADC increases power consumption. So that, this work has selected a mechanism of monotonic capacitor switching procedure to reduce 81 % power consumption. The ADC was designed by TSMC 0.18 um CMOS process and the power consumption of this work is 1mW operating at 1.8 V. The ENOB is 9.96 bits, the peak DNL and INL are +0.6/-0.6 LSB and +0.58/-0.7 LSB, when the input is Nyquist frequency, the SNDR of 61.2 dB, FOM of 52 fJ/conversion-step. The ADC occupies active area 0.74 mm2 with PAD, and the core area of 0.092 mm2.
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Huang, Shih-Lin, and 黃世麟. "A 10-bit 50MSample/s Pipelined Analog-to-Digital Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/07160537484935753409.
Full textAbstract:
碩士淡江大學
電機工程學系碩士班
93
In this paper, a 10-bit 50MSample/s Nyquist-rate CMOS pipelined analog-to-digital converter (ADC) with digital correction is presented for the IEEE 802.11a WLAN and HDTV applications. The digital correction technique adapted by this pipelined ADC can give more accurate demands in application. The simulated DNL and INL of the presented pipelined A/D converter are suppressed within ± 0.45 LSB and ± 0.46 LSB, respectively. The simulated SNDR is 60.5dB and the effective number of bits is 10 at the rate of 50MSample/s with a 5MHz input frequency. This presented circuit has been fabricated in a 0.35um 2P4M CMOS process. The dissipation power of 93mW in this ADC was measured under the sampling rate of 50MHz at 2.5V supply voltage. And its core area without PADs is 2.8×1.5 mm2.
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Liang, Sheng-Chuan, and 梁聖泉. "A 10-bit 60MHz pipelined CMOS analog to digital converter." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/50837276096679760824.
Full textAbstract:
碩士國立成功大學
電機工程研究所
83
In this thesis, we design a single 5-V, 10-bit 62.5MHz pipelined CMOS analog-to-digital converter ADC) for video-rate signal processing. This conversion is the fastest of published pipeline CMOS ADCs up to now. In our proposed framework, sample/ hold circuit, 4-bit flash A/D converter, 4-bit D/A converter, subtractor, and gain circuit are the main elements for this 3-stage pipelined ADC. They will be implemented with switched- capacitor (SC) techniques. Using gain enhancement technique, the OPAMP is designed to have 100-dB gain as well as 400MHz bandwidth. It will satisfy for the settling time and gain error of the sample/hold, subtractor, and gain stage circuits. Compensation scheme is adopted to avoid charage injection in the SC circuits. Besides, offset cancellation technique is used to reduce offset voltage. The D/A converter using a capacitor array can achieve enough accuracy. In the 4-bit flash ADC, each of the 16 high speed comparators composed of a preamplifier stage and positive feedback. To avoid having not enough time for restoration, a rest mechanism is used, but it doesn''''t need extra phase. This ADC system contains two analog signal conversion paths whose operations are interleaved, and these two paths share a single 4-bit flash A/D converter at each of the 3 stages. This will reduce chip area. The digital outputs of each stage are 4-bit, where 1-bit is overlapped between two connected stages for correction, and are summed to generate 10-bit ADC output. This A/D converter will be fabricated with 0.8-micrometer CMOS technology. The power dissipation is about 600 mW. The integral nonlinearity error is about +-0.3LSB. The active area of the chip is 2820um*1300um.
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wang, Wen-Ren, and 王偉仁. "A 10-BIT 5-MS/S LOW-VOLTAGE PIPELINE ADC." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/08117410140618267663.
Full textAbstract:
碩士大同大學
電機工程學系(所)
94
In this thesis, we design a 10-bits 5 Msample/s low-voltage pipeline ADC. Because the threshold voltage of transistors does not scale with the technology, circuits used in the pipeline ADC in the past could not obtain the desired dynamic range in low voltage. Several solutions have been proposed to overcome the problem. In this thesis, the pipeline ADC is design by opamp-reset switching technique. In addition, the comparison between different solutions has been made. We also analyze the operational amplifier requirement to meet the necessary accuracy.
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Chou, Yu-Liang, and 周育諒. "Implementation of the 10-bit 40-MS/s Pipelined ADC." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/6t7kpj.
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Chang, You-Gang, and 張祐綱. "A 10-Bit Compact Source Driver for LCD-TV Application." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/2785m2.
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Huang, Jie-Jueng, and 黃傑忠. "A 3.3v 10-bit CMOS pipelined Analog-to-Digital Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/pb7ev2.
Full textAbstract:
碩士國立交通大學
電子工程系所
94
Among all architectures of analog-to-digital converter (ADC), the pipeline architecture was widely used in applications with high speed and high resolution, due to its small size and low power consumption. If we want to achieve higher speed and more accuracy, there are some errors to overcome. Such as capacitor mismatch, operational amplifier gain error, bandwidth limitation, comparator threshold offset and so on. In this thesis, we present a new operational amplifier with positive feedback technique to reduce its gain error and input parasitic capacitance, it is well suited to implement ADC with high performance. In this thesis, a fully differential 3.3V, 10-bit, 40M sample/sec pipelined ADC with a 1.5-bit stage digital error correction has been designed with TSMC 0.35-μm double-poly four-metal CMOS process. The components in this ADC include residue amplifier, comparator, flip-flop, adder, clock generator and front-end sample-and-hold(S/H). The input range is -1V~+1V.
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Hsu, Chen-Kai, and 徐振凱. "A Single-Channel 10-bit 400-MS/s Pipeline ADC." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/62691292115562348037.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
103
Analog-to-digital (A/D) converters which have been a communicator between the analog world and digital domain are indispensable building block in many systems. In this dissertation, a 10-bit 400-MS/s pipeline ADC is proposed to achieve low power in a 90-nm CMOS technology. On the other hand, amplifiers, important and indispensable block of pipeline ADCs, consume significant power to ensure the performance. A prior art [1] employing a single-stage amplifier consisting of a NMOS differential pair with a PMOS load in pipeline ADCs has been proved that amplifier can provide better conversion-efficiency while achieving better FoM. Although the amplifier increases the power-efficiency, it also introduces the ineluctable linearity issue. A multi-bit front-end stage is a straightforward solution but the solution increases the number of comparators and makes the front-end stage more sensitive to the offset. Hence, this work proposes a coarse-stage-assisted front-end stage that not only resolves 4.5-bit in the first stage but also reduces the number of comparators and becomes less sensitive to the offset. The proposed ADC has been fabricated in a 90-nm standard CMOS technology which occupies 0.15mm2. The proposed ADC consumes 8.7 mW from a 1-V supply and achieves an SNDR of 57.23 dB at a 5.1-MHz input and 55.95 dB near Nyquist rate. It also achieves a signal-to-noise-plus-distortion (SNDR) better than 55 dB over the entire Nyquist band. The figure-of-merit (FoM) of the proposed ADC is 42 fJ/Conv.
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Chou, Kuan-Hung, and 周冠宏. "A 10-bit 500M-sample/sec Digital to Analog Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/82184302127011166824.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
93
In this paper, a 10-bit 500-MSample/s CMOS digital-to-analog (D/A) converter is presented. It is based on a current steering segmented 5 + 5 architecture that comprises 5MSB’s unary cells and 5LSB’s binary weighted cells in this design. The 500-MSample/s conversion rate has been obtained by an, at transistor level, fully custom designed thermometer decoder and synchronization circuit. In the digital part, a high speed, high output crossing-point latch is designed to minimize the glitch energy. Moreover, using cascade current cell in analog part can increase the output impedance and improve the performance of the SNDR and SFDR. From the simulation result, the glitch energy is 0.995 psec-V. For a near 250 MHz input signal at 500 MHz sampling rate, the SNDR is about 60dB. The power consumption of this DAC with a single 3.3V supply is 70 mW. Proper area of current source transistor is chosen to overcome mismatch error due to process variation. This DAC chip is fabricated using TSMC 0.18μm-1P6M CMOS process and the die area is 1.07mm×1.07mm.
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Chang, Hua-Hsuan, and 張華軒. "Implementation of 10-bit 50MSPS Pipelined Analog-to-Digital Converter." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/vaqpaf.
Full textAbstract:
碩士國立東華大學
電機工程學系
100
In this thesis, a 10-bit pipelined analog-to-digital converter (ADC) is implementation with TSMC 0.18um CMOS 1P6M mixed signal process. The sampling rate is 50MHz and the supply voltage is 1.8V. The overall circuit of architecture includes front-end sample and hold circuit, stage1-8 can be a resolution of 1.5-bit, and the last stage is a 2-bit flash analog-to-digital converter. The pipeline ADC in this thesis can be used in video processing, such as digital video broadcasting-handheld (DVB-H). The designed circuitry uses to reduce circuitry noise, therefore, the fully differential architecture is adopted to avoid noise influence for circuitry. Considering the different voltages for the first sub-ADC and MDAC may be sampled, and the difficulty the design, the sample and hold circuit in the front part will be retained. Although power consumption is it increased, the circuit can have better linearity. The designed ADC is simulated by HSPICE software. The SPICE Explorer is used to achieve the simulation of Fast Fourier Transform (FFT), Differential Nonlinearity (DNL) and Integral Nonlinearity (INL). The sine wave input at 1.12 MHz, the proposed ADC of spurious free dynamic range (SFDR) is 47.1dB. The Effect Number of Bits (ENOB) is 7.23Bit and DNL is 3.21LSB. The power consumption is 40.4mW at 1.8V supply voltage.
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Meng-FaYang and 楊孟法. "A 10-bit 27-MS/s Low Power SAR ADC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/10968295848672801404.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
98
This thesis reports the design and implementation of a 10-bit 27-MS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is adopted to reduce the power consumption of the proposed ADC. The average switching energy of the capacitor array can be reduced by 81.3% compared to the conventional switching method. The designed ADC is fabricated in TSMC 0.18-μm 1P6M CMOS technology, and occupies 0.205 mm x 0.31 mm core areas. The total chip draws 1.21 mW from 1.8-V power supply at 27-MS/s sampling rate, and the average energy consumption per conversion step is 226.2 fJ. At 20-MS/s sampling rate, the average energy consumption per conversion step is 85.7 fJ.
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Wu, Chih-wei, and 吳致緯. "A 10-bit 250-MSample/sec Digital to Analog Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/54821077203873613434.
Full textAbstract:
碩士國立中山大學
資訊工程學系研究所
94
The goal of this research is to design a low power, high speed, 10-bit, 250 MHz digital-to-analog converter. For high speed application, the DAC is implemented in thermometer-code based segmented DAC. An optimal switching scheme is used in this design. The switching scheme can compensate the gradient error in thermometer-code DAC arrays.This DAC is implemented in a 0.18μm 1P6M mixed-signal CMOS process provided by TSMC.
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Ho, Chun-Ta, and 何俊達. "10-Bit 200MHz Double-Sampling Pipelined Analog-to-Digital Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/71129943778998648798.
Full textAbstract:
碩士國立交通大學
電信工程系所
95
Pipelined analog-to-digital converters (ADCs) have intrinsic high-speed characteristics and are commonly used in wideband communication and video systems. However, with the higher resolution and throughput rate the power consumption and the required area are getting larger. Therefore, the double-sampling technique provides a method applied to the pipelined ADC to duplicate the sampling rate without consuming two times of power and area. The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was simulated by TSMC 0.18um 1P6M CMOS process. It consists of one front-end SHA, eight cascaded 1.5-bit stages, and a final 2-bit flash converter in the last stage. All analog circuits are fully differential with a 2Vpp input signal and 1.8V power supply. The operation amplifier in each stage is shared between the two paths and active for one of both paths alternately. Not only the operation amplifier in each stage is shared, but sub-ADC is common to both paths. As a result, it makes sampling more efficient and increases the throughput rate of the pipelined ADC. The 10-bit 200MS/s double-sampling pipelined analog-to-digital converter was finally implemented by TSMC 0.18um 1P6M CMOS process. The pipelined ADC dissipates 103mW at a 100MHz clock rate and a 200MS/s sampling rate with 1.8V supply voltage. The chip area is 1.134*1.380 mm2. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.75 LSB and ±0.95 LSB, respectively. And the peak SNDR about 56dB for an input signal of 1MHz sine wave.
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Chen, Wei-chih, and 陳威志. "The 10-bit 10-MHz Continuous-Time Sigma-Delta ADC Chip Design for 4G LTE Applications." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/268yhu.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
102
In this thesis, a 10 MHz CT ΣΔ modulators are designed and fabricated with TSMC 0.18um CMOS. The continuous time lowpass ΣΔ ADC for 4G LTE applications. The modulator is fabricated and taped out. In this chip, CICFF topology is applied. Compared with conventional CIFF topology, capacitive feedforward is a simple approach and has a merit of low power dissipation, and add a feedback path after quantizer to enhance the noise transfer function that effectively suppress noise in bandwidth and push noise to out-of-band and follow by a digital filter to filter the out of band of noise. The ΣΔ analog-to-digital converter achieves a measured dynamic range of 59 dB over a 10 MHz signal bandwidth, SNDR of 58.95 dB, IM3 of -60 dB, power consumption of 40.8 mW at 1.8 V supply with 320 MHz clock frequency. Including pads, the overall chip area is 1.056 (1.028 x 1.028) mm2. Although ΣΔ analog-to-digital converter have high tolerance for the imperfection of analog circuit, a decimation filtering the output stream of ΣΔ modulators enhance the ADC’s performance. The decimation filter consists of two cascaded integrator and comb filter (CIC filter). The output signal of oversampling ΣΔmodulator is down converted by decimation filter; thus, a Nyquist rate bandwidth is obtained for the ΣΔ ADC. The decimation filter can filter noise from high frequency effectively and prevent high frequency noise from folding to desired baseband frequency range.
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I-Jen, Chao, and 趙宜任. "Design of a 10-bit 50MHz Pipelined Analog-to-Digital Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/63562885702621629198.
Full textAbstract:
碩士崑山科技大學
電子工程研究所
95
In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter (ADC) by TSMC 0.35�慆 2P4M mixed signal process technology. The supply voltage is 3.3V. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt 1.5-bit/per stage technology and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit (S/H) and the multiplying DAC (MDAC). In order to reduce the dependence of input signal on charge injection of input switch, the bootstrapped switch structure is used to implement the switches of S/H input. Meanwhile, in order to decrease noise affection, the whole circuit is designed by fully differential structure. The ADC is simulated by HSPICE using TSMC 0.35�慆 2P4M mixed signal process technology. The proposed ADC has the following performances: The sampling rate of ADC is 50MHz, INL is +1.7LSB to -0.85LSB, and DNL is +1.2LSB to -0.6LSB. For 1MHz sine wave input, the SNDR is 58.626dB, the ENOB is 9.47bits, and the power consumption is 258mW at the maximum conversion rate.