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Journal articles on the topic '10-bit'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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1

Sugimoto, Y., and S. Mizoguchi. "An experimental BiCMOS video 10 bit ADC." IEEE Journal of Solid-State Circuits 24, no. 4 (1989): 997–99. http://dx.doi.org/10.1109/4.34083.

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2

Farr, W., L. B. Levit, and U. A. Uhmeyer. "100 MHz 10-Bit Image Chamber Analyzers." IEEE Transactions on Nuclear Science 32, no. 1 (1985): 636–39. http://dx.doi.org/10.1109/tns.1985.4336912.

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3

Zhang, Yulin, Guiliang Guo, Yuepeng Yan, and Tao Yang. "Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network." International Journal of Computer Theory and Engineering 6, no. 6 (December 2014): 443–46. http://dx.doi.org/10.7763/ijcte.2014.v6.906.

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4

Tsai, C. C., C. H. Lai, W. T. Lee, and J. O. Wu. "10-bit switched-current digital-to-analogue converter." IEE Proceedings - Circuits, Devices and Systems 152, no. 3 (2005): 287. http://dx.doi.org/10.1049/ip-cds:20040562.

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5

GAO Yuan, 高原, 魏廷存 WEI Ting-cun, and 李博 LI Bo. "Design of 10-bit TFT-LCD Source Driver Circuit." Chinese Journal of Liquid Crystals and Displays 26, no. 6 (2011): 808–12. http://dx.doi.org/10.3788/yjyxs20112606.0808.

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6

Son, Jisu, Han-Yeol Lee, Yeong-Woong Kim, and Young-Chan Jang. "A 10-bit 10-MS/s SAR ADC with a Reference Driver." Journal of the Korea Institute of Information and Communication Engineering 20, no. 12 (December 31, 2016): 2317–25. http://dx.doi.org/10.6109/jkiice.2016.20.12.2317.

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7

Lee, Byunghun, Ki-Duk Kim, Yong-Joon Jeon, Sung-Woo Lee, Jin-Yong Jeon, Seung-Chul Jung, Jun-Hyeok Yang, Kyu-Sung Park, and Gyu-Hyeong Cho. "27.2: A Buffer Amplifier with Embodied 4-Bit Interpolation for 10-Bit AMLCD Column Drivers." SID Symposium Digest of Technical Papers 40, no. 1 (2009): 371. http://dx.doi.org/10.1889/1.3256790.

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8

Lu, Chih-Wen, Ching-Min Hsiao, Yo-Sheng Lin, and Mau-Chung Frank Chang. "A 10-Bit DAC With 1.6-Bit Interpolation Cells for Compact LCD Column Driver ICs." Journal of Display Technology 9, no. 3 (March 2013): 176–83. http://dx.doi.org/10.1109/jdt.2012.2236679.

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9

Woo, Jong-Kwan, Dong-Yong Shin, Won-Jun Choe, Deog-Kyoon Jeong, and Suhwan Kim. "58.4: 10-Bit Column Driver with Split-DAC Architecture." SID Symposium Digest of Technical Papers 39, no. 1 (2008): 892. http://dx.doi.org/10.1889/1.3069817.

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10

Shehata, Khaled, Saleh Eisa, Hani Fikry, and Tarif Elshafiey. "DESIGN OF A 10-BIT NON-LINEAR INTERPOLATION DAC." International Conference on Electrical Engineering 5, no. 5 (May 1, 2006): 1–7. http://dx.doi.org/10.21608/iceeng.2006.33530.

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11

Rikan, Behnam Samadpoor, Hamed Abbasizadeh, Dong-Soo Lee, and Kang-Yoon Lee. "A 10-bit 10MS/s differential straightforward SAR ADC." IEIE Transactions on Smart Processing and Computing 4, no. 3 (June 30, 2015): 183–88. http://dx.doi.org/10.5573/ieiespc.2015.4.3.183.

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12

Macq, D., and P. G. A. Jespers. "A 10-bit pipelined switched-current A/D converter." IEEE Journal of Solid-State Circuits 29, no. 8 (1994): 967–71. http://dx.doi.org/10.1109/4.297705.

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13

O'Leary, P. L., and H. J. Orben. "10-MHz 64-bit error-tolerant signature recognition circuit." IEEE Journal of Solid-State Circuits 23, no. 3 (June 1988): 625–29. http://dx.doi.org/10.1109/4.299.

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14

Nayebi, M., and B. A. Wooley. "A 10-bit video BiCMOS track-and-hold amplifier." IEEE Journal of Solid-State Circuits 24, no. 6 (1989): 1507–16. http://dx.doi.org/10.1109/4.44986.

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15

Tentrup, Tristan B. H., Thomas Hummel, Tom A. W. Wolterink, Ravitej Uppu, Allard P. Mosk, and Pepijn W. H. Pinkse. "Transmitting more than 10 bit with a single photon." Optics Express 25, no. 3 (February 2, 2017): 2826. http://dx.doi.org/10.1364/oe.25.002826.

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16

Chiang, Shiuh-Hua Wood, Hyuk Sun, and Behzad Razavi. "A 10-Bit 800-MHz 19-mW CMOS ADC." IEEE Journal of Solid-State Circuits 49, no. 4 (April 2014): 935–49. http://dx.doi.org/10.1109/jssc.2014.2300199.

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17

Barra, Samir, Souhil Kouda, Abdelghani Dendouga, and N. E. Bouguechal. "Simulink Behavioral Modeling of a 10- bit Pipelined ADC." International Journal of Automation and Computing 10, no. 2 (April 2013): 134–42. http://dx.doi.org/10.1007/s11633-013-0706-0.

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18

O'Halloran, M., and R. Sarpeshkar. "A 10-nW 12-bit accurate analog storage cell with 10-aA leakage." IEEE Journal of Solid-State Circuits 39, no. 11 (November 2004): 1985–96. http://dx.doi.org/10.1109/jssc.2004.835817.

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19

Yang, Huanhuan, Fan Yang, Shenheng Xu, Yilin Mao, Maokun Li, Xiangyu Cao, and Jun Gao. "A 1-Bit $10 \times 10$ Reconfigurable Reflectarray Antenna: Design, Optimization, and Experiment." IEEE Transactions on Antennas and Propagation 64, no. 6 (June 2016): 2246–54. http://dx.doi.org/10.1109/tap.2016.2550178.

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20

Kang, Jin-Seong, Jin-Ho Kim, Seon-Yung Kim, Jun-Yong Song, Oh-Kyong Kwon, Yuen-Joong Lee, Byung-Hoon Kim, et al. "10-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs)." IEEE Journal of Solid-State Circuits 42, no. 12 (December 2007): 2913–22. http://dx.doi.org/10.1109/jssc.2007.908690.

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21

Lin, Jin-Yi, and Chih-Cheng Hsieh. "A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 3 (March 2017): 562–72. http://dx.doi.org/10.1109/tcsi.2016.2613505.

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22

Vandenberg, JD, and Stefano Andriani. "A Review of 3D-LUT Performance in 10-bit and 12-bit HDR BT.2100 PQ." SMPTE Motion Imaging Journal 129, no. 2 (March 2020): 59–70. http://dx.doi.org/10.5594/jmi.2020.2965022.

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23

Geng, Xueyang, Fa Foster Dai, J. David Irwin, and Richard C. Jaeger. "An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC." IEEE Journal of Solid-State Circuits 45, no. 2 (February 2010): 300–313. http://dx.doi.org/10.1109/jssc.2009.2037542.

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24

Bramburger, Stefan, and Dirk Killat. "10-bit tracking ADC with a multi-bit quantizer, variable step size and segmented current-steering DAC." Advances in Radio Science 17 (September 19, 2019): 161–67. http://dx.doi.org/10.5194/ars-17-161-2019.

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Abstract. This paper presents a 10-bit tracking ADC using a multi-bit quantiser and a segmented current-steering DAC. The quantiser allows a dynamical adjustment of the step size dependent on the input signal waveform. This mitigates the limited slew rate of delta encoded ADCs. Energy consumption induced by 1 LSB ripple is removed by the quantiser. The segmented current-steering DAC allows simple control, good monotonicity and improved transient response when compared to previous design as well as potential power reduction.
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25

Jang, ByeongGi, Abbas Syed Hayder, SungHan Do, SungHun Cho, DongSoo Lee, YoungGun Pu, Keum Cheol Hwang, Youngoo Yang, and Kang-Yoon Lee. "A design of 10-bit, 10 MS/s Pipelined ADC with Time-interleaved SAR." Microelectronics Journal 62 (April 2017): 79–84. http://dx.doi.org/10.1016/j.mejo.2017.02.011.

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26

Koundal, Anjali, and Sanjeev Dewra. "Performance Analysis of 4×10 Gbps OFDM-PON System Over ROF Link." Journal of Optical Communications 40, no. 2 (March 26, 2019): 113–17. http://dx.doi.org/10.1515/joc-2017-0049.

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Abstract In this paper, an OFDM-ROF-PON transmission system at bit rate of 4×10 Gbps is proposed and demonstrated. This paper analyzes orthogonal frequency division multiplexing system for radio over fiber in passive optical network at different input powers. A laser source of 193.1 THz is used with single mode fibers of length 400 km and 500 km. A transmission bit rate of 10 Gbits/sec is used to simulate the OFDM-ROF-PON system. The performance of the system has been analyzed with acceptable Quality Factor and Bit Error Rate at low signal input power in the presence of fiber non-linearities. Also the system does not use any amplifiers and the work is done at higher bit rates. It is analyzed that as the input power increases quality factor also increases and bit error rate decreases.
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27

Selasi, Andrew, Ernest Ofosu, and Benjamin Kommey. "A 3-Bit 10-MSps Low Power CMOS Flash ADC." Communications on Applied Electronics 7, no. 22 (November 30, 2018): 21–26. http://dx.doi.org/10.5120/cae2018652796.

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28

Rikan, Behnam Samadpoor, Hamed Abbasizadeh, Sung-Han Do, Dong-Soo Lee, and Kang-Yoon Lee. "Digital Error Correction for a 10-Bit Straightforward SAR ADC." IEIE Transactions on Smart Processing and Computing 4, no. 1 (February 28, 2015): 51–58. http://dx.doi.org/10.5573/ieiespc.2015.4.1.051.

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29

Dong, Shang-Ching, and Bradley S. Carlson. "10 bit, 25 MHz, 15 MW CMOS pipelined subranging ADC." Computer Standards & Interfaces 21, no. 2 (June 1999): 106. http://dx.doi.org/10.1016/s0920-5489(99)91953-0.

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30

Tseng, Chien-Jian, Yi-Chun Hsieh, Ching-Hua Yang, and Hsin-Shu Chen. "A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC." IEEE Transactions on Circuits and Systems I: Regular Papers 60, no. 11 (November 2013): 2902–10. http://dx.doi.org/10.1109/tcsi.2013.2256212.

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31

SARAFI, SAHAR, KHEYROLLAH HADIDI, EBRAHIM ABBASPOUR, ABU KHARI BIN AAIN, and JAVAD ABBASZADEH. "100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION." Journal of Circuits, Systems and Computers 23, no. 05 (May 8, 2014): 1450057. http://dx.doi.org/10.1142/s0218126614500571.

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This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.
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32

Bringas, R., F. Dy, and O. J. Gerasta. "10-bit segmented current steering DAC in 90nm CMOS technology." IOP Conference Series: Materials Science and Engineering 79 (June 10, 2015): 012005. http://dx.doi.org/10.1088/1757-899x/79/1/012005.

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33

Nakamura, Michinori, Yasuhiro Sugimoto, Toshiya Watanabe, and Takashi Sugimoto. "A 10-Bit 65MSPS Glitch-free Video D/A Converter." IEEE Transactions on Consumer Electronics CE-31, no. 3 (August 1985): 592–600. http://dx.doi.org/10.1109/tce.1985.289975.

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34

BANIHASHEMI, M. "A Low-Power, Small-Size 10-Bit Successive-Approximation ADC." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 4 (April 1, 2005): 996–1006. http://dx.doi.org/10.1093/ietfec/e88-a.4.996.

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35

ITO, T. "Low-Power Design of 10-bit 80-MSPS Pipeline ADCs." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, no. 7 (July 1, 2006): 2003–8. http://dx.doi.org/10.1093/ietfec/e89-a.7.2003.

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36

Van Praet, C., G. Torfs, Z. Li, X. Yin, D. Suvakovic, H. Chow, X. Z. Qiu, and P. Vetter. "10 Gbit/s bit interleaving CDR for low-power PON." Electronics Letters 48, no. 21 (2012): 1361. http://dx.doi.org/10.1049/el.2012.3200.

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37

Yu, J., M. F. Chang, S. Beccue, W. J. Ho, K. C. Wang, and P. Zampardi. "10 bit 200 MSPS GaAs BiFET sample and hold circuit." Electronics Letters 31, no. 16 (August 3, 1995): 1335–37. http://dx.doi.org/10.1049/el:19950947.

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38

Yi, Shu-Chung. "A 10-bit current-steering CMOS digital to analog converter." AEU - International Journal of Electronics and Communications 69, no. 1 (January 2015): 14–17. http://dx.doi.org/10.1016/j.aeue.2014.07.010.

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39

Harris, Richard W., Robert H. Brey, Yuan-Shu Chang, B. Diann Soria, and Laurence M. Hilton. "The Effects of Digital Quantization Error on Speech Intelligibility and Perceived Speech Quality." Journal of Speech, Language, and Hearing Research 34, no. 1 (February 1991): 189–96. http://dx.doi.org/10.1044/jshr.3401.189.

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The effects of digital quantization error upon speech intelligibility and perceived speech quality, for normally hearing subjects, were investigated for digitized speech processed to simulate 6-, 8-, 10-, 12-, 14-, and 16-bit integer conversion and 2-, 3-, 4-, 5-, 6-, and 7-bit floating-point conversion. For the integer data, there were no significant differences in speech intelligibility for 8- to 16-bit conversion. Only 6-bit integer conversion at 55 dB SPL resulted in a significant degradation in speech intelligibility. For the floating-point data, there were no significant differences in speech intelligibility for 2- to 7-bit floating-point conversion. However, results of the perceived quality experiment appeared to be more sensitive to differences among the various conditions. Speech processed using 12-, 14-, and 16-bit integer conversion was judged to be superior to speech processed using the 6-, 8-, and 10-bit integer conditions. Speech processed using 5-, 6-, and 7-bit floating-point conversion was judged to be superior to speech processed using 2-, 3-, and 4-bit floating-point conversion.
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40

Jeong, Yeon-Ho, and Young-Chan Jang. "A 10-bit 10-MS/s Asynchronous SAR analog-to-digital converter with digital-to-analog converter using MOM capacitor." Journal of the Korea Institute of Information and Communication Engineering 18, no. 1 (January 31, 2014): 129–34. http://dx.doi.org/10.6109/jkiice.2014.18.1.129.

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41

Muthers, D., and R. Tielert. "Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2." Advances in Radio Science 2 (May 27, 2005): 205–9. http://dx.doi.org/10.5194/ars-2-205-2004.

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Abstract. Ein 10 bit 10MS/s Analog-Digital- Wandler mit niedriger Leistungaufnahme von 8,4mW wurde implementiert. Der geringe Flächenbedarf von 0,11mm2 macht diesen Wandler besonders geeignet f¨ur Multikanalanwendungen. Um die Anforderungen von 10 bit, 10 MS/s möglichst effizient zu erfüllen wurde eine zyklische Wandlerarchitektur gewählt, die in einem 0,18μm-CMOSProzess mit MIM-Kondensatoren implementiert wurde. Der entworfene ADC wurde in 21 parallelen Kanälen auf einem mixed-signal-Chip zusammen mit digitalen Filtern, vier RISC-CPUs und I/O-Schaltungen implementiert. A 10 bit 10MS/s Analog to Digital Converter, consuming a power of 8,4mW, has been implemented. Due to the small area of 0,11mm2 this ADC is highly suited for multichannel implementations. A cyclic converter architecture is best suited for this application, being implemented in a 0,18μm CMOS process with MIM-capacitors. The designed ADC was implemented in an array of 21 channels on a mixed signal chip together with digital filters, four RISC-CPUs and I/O circuitry.
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42

Jeong, Yeon-Ho, and Young-Chan Jang. "A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC." Journal of the Korean Institute of Information and Communication Engineering 17, no. 2 (February 28, 2013): 414–22. http://dx.doi.org/10.6109/jkiice.2013.17.2.414.

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43

Naderi, Meysam, and Ehsan Khamehchi. "Application of Optimized Least Square Support Vector Machine and Genetic Programming for Accurate Estimation of Drilling Rate of Penetration." International Journal of Energy Optimization and Engineering 7, no. 4 (October 2018): 92–108. http://dx.doi.org/10.4018/ijeoe.2018100105.

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This article describes how the accurate estimation of the rate of penetration (ROP) is essential to minimize drilling costs. There are various factors influencing ROP such as formation rock, drilling fluid properties, wellbore geometry, type of bit, hydraulics, weight on bit, flow rate and bit rotation speed. This paper presents two novel methods based on least square support vector machine (LSSVM) and genetic programming (GP). Models are a function of depth, weight on bit, rotation speed, stand pipe pressure, flow rate, mud weight, bit rotational hours, plastic viscosity, yield point, 10 second gel strength, 10 minute gel strength, and fluid loss. Results show that LSSVM estimates 92% of field data with average absolute relative error of less than 6%. In addition, sensitivity analysis showed that factors of depth, weight on bit, stand pipe pressure, flow rate and bit rotation speed account for 93% of total variation of ROP. Finally, results indicate that LSSVM is superior over GP in terms of average relative error, average absolute relative error, root mean square error, and the coefficient of determination.
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44

Raj, Keshav, Bharti Sharma, Neeraj Kumar, and Dr Dalveer Kaur. "Differential Cryptanalysis on S-DES." INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY 1, no. 2 (July 26, 2012): 42–45. http://dx.doi.org/10.24297/ijmit.v1i2.1445.

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In this paper differential attack on S-DES is carried out. S-DES is the reduced version of DES algorithm. This algorithm operates on 8-bit message block with 10-bit key and DES operates on 64-bit message block with 56-bit key. This paper analyzed the differential attack on S-DES. Differential attack is used to break a cipher by trying each possible key.
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45

Ahn, Cheol-Min, and Young-Sik Kim. "A 8-bit 10-MSample/s Folding & Interpolation ADC using Preamplifier Sharing Method." Journal of IKEEE 17, no. 3 (September 30, 2013): 275–83. http://dx.doi.org/10.7471/ikeee.2013.17.3.275.

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46

Yang, Yu Jun, Wei Hu, Jun Liu, Zhou Yu, Dong Bing Fu, and Guang Bing Chen. "Design of a 10 Bit 2GHz Digital to Analog Converter Circuit." Applied Mechanics and Materials 713-715 (January 2015): 942–45. http://dx.doi.org/10.4028/www.scientific.net/amm.713-715.942.

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This paper presents the design of a 10 bit 2GHz digital to analog converter circuit. The digital to analog converter circuit adopts the design simulation of HBT process, able to work at a sampling frequency of 2 GHz, the highest sampling frequency can reach about 4 GHz. The SFDR of the digital to analog converter circuit can reach 62dB (simulation work at 2 GHz), the SFDR can reach 45 dB (simulation work at 4 GHz). Early product parameters of the digital to analog converter circuit (working in 1 GHz sampling frequency) are as follows: the narrowband SFDR parameter can be achieved 81 dB, broadband SFDR parameters can reach 46 dB.
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47

Cui, Zhi-Yuan, Hua-Lan Piao, and Nam-Soo Kim. "A 10-bit Current-steering DAC in 0.35-μm CMOS Process." Transactions on Electrical and Electronic Materials 10, no. 2 (April 25, 2009): 44–48. http://dx.doi.org/10.4313/teem.2009.10.2.044.

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48

Zhu, Zhangming, Yu Xiao, Lifeng Xu, Haoyu Ding, and Yintang Yang. "An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC." Analog Integrated Circuits and Signal Processing 77, no. 2 (September 19, 2013): 249–55. http://dx.doi.org/10.1007/s10470-013-0133-8.

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49

Huang, Jiaoying, Yigang He, Yichuang Sun, Hui Liu, and Hui Yang. "A 10-bit 200-MHz CMOS video DAC for HDTV applications." Analog Integrated Circuits and Signal Processing 52, no. 3 (September 20, 2007): 133–38. http://dx.doi.org/10.1007/s10470-007-9105-1.

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50

KIM, J. H. "A True 10-bit Data Driver LSI for HDTV TFT-LCDs." IEICE Transactions on Electronics E89-C, no. 5 (May 1, 2006): 585–90. http://dx.doi.org/10.1093/ietele/e89-c.5.585.

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