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Dissertations / Theses on the topic '12-bit'

Author: Grafiati

Published: 30 June 2021

Last updated: 4 February 2022

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1

Ricci, Luca. "Design of a 12-bit 200-MSps SAR Analog-to-Digital converter." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-284559.

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The Successive Approximation (SAR) Analog-to-Digital converter is one of the most energy-efficient A/D converter. In this thesis, the development of a SAR ADC in a 28-nm CMOS technology based on charge redistribution is presented.The implemented SAR ADC uses a switching procedure based on a modified version of the mono- tonic switching algorithm to reduce the switching energy and area of the DAC. The DAC is a binary- weighted array of unit capacitors. A unit custom capacitor has been designed with a value of 0.8 fF to reduce the DAC energy consumption. Two comparators have been implemented, a

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Todorov, Borislav St. "Performance evaluation of 12 and 14-bit converter technology for software radio applications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0016/MQ57742.pdf.

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Todorov, Borislav St (Borislav Stefanov) Carleton University Dissertation Engineering Systems and Computer. "Performance evaluation of 12 and 14-bit converter technology for software radio applications." Ottawa, 2000.

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4

Nuytkens, Peter R. (Peter Read). "A 12-bit 500 MHz GaAs MESFET digital-to-analog converter with p+ ohmic contact isolation." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/12760.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992.<br>Vita.<br>Includes bibliographical references (leaves 134-135).<br>by Peter R. Nuytkens.<br>M.S.

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Thomsson, Pontus, and Aghamiri Cyrus Seyed. "Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177548.

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Wireless communication technologies continue to evolve to meet the demand for increased data throughput. To achieve higher data throughput one approach is to increase the bandwidth. One problem related to very large bandwidths is the implementation of digital-to-analog converters with sampling rates roughly in the 5 to 20 GHz range. Traditionally, current-steering data converters have been the go-to choice but their linearity suffers at higher frequencies. An alternative to the current-steering digital-to-analog converter is the voltage-mode digital-to-analog converter, which is an attractive

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Juo, Ru-Hung, and 卓儒宏. "12-bit Digital Transmitter for VDSL." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/qqzuha.

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碩士<br>國立臺北科技大學<br>電機工程系研究所<br>99<br>This thesis describes the chip implementation of a 200 MHz CMOS digital transmitter based on VDSL system specification. which is composed of a 12-bit, 200 MHz digital to analog converter, and a fully differential current-mode line driver. The digital transmitter had been fabricated with the TSMC 0.18 μm 1P6M CMOS technology. For high-speed application, the digital to analog converter adopts the switch-current mode architecture. This is a 12-bit digital-to-analog converter (DAC) is implemented with M-bit segmented, which is implemented with 3-bit binary and 9

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Sheng-YangWeng and 翁聖洋. "A 14-Bit 2GS/s and 12-Bit 4GS/s Reconfigurable DAC with Triple Modes." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/33707004393574784529.

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碩士<br>國立成功大學<br>電機工程學系<br>102<br>In this thesis, a triple-mode 14-bit 2GS/s or 12-bit 4GS/s reconfigurable current-steering digital-to-analog converter (DAC) is presented. For different DAC applications, triple mode is proposed, which means over-sampling mode, Nyquist mode, and over-Nyquist mode. The target of this work is that using a single DAC chip to fulfill all of the applications and with better performances than any state-of-the-art work. For this target, many techniques are proposed to improve the performances. In current-steering DAC design, current source mismatch is a main problem.

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Hsiao, Ming-Kai, and 蕭名開. "12-Bit low power SAR-ADC for ECG application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/05793753502319870096.

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碩士<br>淡江大學<br>電機工程學系碩士在職專班<br>99<br>With the constant improvement on highly advanced technology nowadays, under the development of the microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP) influence, Analog to Digital Converter (ADC) has become a widely used application. The request for ADC specification will therefore be strict, as a result, more research will be conducted aggressively in the industrial and academic field. In order for ADC application become extensively used and correspond to the requirement of the present electronic products, fo

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Lin, Chi-shen, and 林綮紳. "A 12-bit Power Saving DAC with Clock Controller." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/7f3sus.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>102<br>In this thesis, A 12-bit 1GS/s DAC for wireless communications is proposed. In order to achieve the high performance requirements, the current-steering architecture is the most suitable and widely used in the present design. The segmented current steering architecture that comprises 8MSB’s thermometer code and 4LSB’s binary-weighted is used. In this design, a new technique of the column clock controller (CCC) is proposed to improve the DAC performance. The Column clock controller (CCC) is able to reduce the clock feed-through effect for DAC and reduce power

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LAI, CHENG-QIAN, and 賴承謙. "Ultra Low Power 12-Bit Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/yvz8sn.

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Wei-ChengHung and 洪偉程. "A 12-bit 2GS/s Current-Steering DAC in 0.07mm2." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/19395243757378184961.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>101<br>In this thesis, a 12-bit 2GS/s current-steering DAC design is presented to overcome the three main nonlinearity sources, which are current source mismatch, output transition nonlinearity, and finite output impedance, and achieve high-speed high-resolution characteristic. Firstly, for the current source mismatch, two different dynamic element matching (DEM) algorithms, random rotation-based binary-weighted selection (RRBS) and data weighted averaging (DWA), are adopted to process the harmonic distortion tones caused by mismatch error for different applicatio

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12

Ghezawi, Saeed Ramzi. "Characterization of a 12-bit pipeline analog to digital converter." 2009. http://etd.utk.edu/2009/May2009Theses/GhezawiSaeedRamzi.pdf.

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13

Jih, Wei-Shu, and 日韋舒. "Design and Implementation of 12-bit Sub-ranged SAR ADCs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/cq776s.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>106<br>This thesis is aimed to present 12-bit Sub-ranged successive approximation register (SAR) analog-to-digital converters (ADCs). In order to speed up the sampling rate, the ADC architecture is proposed using the subrange SAR operation. Besides, by applying a new dynamic latch logic architecture, the DAC control delay between the comparator output and DAC switch is reduced. Thus, the sampling rate of the ADC is also improved. To achieve the 12-bit linearity requirement, the binary-window and capacitor-swapping switching techniques are applied in the DAC. Two ADCs

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Hsu, Wei-Hung, and 徐偉宏. "A 12-bit 250-MSample/sec Digital-to-Analog Converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/50738999911029568589.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>92<br>The goal of this research was to design a low power 12-bit, 250 MHz digital-to-analog converter suitable for applications in video. The proposed DAC composed of segmented coding method for MSB and LSB bits, where the thermometer way for MSB and binary-weighted for LSB. Besides, to promote linearity of performance and suppress undesired glitch, the signal controlled differential switches of current sources is pre-processed by de-glitch latch. There is trade-off between accuracy and area for mismatch issue of current sources. The routing complexity and parasit

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Gandara, Miguel Francisco. "A 12-bit, 10 Msps two stage SAR-based pipeline ADC." 2012. http://hdl.handle.net/2152/19973.

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The market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required for digital signal processing elements and micro-processors. For these applications, power efficiency and accuracy are of the utmost importance. Successive approximation register (SAR) ADCs are frequently used in power constrained applications, but their main limitation is their low sampling rate. In this work, a two stage pipelined ADC is present

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Lee, Chien-Wei, and 李建緯. "A 12-bit High Speed DAC with Novel Self-Calibrated Technique." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/88294442353421270077.

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碩士<br>國立中正大學<br>電機工程所<br>95<br>We design the Digital-to-Analog Converter (DAC) with Current-Steering architecture to achieve high-speed specification and propose a novel calibration technique in this thesis. The technique could directly suppress the differential nonlinearity (DNL) and integral nonlinearity (INL) and furthermore lift up dynamic performance to increase the linearity of whole DAC effectively. By this technique, we have attained the destination of high speed, high resolution and low power consumption because of successfully improving the drawback caused by requiring large scale ar

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Chou, Wen-Duen, and 周文敦. "12-bit/200MHz Digital Transmitter with Double Sampling-Rate for VDSL." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/28ctf3.

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碩士<br>國立臺北科技大學<br>電機工程系所<br>101<br>This thesis describes the chip implementation of a 200MHz/double sampling-rate CMOS digital transmitter based on VDSL system specification. This digital transmitter is composed of a 12-bit, 200MHz digital-to-analog converter (DAC) operated in the proposed double sampling-rate structure, and a fully differential current-mode line driver integrated with a 2nd-ordered transmitting filter. The digital transmitter had been fabricated with the TSMC 0.18μm 1P6M CMOS technology. VDSL (Very High-Bit Rate Digital Subscriber Line) technology permits the transmission of

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Tsung-HsienLin and 林宗賢. "A 12-bit 3GS/s 4xTI Pipelined ADC with DigitalBackground Calibration." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/3u3jex.

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Hsieh, Yi-Cheng, and 謝易成. "12-bit SAR ADC with Mixed Switching and Background Offset Calibration." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ngq679.

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碩士<br>國立交通大學<br>電機工程學系<br>106<br>This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure is applied. The mixed switching procedure combines the merged capacitor switching with monotonic switching. Beside, two dynamic comparators with charge pump and adaptive capacitor calibration to achieve lower offset are used. For the SAR ADC with charge pump at 1.8V supply voltage and 10MHz sampling ra

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Chen, Chien-Chung, and 陳建仲. "An Area-Efficient 12-bit 20 MHz Two-Step SAR ADC." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/t295d5.

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碩士<br>國立清華大學<br>電子工程研究所<br>107<br>This thesis describes an analog-to-digital converter (ADC) for FHD image sensors. The ADC specification is 12-bit resolution and the sampling rate is 20 MHz. The architecture of this ADC is two-step successive approximation register (SAR) ADC. The disadvantage of the traditional SAR ADC is the great area of capacitor. When we add every 1-bit resolution, the area of the capacitor will double. In this thesis, the number of unit capacitor of the two-step SAR ADC is reduced to 1/16th of that of a conventional 12-b SAR ADC. The prototype was fabricated using TSMC 0

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Chiang, Min-Sheng, and 江民陞. "Design and Implementation of 12-bit Ultra-Low-Power SAR ADCs." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/67t8b9.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>107<br>This thesis is aimed to present 12-bit Ultra low power successive approximation register (SAR) analog-to-digital converters (ADCs). In order to save the power, the ADC architecture is proposed using the synchronous clocking operation and low voltage supply. Besides, by applying a bypass window for EKG signals. To achieve the 12-bit linearity requirement, the bypass window and capacitor-swapping switching techniques are applied in the DAC. Two ADCs were implemented in UMC 180 nm CMOS process. The first one is a 12-bit Synchronous-SAR ADC for IoT applications, w

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Lee, Yueh-Ru, and 李岳儒. "Design of 12-bit SAR ADCs with Analog Background Calibration Technique." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5gjh23.

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碩士<br>國立交通大學<br>電機工程學系<br>107<br>In this thesis, the design consideration of low-speed, mid/high resolution successive approximation register analog-to-digital converters (SAR ADCs) is discussed in depth. The three mentioned ADCs are all designed for biomedical applications, such as the external signal receiver of bone-guided cochlear implants. All the ICs were fabricated by using 0.18-μm 1P6M TSMC CMOS process. The first IC is a 10-bit 47KS/s SAR ADC which adopts monotonic switching technique. Due to the layout simplicity of the digital blocks, the power consumption is as low as 2.6μW. At nor

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Huang, Chia-Hsuan, and 黃嘉玄. "Low Power 12-bit Successive Approximation ADC for Biomedical Acquisition System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/82543200626928576057.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>Generally, the signal bandwidth of biomedical signals ( EEG, ECG, Oxygen Saturation, Heart Rate, Temperature ) is under 10 kHz [29]. For portable biomedical acquisition system, lower power A/D converter is an important component that can determine the performance of whole system. In this paper, a 1.8V 12-bit 200-kS/s successive approximation analog-to-digital converter (SAR ADC) is presented in this work. In order to overcome the biomedical signal’s dc shift and acquire accurately, the proposed ADC receives rail-to-rail input and performs 12-bit resolution (

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Sousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Dissertação, 2009. http://hdl.handle.net/10216/57854.

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Estágio realizado no CERN e orientado pelo Doutor Paulo Rodrigues Simões Moreira<br>Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

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Yen, Chia-Wei, and 顏嘉威. "Design and Implementation of a 12-bit 100-MS/s SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/74411232626403249189.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>105<br>This thesis presents a 12bit 100MS/s successive approximation register analog to digital converter (SAR ADC). Sub-ranged SAR architecture is used to achieve 100MS/s sampling rate. This ADC design is based on SAR architecture but with sub-ranged operation. A low resolution and high speed binary-search ADC is used to quantize first five MSBs for speeding up. For 12-bit linearity requirement, capacitor swapping technique is used in digital to analog converter (DAC) to prevent the use of large capacitor array. This ADC was implemented in TSMC 65nm digital CMOS pro

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Wang, Chih-Cheng, and 王智正. "A 12-BIT SEGMENTED DIGITAL-TO-ANALOG CONVERTOR FOR LCD DRIVER ICS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/00210556998549254472.

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碩士<br>大同大學<br>通訊工程研究所<br>98<br>In this thesis, a linear 12 bit segmented digital-to-analog converter (DAC) for LCD source driver is proposed. This design employs a method that reduces the area of an LCD source driver without increasing extra power consumption. A typical 12-bit resistor-string DAC requires a 4096-to1 selector. The proposed architecture uses three sets of 4-bit subDACs to reduce the complexity of a 12-bits resistor-string DAC. The digital signal selects 3 voltages from the tree subDACs, and then adds these voltages up by a Switched-Capacitor (SC) adder. The Opamp of the SC adder

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Tsai, Tsung-Yen, and 蔡宗諺. "A 12-bit 500-MSamples/s Current-Steering CMOS D/A Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/94140123580238255874.

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碩士<br>國立交通大學<br>電信工程系所<br>95<br>Digital-To-Analog converters are essential components of modern applications, such as digital signal synthesis, video signal processing, and both wired and wireless transmitters.For data converters used in communications applications, the integral nonlinearity (INL) and differential nonlinearity (DNL) are not sufficient to characterize the performance. It is more convenient to characterize the performance in the frequency domain using measures as the spurious-free dynamic range (SFDR). The major target specification for SFDR of this paper, a 12-bit 500-MSam

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Sousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Master's thesis, 2009. http://hdl.handle.net/10216/57854.

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Estágio realizado no CERN e orientado pelo Doutor Paulo Rodrigues Simões Moreira<br>Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

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Yi-AnChao and 趙一安. "A 12-bit 100MHz DAC with Dynamic Element Matching and Output Impedance Calibration." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/56113954744671940792.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>98<br>Current-steering DAC can drive external loads, and usually used in high speed application. In recent years, many digital-to-analog converters have been implemented in advanced process, especially in 130nm, 90nm, and CMOS process. However, as far as the cost is concerned, the area of chip is getting as smaller as possible. In this thesis, a low-cost high resolution and high speed DAC is implemented. A new Dynamic Element Matching (DEM) algorithm is proposed. This algorithm can resist the mismatch error of current source. The effect of Dynamic Element Matching

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Wei, Chia-Liang, and 魏嘉良. "A Low Power 12-bit 100KSample/s Successive- Approximation Analog-to-Digital Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/09580713306729557654.

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碩士<br>國立暨南國際大學<br>電機工程學系<br>99<br>In this thesis, A low power 12-bit 100KSample/s successive-approximation(SAR) analog-to-digital converter(ADC) is presented. The ADC contains a sample and hold circuit(S/H), a digital-to-analog converter(DAC), a latched comparator, and a successive-approximation register(SAR). The ADC is constructed by using binary search to the reference voltage in order to using a simple comparator. The DAC employs the hybrid structure including a C-2C capacitors array and a binary-weighted capacitors array, which reduces the power consumption. The 12-bit 100 KSample/s SAR A

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Wang, Yu-Chung, and 王玉忠. "A LCD SOURCE DRIVER WITH 12-BIT PIECEWISE LINEAR DIGITAL-TO-ANALOG CONVERTOR." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/65675397718599607485.

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碩士<br>大同大學<br>電機工程學系(所)<br>99<br>This thesis is to improve liquid crystal displays for color saturation and Gamma correction, and a piecewise linear 12-bit segmented digital-to-analog converter (DAC) for LCD source driver is proposed. The data conversion is carried out by an 8-bit resistor-string type DAC (R-DAC) and a 4-bit charge sharing DAC (C-DAC), which are used for the most significant bit and least significant bit data conversions, respectively. Piecewise linear compensation is utilized to reduce the die area and increase the effective color depth. In addition, Gamma correction can be a

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Shen, Yu-Chen, and 沈游城. "A 12-BIT 50-MS/S BUILT-IN ANALOG SELF-CALIBRATED PIPELINE ADC." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/77935746102177460675.

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碩士<br>大同大學<br>電機工程學系(所)<br>94<br>This thesis describes a design of a low-power, 12-bit, 50Msample/s, and 3.3-V supply pipeline analog-to-digital converter (ADC). In order to achieve the requirements of digital imaging, where differential nonlinearity (DNL) and integral nonlinearity (INL) are both important, we propose a built-in analog self-calibrated circuit of the ADC in this thesis. Compared with the ADC with the typical digital error correction architecture, our circuit does not need a large and complex digital circuit, but they are replaced by the self-calibration capacitor array and line

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"Design and Calibration of a 12-Bit Current-Steering DAC Using Data-Interleaving." Master's thesis, 2014. http://hdl.handle.net/2286/R.I.26805.

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abstract: High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required

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Chang, Yung-Te, and 張永德. "A 12-bit zero-crossing-based pipelined-SAR ADC with single-polarity transfer." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t7wu3n.

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碩士<br>國立清華大學<br>電機工程學系所<br>107<br>This thesis presents a 12-bit zero-crossing-based pipelined-SAR (successive-approximation register) analog-to-digital converter with single-polarity transfer. The proposed ADC operates on pipelined mode and uses single-polarity transfer zero-crossing detection instead conventional multiplying digital-to-analog converter to achieve a higher operation speed and save power. The proposed single-polarity transfer zero-crossing detection can improve the power consumption from MDAC in pipelined ADC effectively and the error sources from the differential mode, which c

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Dai, Yu-Kai, and 戴于凱. "12-Bit 500MHz Digital-to-Analog Converter Based on Highly Matching Current Mirror." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/21554786935199671737.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>In recent years, communication systems require high speed and resolution Digital-to-Analog Converter. For high speed operation, the work employed a current-steering and differential pair architecture. In circuit part, output impedance is restricted by the low supply voltage and MOS short-channel effect. Therefore, designing an accurate current source array is extremely difficult. The Digital-to-Analog Converter with a highly matching current mirror circuit is proposed in this work. The precision of this current source array can be obtained. The proposed 500MHz

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Lei, Kin-Man, and 李健文. "A 12-bit 25MS/s Asynchronous SAR ADC With All Digital Background Calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/07793099824693147628.

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碩士<br>國立交通大學<br>電控工程研究所<br>100<br>The resolution of a SAR ADC is mainly limited by the accuracy of capacitor ratios. Foreground and background calibration schemes [1][2][3][4][5] have been proposed to calibrate the capacitor weight errors. However, both kinds of calibration schemes may suffer from power and speed penalties. The foreground calibration schemes using charge redistribution have the advantage of simple implementation but the continuous variations of environmental parameters may cause it failed. The background calibration schemes can address the variation problems but its hardware i

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Huang, Shao-Hung, and 黃少宏. "A Low Power 12-bit SAR ADC with Split Capacitor Array for Biomedical Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/86945961070280859000.

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碩士<br>淡江大學<br>電機工程學系碩士班<br>100<br>Under the development of microcomputer system, Very Large Scale Integrated circuit (VLSI) and Digital Signal Processing (DSP), Analog to Digital Converter (ADC) relted applications has been widely used. Speed, resolution, power consumption, and area are the four key specifications while designing ADC. Under the limitations of the actual conditions, trade-off was made within these four specifications in order to design the most appropriate ADC converter. This thesis refers to the 12-Bit SAR-ADC which is mainly used in electrocardiogram (ECG) measurement system.

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Cheng, Ju-tien, and 鄭如恬. "A 12-bit Column-parallel Cyclic Analog-to-Digital Converter for CMOS Image Sensors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/68850192822754286755.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>94<br>Images in digital format is the most effective way for analysis, storage, and operation. The imager is the front-end of any machine vision system. There are two major type imager, Charge Coupled Device (CCD) and Complementary Metal-Oxide Semiconductor (CMOS). In order to achieve the function of digital image output, modern imaging system are typically implement with signal digitization function. For example, a traditional CCD camera system with a single analog output channel can be implemented with an independent single-chip ADC to convert analog image signa

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Hwa-AnTseng and 曾華安. "A 12-bit 50-MS/s Time-Interleaved Successive-Approximation Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/qh4xu4.

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Li-JenChang and 張力仁. "A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/22jsa9.

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碩士<br>國立成功大學<br>電機工程學系<br>107<br>A 12-bit 10-MS/s calibration-free successive-approximation register (SAR) analog-to-digital converter (ADC) in 180-nm process is presented in this thesis. This work adopts two techniques, namely residue oversampling and detect-and-skip (DAS) algorithm. For each sample voltage, the residue oversampling technique generates different residual voltages by dynamically rearranging different weights to different capacitors in the capacitor array. These residual voltages would be quantized to generate digital codes with higher accuracy. Besides, the switching procedure

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Su, Yen-Ying, and 蘇彥熒. "A 12‐bit Column‐parallel Cyclic Analog‐to‐Digital Converter for CMOS Image Sensors." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/03752608734621050278.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>93<br>ABSTRACT Images in digital format is more convenient for analysis, storage, and operation. In order to achieve the function of digital image output, modern imaging systems are typically implement with signal digitization function. For example, a traditional CCD camera system with a single analog output channel can be implemented with an independent single-chip ADC to convert analog image signal to digital format. However, this traditional architecture faces the insufficient frame-rate limitation as high quality, high resolution digital images are require

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Ni, Hung-Po, and 倪宏博. "Design and Implementation of 12-bit SAR ADCs with Binary-Window DAC Switching Technique." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/05097672315184836784.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>105<br>This dissertation implements two successive-approximation registers (SAR) analog-to-digital converters (ADCs). The first is a 12-bit 20-MS/s SAR ADC in UMC 0.18µm CMOS. The second is a 12-bit 60-MS/s SAR ADC in UMC 55nm LPCMOS. In order to avoid large capacitance to meet the linearity requirement for DAC, we propose two switching techniques. There are the binary-window DAC switching technique and the capacitor-swapping technique to solve the problem of linearity. The first SAR ADC was fabricated in UMC 0.18µm CMOS. The die area is 2.25mm2 and ADC uses a chip a

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Guo, Rong-Jhou, and 郭榮洲. "Design of a 12-bit, Ultra-low Power Successive Approximation Analog-to-Digital Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/32630405104494533917.

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碩士<br>國立交通大學<br>電機與控制工程系所<br>96<br>This paper presents a 12-bit, ultra low power successive approximation analog-to-digital converter in TSMC 0.18μm 1P6M CMOS process. The analog-to-digital converter uses the offset-free pre-amplifiers to alleviate the impacts of the comparator’s offset. The bridging capacitive DAC is adopted to reduce the nonlinearity and to save the power of the DAC. The pre-amplifiers with a rail-to-rail input range are used to make the input range of the ADC also rail-to-rail. We used a diode-connected transistor in parallel with a negative resistor as the loads of the pre

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Wei, Yen-Hsin, and 魏衍昕. "A 12-bit 600MS/s Time-Interleaved SAR ADC with Background Timing Skew Calibration." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/19086299833215672228.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>103<br>A four channel time-interleaved 12-b SAR ADC, employing the proposed digital calibration technique to correct timing skew, achieves a 600-MHz sampling rate. The interleaved ADC composed of four channel SAR ADC. Digital mixing method is used to estimate timing skew, and proposed dual core with delay sampling is used to correct the timing skew. The ADC has been fabricated in a 40-nm CMOS technology, improves interleaving spurious tones from -50dB to -76dB and achieves a 61.7-dB SNDR while dissipating 23 mW from a 0.9-V power supply. The figure of merit (FoM) is

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Pannell, Zachary William. "Design of a Highly Constrained Test System for a 12-bit, 16-channel Wilkinson ADC." 2009. http://trace.tennessee.edu/utk_gradthes/549.

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Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed th

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Hsu, Pei-Jung, and 許倍榮. "A 12-bit 100-MS/s Zero Crossing Based Pipelined ADC With Current Mismatch Correction." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/22210442056161344047.

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碩士<br>國立中正大學<br>電機工程研究所<br>100<br>This work presents a 12b 100MS/s zero-crossing-based switched-capacitor CMOS pipelined analog-to-digital converter (ADC). The proposed ADC improves the resolution, power efficiency, and sample rate of the fully differential zero-crossing-based circuits and features a 90nm CMOS technology. Offset tolerance, current splitting, and a digital correction scheme were implemented to correct mismatches among current sources. Post-layout simulations show that the SNDR is 72.6dB when the input is close to Nyquist rate. The power consumption is 20.8mW from a 1.2V supply

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Tang, Yi Fu, and 湯益福. "A 12-bit Time-Domain Analog-to-Digital Converter With a Multiphase Voltage-Controlled Oscillator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/93859287530846279552.

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碩士<br>長庚大學<br>電機工程學系<br>100<br>This thesis intends to discuss on how to construct an analog-to-digital conveter (ADC) by using the conversion of time-domain signals. We try to transform the analog voltage signal into digital time-pulse signal hence to form the digitally assisted analog circuit design. In theorical view, while the characteristic length of CMOS gates continuously shrinks to the nano-meter scale, the variations of analog signal increase, the current leakage of gates increases, and the open loop gain decreases…etc., more and more disadvantages occur. Since the accuracy and stabili

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Lin, Wei-Ting, and 林葦婷. "A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/14040227441703086392.

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碩士<br>國立清華大學<br>電機工程學系<br>101<br>This thesis presents a 12-bit 100KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The A/D converter is designed in TSMC 0.18um CMOS process and operates at a supply voltage of 1.8V. The SAR A/D converter includes track-and-hold (T/H) stage, comparator, digital-to-analog converter and SAR control logic. Bootstrapped switch is used in S/H for improving circuit linearity and reducing the signal distortion. The comparator is composed of a dynamic latched regenerative circuit which gives comparator output be

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HouTsung-Tien and 侯宗典. "Design and Implementation of a 12-bit 100 MHz Current-Steering Digital-to-Analog Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/37193550974193948180.

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碩士<br>崑山科技大學<br>電子工程研究所<br>94<br>In this thesis, we realize a 12-bit 100 MHz current-steering digital-to-analog converter (DAC) in TSMC 0.35-um 2P4M mixed signal process technology. The DAC adopts the segmented architecture which comprises a segment of 7-bit into 127 equally weighted current sources in the MSB and a segment of 5-bit binary-weighted current sources in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture. The DAC is simulated by HSPICE using TSMC 0.35-um 2P4M mixed signal process technology. The propo

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Liang, Ming-Chieh, and 梁明傑. "A 12-Bit 200MS/S Current-Steering DAC with TSMC 0.18um PDK Monte-Carlo-Analysis." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/04521674800079642167.

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碩士<br>國立清華大學<br>產業研發碩士積體電路設計專班<br>98<br>We propose a 12-Bit 200MS/S Current-Steering DAC based on a Segmented (5+7) current-steering architecture. In order to decrease the differential nonlinearity error (DNL) and reduce area, we employ Unary-Current cell with thermometer code decoder for the 5MSBs and Binary-Weighted Current Cell for the 7LSBs. In order to synchronize inputs and improve glitch energy, we use a digital latch approach. Differential switch order is very critical for DNL, so we use the Two Dimensional Centroid method. In order to enhance DAC output impedance and SFDR, both the MS

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