Dissertations / Theses on the topic '12-bit'
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Ricci, Luca. "Design of a 12-bit 200-MSps SAR Analog-to-Digital converter." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-284559.
Full textTodorov, Borislav St. "Performance evaluation of 12 and 14-bit converter technology for software radio applications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0016/MQ57742.pdf.
Full textTodorov, Borislav St (Borislav Stefanov) Carleton University Dissertation Engineering Systems and Computer. "Performance evaluation of 12 and 14-bit converter technology for software radio applications." Ottawa, 2000.
Find full textNuytkens, Peter R. (Peter Read). "A 12-bit 500 MHz GaAs MESFET digital-to-analog converter with p+ ohmic contact isolation." Thesis, Massachusetts Institute of Technology, 1992. http://hdl.handle.net/1721.1/12760.
Full textThomsson, Pontus, and Aghamiri Cyrus Seyed. "Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177548.
Full textJuo, Ru-Hung, and 卓儒宏. "12-bit Digital Transmitter for VDSL." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/qqzuha.
Full textSheng-YangWeng and 翁聖洋. "A 14-Bit 2GS/s and 12-Bit 4GS/s Reconfigurable DAC with Triple Modes." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/33707004393574784529.
Full textHsiao, Ming-Kai, and 蕭名開. "12-Bit low power SAR-ADC for ECG application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/05793753502319870096.
Full textLin, Chi-shen, and 林綮紳. "A 12-bit Power Saving DAC with Clock Controller." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/7f3sus.
Full textLAI, CHENG-QIAN, and 賴承謙. "Ultra Low Power 12-Bit Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/yvz8sn.
Full textWei-ChengHung and 洪偉程. "A 12-bit 2GS/s Current-Steering DAC in 0.07mm2." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/19395243757378184961.
Full textGhezawi, Saeed Ramzi. "Characterization of a 12-bit pipeline analog to digital converter." 2009. http://etd.utk.edu/2009/May2009Theses/GhezawiSaeedRamzi.pdf.
Full textJih, Wei-Shu, and 日韋舒. "Design and Implementation of 12-bit Sub-ranged SAR ADCs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/cq776s.
Full textHsu, Wei-Hung, and 徐偉宏. "A 12-bit 250-MSample/sec Digital-to-Analog Converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/50738999911029568589.
Full textGandara, Miguel Francisco. "A 12-bit, 10 Msps two stage SAR-based pipeline ADC." 2012. http://hdl.handle.net/2152/19973.
Full textLee, Chien-Wei, and 李建緯. "A 12-bit High Speed DAC with Novel Self-Calibrated Technique." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/88294442353421270077.
Full textChou, Wen-Duen, and 周文敦. "12-bit/200MHz Digital Transmitter with Double Sampling-Rate for VDSL." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/28ctf3.
Full textTsung-HsienLin and 林宗賢. "A 12-bit 3GS/s 4xTI Pipelined ADC with DigitalBackground Calibration." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/3u3jex.
Full textHsieh, Yi-Cheng, and 謝易成. "12-bit SAR ADC with Mixed Switching and Background Offset Calibration." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ngq679.
Full textChen, Chien-Chung, and 陳建仲. "An Area-Efficient 12-bit 20 MHz Two-Step SAR ADC." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/t295d5.
Full textChiang, Min-Sheng, and 江民陞. "Design and Implementation of 12-bit Ultra-Low-Power SAR ADCs." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/67t8b9.
Full textLee, Yueh-Ru, and 李岳儒. "Design of 12-bit SAR ADCs with Analog Background Calibration Technique." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/5gjh23.
Full textHuang, Chia-Hsuan, and 黃嘉玄. "Low Power 12-bit Successive Approximation ADC for Biomedical Acquisition System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/82543200626928576057.
Full textSousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Dissertação, 2009. http://hdl.handle.net/10216/57854.
Full textYen, Chia-Wei, and 顏嘉威. "Design and Implementation of a 12-bit 100-MS/s SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/74411232626403249189.
Full textWang, Chih-Cheng, and 王智正. "A 12-BIT SEGMENTED DIGITAL-TO-ANALOG CONVERTOR FOR LCD DRIVER ICS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/00210556998549254472.
Full textTsai, Tsung-Yen, and 蔡宗諺. "A 12-bit 500-MSamples/s Current-Steering CMOS D/A Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/94140123580238255874.
Full textSousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Master's thesis, 2009. http://hdl.handle.net/10216/57854.
Full textYi-AnChao and 趙一安. "A 12-bit 100MHz DAC with Dynamic Element Matching and Output Impedance Calibration." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/56113954744671940792.
Full textWei, Chia-Liang, and 魏嘉良. "A Low Power 12-bit 100KSample/s Successive- Approximation Analog-to-Digital Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/09580713306729557654.
Full textWang, Yu-Chung, and 王玉忠. "A LCD SOURCE DRIVER WITH 12-BIT PIECEWISE LINEAR DIGITAL-TO-ANALOG CONVERTOR." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/65675397718599607485.
Full textShen, Yu-Chen, and 沈游城. "A 12-BIT 50-MS/S BUILT-IN ANALOG SELF-CALIBRATED PIPELINE ADC." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/77935746102177460675.
Full text"Design and Calibration of a 12-Bit Current-Steering DAC Using Data-Interleaving." Master's thesis, 2014. http://hdl.handle.net/2286/R.I.26805.
Full textChang, Yung-Te, and 張永德. "A 12-bit zero-crossing-based pipelined-SAR ADC with single-polarity transfer." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t7wu3n.
Full textDai, Yu-Kai, and 戴于凱. "12-Bit 500MHz Digital-to-Analog Converter Based on Highly Matching Current Mirror." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/21554786935199671737.
Full textLei, Kin-Man, and 李健文. "A 12-bit 25MS/s Asynchronous SAR ADC With All Digital Background Calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/07793099824693147628.
Full textHuang, Shao-Hung, and 黃少宏. "A Low Power 12-bit SAR ADC with Split Capacitor Array for Biomedical Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/86945961070280859000.
Full textCheng, Ju-tien, and 鄭如恬. "A 12-bit Column-parallel Cyclic Analog-to-Digital Converter for CMOS Image Sensors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/68850192822754286755.
Full textHwa-AnTseng and 曾華安. "A 12-bit 50-MS/s Time-Interleaved Successive-Approximation Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/qh4xu4.
Full textLi-JenChang and 張力仁. "A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/22jsa9.
Full textSu, Yen-Ying, and 蘇彥熒. "A 12‐bit Column‐parallel Cyclic Analog‐to‐Digital Converter for CMOS Image Sensors." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/03752608734621050278.
Full textNi, Hung-Po, and 倪宏博. "Design and Implementation of 12-bit SAR ADCs with Binary-Window DAC Switching Technique." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/05097672315184836784.
Full textGuo, Rong-Jhou, and 郭榮洲. "Design of a 12-bit, Ultra-low Power Successive Approximation Analog-to-Digital Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/32630405104494533917.
Full textWei, Yen-Hsin, and 魏衍昕. "A 12-bit 600MS/s Time-Interleaved SAR ADC with Background Timing Skew Calibration." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/19086299833215672228.
Full textPannell, Zachary William. "Design of a Highly Constrained Test System for a 12-bit, 16-channel Wilkinson ADC." 2009. http://trace.tennessee.edu/utk_gradthes/549.
Full textHsu, Pei-Jung, and 許倍榮. "A 12-bit 100-MS/s Zero Crossing Based Pipelined ADC With Current Mismatch Correction." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/22210442056161344047.
Full textTang, Yi Fu, and 湯益福. "A 12-bit Time-Domain Analog-to-Digital Converter With a Multiphase Voltage-Controlled Oscillator." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/93859287530846279552.
Full textLin, Wei-Ting, and 林葦婷. "A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/14040227441703086392.
Full textHouTsung-Tien and 侯宗典. "Design and Implementation of a 12-bit 100 MHz Current-Steering Digital-to-Analog Converter." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/37193550974193948180.
Full textLiang, Ming-Chieh, and 梁明傑. "A 12-Bit 200MS/S Current-Steering DAC with TSMC 0.18um PDK Monte-Carlo-Analysis." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/04521674800079642167.
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