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Journal articles on the topic '12-bit'

Author: Grafiati

Published: 30 June 2021

Last updated: 29 July 2025

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1

Kaur, Amandeep, Deepak Mishra, and Mukul Sarkar. "A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 1 (2019): 248–52. http://dx.doi.org/10.1109/tvlsi.2018.2871341.

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2

Rout, Shasanka Sekhar, Rajesh Kumar Patjoshi, Sarmila Garnaik, and Ranjita Rout. "Comparative Analysis of Heterogeneous Adders: Evaluating Performance across 12-bit, 14-bit, and 16-bit Configurations." Journal of Information Assurance and Security 19, no. 4 (2024): 136–45. https://doi.org/10.2478/ias-2024-0010.

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Abstract Digital Signal Processing (DSP) heavily relies on repetitive addition and multiplication operations, making adders a crucial component in DSP systems. Likewise, in processor design, an efficient adder circuit is essential for optimizing compactness, achieving high speed, and minimizing power consumption, particularly when utilizing Xilinx technology. This study delves into the exploration and design of an effective adder architecture by examining various parallel, synchronous adders and proposing a novel combination. The presented research introduces heterogeneous adders composed of c

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3

Jayamani, Jayapramila, Noor Diyana Osman, Abdul Aziz Tajuddin, Zaker Salehi, Mohd Hanafi Ali, and Mohd Zahri Abdul Aziz. "Determination of computed tomography number of high-density materials in 12-bit, 12-bit extended and 16-bit depth for dosimetric calculation in treatment planning system." Journal of Radiotherapy in Practice 18, no. 03 (2019): 285–94. http://dx.doi.org/10.1017/s1460396919000013.

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AbstractAimThe main aim was to examine the effect of bit depth on computed tomography (CT) number for high-density materials. Analysis of the CT number for high-density materials using 16-bit scanners will extend the CT scale that currently exists for 12-bit scanners and thus will be beneficial for use in CT–electron density (ED) curve in radiotherapy treatment planning system (TPS). Implementation of this extended CT scale will compensate for tissue heterogeneity during CT–ED conversion in treatment planning.Materials and methodsAn in-house built phantom with 10 different metal samples was sc

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4

Neal, Brent. "Photoshop and 12-bit Digital Microscope Camera Images." Microscopy Today 12, no. 2 (2004): 24–25. http://dx.doi.org/10.1017/s1551929500051956.

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One problem facing owners of high-end digital microscope cameras and scanners is dealing with 12-bit TIFF format images. Because of a vagueness in the TIFF specification [1], some prograins do not load 12-bit TIFF images at all, or do not handle them gracefully. Unfortunately, Adobe Photoshop is one such program.A common problem with 12-bit images that do load in Photoshop is that the image appears to be totally black once loaded. This occurs when the camera stores the most significant bits of the image in the lower 12-bits of a 16-bit data space. Photoshop, when converting to its internal 16-

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5

Sahoo, Bibhu Datta, and Behzad Razavi. "A 12-Bit 200-MHz CMOS ADC." IEEE Journal of Solid-State Circuits 44, no. 9 (2009): 2366–80. http://dx.doi.org/10.1109/jssc.2009.2024809.

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6

Kolluri, M. P. V. "A 12-bit 500-ns subranging ADC." IEEE Journal of Solid-State Circuits 24, no. 6 (1989): 1498–506. http://dx.doi.org/10.1109/4.44985.

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7

Srivastava, Amit K., Atish Sharma, Tushar Raval, and D. Chenna Reddy. "CAMAC based 4-channel 12-bit digitizer." Journal of Physics: Conference Series 208 (February 1, 2010): 012022. http://dx.doi.org/10.1088/1742-6596/208/1/012022.

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8

Wells, S. C., G. J. Williamson, and S. E. Carrie. "Dithering for 12-bit true-color graphics." IEEE Computer Graphics and Applications 11, no. 5 (1991): 18–29. http://dx.doi.org/10.1109/38.90564.

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9

Maimunah, Siti, Amila Amila, Jon Kenedy Marpaung, Vierto Irennius Girsang, and Henny Syapitri. "KARAKTERISASI DAN SKRINING FITOKIMIA DARI TEPUNG BUAH BIT (Beta vulgaris L.)." FORTE JOURNAL 1, no. 2 (2021): 139–45. http://dx.doi.org/10.51771/fj.v1i2.141.

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Buah bit (Beta vulgaris L.) merupakan tanaman yang banyak mengandung senyawa betalain. sumber utama pewarna merah alami. Salah satu inovasi pemanfaatan buah bit yaitu pembuatan tepung bit. Tujuan penelitian ini adalah mengetahui karakterisasi dan skrining fitokimia umbi bit, serta mengetahui tingkat penerimaan umbi bit yang dijadikan tepung bit bagi para panelis. Penelitian ini merupakan eksperimental dengan menguji kandungan senyawa kimia melalui uji karakterisasi dan skrining fitokimia. Hasil penelitian menunjukkan bahwa tepung bit (Beta vulgaris L.) memiliki senyawa alkaloid, tanin, saponin

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10

Xin-ye, Ni, Gao Liugang, Fang Mingming, and Lin Tao. "Application of Metal Implant 16-Bit Imaging: New Technique in Radiotherapy." Technology in Cancer Research & Treatment 16, no. 2 (2016): 188–94. http://dx.doi.org/10.1177/1533034616649530.

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Objective: This study aimed to evaluate the computed tomography number and the variation of dose distribution based on 12-bit, 16-bit, and revised 16-bit images while the metal bars were inserted. Methods: The phantoms containing stainless steel, titanium alloy, and aluminum bar were scanned with computed tomography. These images were reconstructed with 12-bit and 16-bit imaging technologies. The “cupping artifacts” computed tomography value of the metal object revised by Matlab software was called the revised 16-bit image. The computed tomography values of these metal materials were analyzed.

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11

FAN Ci-en, 范赐恩, 吴敏渊 WU Min-yuan, 张立国 ZHANG Li-guo, 邓德祥 DENG De-xiang, and 曹庆源 CAO Qing-yuan. "Companding transformation display for 12 bit image data." Optics and Precision Engineering 19, no. 6 (2011): 1421–28. http://dx.doi.org/10.3788/ope.20111906.1421.

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12

Lu, Jing, Ho Joon Lee, Yong-Bin Kim, and Kyung Ki Kim. "A 12-bit Hybrid Digital Pulse Width Modulator." Journal of the Korea Industrial Information Systems Research 20, no. 1 (2015): 1–7. http://dx.doi.org/10.9723/jksiis.2015.20.1.001.

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13

Рембеза, S. Rembeza, Кононов, and V. Kononov. "12-bit buttongenerator CMOS ADC with SOI-structure." Modeling of systems and processes 6, no. 4 (2014): 53–55. http://dx.doi.org/10.12737/4047.

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The paper architecture CMOS ADC with digital forecasting an inlet of the analog signal and signal transformation errors sectional ADCS from analog to howl convolution. It is shown that 12-bit CMOS ADC with project standards 0.18 micron provides high accuracy and speed of conversion to 600...1000 million samples/s when operating in hard conditions.

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14

R P, Sheetal, and Ameet Chavan. "12 bit Time Interleaved ADC in 65nm Technology." International Journal of Electronics and Communication Engineering 2, no. 10 (2015): 1–7. http://dx.doi.org/10.14445/23488549/ijece-v2i10p102.

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15

Sehgal, Jyoti, and Manoj Kumar. "12-Bit Clock Gated SAR-ADC for Bio-Medical Applications." Indian Journal Of Science And Technology 15, no. 34 (2022): 1648–54. http://dx.doi.org/10.17485/ijst/v15i34.1033.

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16

Hidayat, Achmad, and Fidya Varayesi. "Analisis Performa Tricone Dan Polycrystalline Diamond Compact (PDC) Bit Pada Sumur S11 Menggunakan Metode Cost Per Foot Dan Specific Energy." Jurnal Teknik & Teknologi Terapan 1, no. 1 (2023): 36–43. http://dx.doi.org/10.47970/jttt.v1i1.432.

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Pemilihan jenis bit merupakan salah satu faktor penting dalam operasi pemboran yang diharapkan dapat memberikan laju penembusan yang baik guna mendapatkan hasil yang optimum dan ekonomis. Pada sumur S11 telah diaplikasikan dua jenis bit yaitu roller cone tipe tricone dan PDC bit, dengan melakukan pemboran pada kedalaman 0-2350 ft. Dimana pada sumur S11 ini ada sembilan kali percobaan run bit dengan tiga jenis ukuran bit yang berbeda yakni ukuran 17-1/2”, ukuran 12-1/2” dan yang terakhir ukuran 8-1/2” . Pada run bit yang pertama dan kedua memakai ukuran 17-1/2”, run bit yang ketiga dan ke

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17

AB-AZIZ, M. T. S., A. MARZUKI, and Z. A. A. AZIZ. "12-BIT PSEUDO-DIFFERENTIAL CURRENT-SOURCE RESISTOR-STRING HYBRID DAC." Journal of Circuits, Systems and Computers 20, no. 04 (2011): 709–25. http://dx.doi.org/10.1142/s0218126611007566.

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This paper discusses a hybrid Digital-Analog Converter (DAC) architecture which is a combination of a binary-weighted resistor approach for eight bits in the least-significant-bit and thermometer coded approach for four bits in the most-significant-bit. The proposed design combines advantages of the binary-weighted resistor approach and thermometer coded approach. The final design is composed of two 12-bit DACs to achieve a pseudo differential output signal. The converter was designed with a Silterra 0.18 μm 1.8 V/3.3 V CMOS process technology. The post-layout simulation results show that this

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18

Jin-Sheng Wang and Chin-Long Wey. "A 12-bit 100-ns/bit 1.9-mW CMOS switched-current cyclic A/D converter." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, no. 5 (1999): 507–16. http://dx.doi.org/10.1109/82.769799.

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19

Harris, Richard W., Robert H. Brey, Yuan-Shu Chang, B. Diann Soria, and Laurence M. Hilton. "The Effects of Digital Quantization Error on Speech Intelligibility and Perceived Speech Quality." Journal of Speech, Language, and Hearing Research 34, no. 1 (1991): 189–96. http://dx.doi.org/10.1044/jshr.3401.189.

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The effects of digital quantization error upon speech intelligibility and perceived speech quality, for normally hearing subjects, were investigated for digitized speech processed to simulate 6-, 8-, 10-, 12-, 14-, and 16-bit integer conversion and 2-, 3-, 4-, 5-, 6-, and 7-bit floating-point conversion. For the integer data, there were no significant differences in speech intelligibility for 8- to 16-bit conversion. Only 6-bit integer conversion at 55 dB SPL resulted in a significant degradation in speech intelligibility. For the floating-point data, there were no significant differences in s

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20

Widyaningsih, Ratna, Kharisma Idea, Ayu Utami, et al. "EVALUATING CUTTING TRANSPORT ON 12 ¼” SECTION WELL TM-1." Journal of Petroleum and Geothermal Technology 5, no. 1 (2024): 7. http://dx.doi.org/10.31315/jpgt.v5i1.10742.

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Mud hydraulics on a 12-1/4" section needs to be planned properly. Mud hydraulics design on a 12-1/4" section includes determining mud density, flow type, pressure loss, pump specifications, bit hydraulics and cutting lifting design. The purpose of bit hydraulics design is to determine the optimum flow rate. Mud hydraulics optimization is carried out using methods the Bit Hydraulic Horse Power (BHHP), Bit Hydraulic Impact (BHI) and Jet Velocity (JV) methods, where the analysis is in the form of graphs. The graph is analyzed by using a trial and error method to obtain the recommended flow rate s

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21

Smith, H. J., S. J. Bakke, B. Smevik, et al. "Comparison of 12-Bit and 8-Bit Gray Scale Resolution in Mr Imaging of the CNS." Acta Radiologica 33, no. 6 (1992): 505–11. http://dx.doi.org/10.1177/028418519203300601.

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A reduction in gray scale resolution of digital images from 12 to 8 bits per pixel usually means halving the storage space needed for the images. Theoretically, important diagnostic information may be lost in the process. We compared the sensitivity and specificity achieved by 4 radiologists in reading laser-printed films of original 12-bit MR images and cathode ray tube displays of the same images which had been compressed to 8 bits per pixel using a specially developed computer program. Receiver operating characteristic (ROC) curves showed no significant differences between film reading and

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22

Oh, Sung Kwang, Kwang Sub Yoon, and Jonghwan Lee. "A Reconfigurable Hybrid ADC Using a Jump Search Algorithm." Electronics 13, no. 3 (2024): 606. http://dx.doi.org/10.3390/electronics13030606.

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This paper presents a reconfigurable hybrid Analog to Digital Converter (ADC) designed specifically for bio-signal processing, aiming to achieve low power consumption and high area efficiency. The proposed ADC utilizes a combination of 10-bit Most Significant Bit (MSB) Successive Approximation Register (SAR) and 2–4-bit Least Significant Bit (LSB) Single Slope (SS) architectures. The SS architecture incorporates the Dummy Capacitor Quantization Method (DCQM) which employs a 10-bit MSB dummy capacitor. This dummy capacitor can be configured to represent the 2-LSBs or reconstruct 4-LSBs. The rec

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23

Suthaskumar, Muneswaran. "A 12-bit Hybrid DAC with Swing Reduced Driver." IOSR Journal of VLSI and Signal Processing 3, no. 2 (2013): 35–39. http://dx.doi.org/10.9790/4200-0323539.

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24

Chou, Fang-Ting, and Chung-Chih Hung. "A compact 12-bit DAC with novel bias scheme." IEICE Electronics Express 11, no. 17 (2014): 20140572. http://dx.doi.org/10.1587/elex.11.20140572.

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25

Wu, Xue, Wu Lu, and Qi Guo. "TID Effects on 12-Bit Digital-to-Analog Converter." Advanced Materials Research 677 (March 2013): 326–33. http://dx.doi.org/10.4028/www.scientific.net/amr.677.326.

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This Paper describes ionizing irradiation effects and annealing behavior on some commercial available CMOS high speed and high resolution Digital-to-Analog Converter —AD9742. AC and DC parameters are measured before and after radiation and annealing experiment. Results show that DC parameters are more sensitive than AC parameters, and all parameters are fully recovered after room-temperature and elevated-temperature annealing behaviors. Test facilities, results and analysis are presented in this paper in details.

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26

Belcher, R. "A 12 bit 125 MHz ADC using direct interpolation." Measurement 28, no. 2 (2000): 77–83. http://dx.doi.org/10.1016/s0263-2241(99)00047-0.

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27

Kerth, D. A., N. S. Sooch, and E. J. Swanson. "A 12-bit, 1-MHz, two-step flash ADC." IEEE Journal of Solid-State Circuits 24, no. 2 (1989): 250–55. http://dx.doi.org/10.1109/4.18583.

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28

Bastos, J., A. M. Marques, M. S. J. Steyaert, and W. Sansen. "A 12-bit intrinsic accuracy high-speed CMOS DAC." IEEE Journal of Solid-State Circuits 33, no. 12 (1998): 1959–69. http://dx.doi.org/10.1109/4.735536.

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29

Frater, Michael R., and John F. Arnold. "Coding of 12-bit video from thermal imaging systems." Signal Processing: Image Communication 15, no. 10 (2000): 907–16. http://dx.doi.org/10.1016/s0923-5965(99)00038-7.

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30

Tan, BTG, and LP Tay. "12-bit digital audio time delay using the 6809." Microprocessors and Microsystems 10, no. 9 (1986): 500–505. http://dx.doi.org/10.1016/0141-9331(86)90179-1.

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31

Qiu, Peng, Yong Zhao, Jie Zheng, Jian-Feng Wang, and Xiao-Jun Jiang. "Research on performances of back-illuminated scientific CMOS for astronomical observations." Research in Astronomy and Astrophysics 21, no. 10 (2021): 268. http://dx.doi.org/10.1088/1674-4527/21/10/268.

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Abstract To evaluate performances of a back-illuminated scientific CMOS (sCMOS) camera for astronomical observations, comparison tests between Andor Marana sCMOS and Andor iKon-L 936 CCD cameras were conducted in a laboratory and on a telescope. The laboratory tests showed that the readout noise of the sCMOS camera is about half lower, the dark current is about 17 times higher, the dynamic range is lower in the 12-bit setting and higher in the 16-bit setting, and the linearity and bias stability are comparable relative to those of the CCD camera. In field tests, we observed the open cluster M6

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32

Smith, H. J., S. J. Bakke, B. Smevik, et al. "Comparison of 12-Bit and 8-Bit Gray Scale Resolution in MR Imaging of the CNS." Acta Radiologica 33, no. 6 (1992): 505–11. http://dx.doi.org/10.3109/02841859209173201.

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33

Smith, H. J., S. J. Bakke, B. Smevik, et al. "Comparison of 12-Bit and 8-Bit Gray Scale Resolution in MR Imaging of the CNS." Acta Radiologica 33, no. 6 (1992): 505–11. http://dx.doi.org/10.1080/02841859209173201.

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34

Vandenberg, JD, and Stefano Andriani. "A Review of 3D-LUT Performance in 10-bit and 12-bit HDR BT.2100 PQ." SMPTE Motion Imaging Journal 129, no. 2 (2020): 59–70. http://dx.doi.org/10.5594/jmi.2020.2965022.

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35

Lee, Ho-Yong, Min-Soo Shim, Jongwhan Lee, Byung Seong Bae, and Kwang Sub Yoon. "A CMOS two-way time interleaved 12-bit SAR ADC with 6-bit MSBs sharing technique." Analog Integrated Circuits and Signal Processing 103, no. 2 (2020): 337–43. http://dx.doi.org/10.1007/s10470-020-01655-4.

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36

Halazonetis, Demetrios J. "What do 8-bit and 12-bit grayscale mean and which should I use when scanning?" American Journal of Orthodontics and Dentofacial Orthopedics 127, no. 3 (2005): 387–88. http://dx.doi.org/10.1016/j.ajodo.2004.07.025.

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37

Ese, Zehra, and Waldemar Zylka. "Influence of 12-bit and 16-bit CT values of metals on dose calculation in radiotherapy using PRIMO, a Monte Carlo code for clinical linear accelerators." Current Directions in Biomedical Engineering 5, no. 1 (2019): 597–600. http://dx.doi.org/10.1515/cdbme-2019-0150.

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AbstractIn this paper, the effect of computed tomography (CT) values of metals in 12-bit and 16-bit extended Hounsfield Unit (EHU) scale on dose calculations in radiotherapy treatment planning systems (TPS) were quantified. Dose simulations for metals in water environment were performed with the software PRIMO in 6MV photon mode. The depth dose profiles were analysed and the relative dose differences between the metals determined with 12-bit and 16-bit CT imaging, respectively, were calculated. Maximum dose differences of ΔAl = 3.0%, ΔTi = 4.5%, ΔCr = 6.2% and ΔCu = 11.6% were measured. In ord

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38

Han, Jiaqi, Long Li, Guangyao Liu, Zhao Wu, and Yan Shi. "A Wideband 1 bit 12 × 12 Reconfigurable Beam-Scanning Reflectarray: Design, Fabrication, and Measurement." IEEE Antennas and Wireless Propagation Letters 18, no. 6 (2019): 1268–72. http://dx.doi.org/10.1109/lawp.2019.2914399.

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39

Moon, Cheol Woo, Kwang Sub Yoon, and Jonghwan Lee. "A 12~14-Bit SAR-SS Hybrid ADC with SS Bit Shifting Resolution Reconfigurable Method for Bio-Signal Processing." Electronics 12, no. 24 (2023): 4916. http://dx.doi.org/10.3390/electronics12244916.

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This paper presents a low-power, high-resolution reconfigurable hybrid ADC for bio-electrical signal processing. The proposed ADC contains a SAR ADC for the most significant bit (MSB) and a single-slope ADC for the least significant bit (LSB). To solve the issue of exponentially increasing sampling speed based on the resolution of the single-slope ADC, the SAR ADC is designed to be reconfigurable with a resolution of 8–10-bit, while the single-slope ADC is configured with a resolution of 4-bit. To achieve this resolution reconfiguration, the bit shifting method is proposed and implemented with

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40

Rikan, Behnam, Sang-Yun Kim, Hamed Abbasizadeh, et al. "A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System." Energies 11, no. 10 (2018): 2673. http://dx.doi.org/10.3390/en11102673.

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This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module, a hybrid-type structure with capacitor and resistor DACs is applied, in which the resistor DAC is shared between channels and determines the seven least significant bits (LSB)s, while the capacitor DAC determines the three most significant bits (MS

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41

Tang, Junlong, Yaodong Wang, Hongbo Gu, and Wanghui Zou. "Design of Self-Calibration Comparator for 12-Bit SAR ADCs." Electronics 12, no. 10 (2023): 2277. http://dx.doi.org/10.3390/electronics12102277.

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A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output offset storage (IOS/OOS) and an offset trimming circuit was employed to reduce the offset of the cascade preamplifier and the operational transconductance amplifier (OTA), a novel offset trimming circuit with a 5-bit digital controller was designed to further reduce the residual offset

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42

Lim, Xian Yang, Boon Chiat Terence Teo, Venkadasamy Navaneethan, Wu Cong Lim, and Liter Siek. "Design and Analysis of a Novel 12-Bit Current-Steering–Capacitive Digital-to-Analog Converter." Journal of Low Power Electronics and Applications 15, no. 1 (2025): 9. https://doi.org/10.3390/jlpea15010009.

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This article introduces a novel digital-to-analog converter (DAC), which addresses a few weaknesses that a traditional capacitive DAC (CDAC) has, such as matching and parasitic capacitance-induced code dependency and a challenging bridge capacitor design. Our novel idea is a hybrid DAC of a CDAC and a current-steering DAC (CSDAC) and is named the CSCDAC. In this paper, a 12-bit CSCDAC is designed, and the post-layout simulation is provided. The Nyquist 12-bit CSCDAC exhibits a spurious free dynamic range (SFDR) of 67.62 dB under an operating frequency of 2 GS/s, with an expected average power

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43

Sharma, Vijay Pratap, and Hemant Patidar. "ANALYSIS AND IMPLEMENTATION OF MAC UNIT FOR DIFFERENT PRECISIONS." ICTACT Journal on Microelectronics 7, no. 4 (2022): 1260–64. https://doi.org/10.21917/ijme.2022.0217.

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This paper describes the design of the multiply- Accumulate unit and compares all parameters of the 4-bit, 8-bit, 12-bit, and 16-bit MAC unit. MAC is the basic unit that performs the multiplication operation and addition/accumulation operation. This MAC unit is designed on Vivado HLS software using LUTs at room temperature. These designs are analyzed and simulated by using the Vivado HLS tool and implemented on Zybo Evaluation and Development kit (xc7z020clg400-1).

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44

Malik, Seema, and Sunil Nandal. "Design of 12 bit Successive Approximation Analog-to-Digital Converter." International Journal of Computer Applications 74, no. 6 (2013): 1–6. http://dx.doi.org/10.5120/12886-9627.

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45

Fan, Xiang Ning, Hao Zheng, Yu Tao Sun, and Xiang Yan. "Design and Implementation of a 12-Bit 100MS/s ADC." Applied Mechanics and Materials 229-231 (November 2012): 1507–10. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1507.

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In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to fur

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46

Adimulam, Mahesh Kumar, and M. B. Srinivas. "A 12-bit, 1.1-GS/s, Low-Power Flash ADC." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30, no. 3 (2022): 277–90. http://dx.doi.org/10.1109/tvlsi.2021.3138538.

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47

Zhihe Zhou and G. S. La Rue. "A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 9 (2008): 2459–68. http://dx.doi.org/10.1109/tcsi.2008.920981.

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48

Hotta, M., T. Shimizu, K. Maio, K. Nakazato, and S. Ueda. "A 12-mW 6-bit video-frequency A/D converter." IEEE Journal of Solid-State Circuits 22, no. 6 (1987): 939–43. http://dx.doi.org/10.1109/jssc.1987.1052841.

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Rho, Sung-Chan, and Shin-Il Lim. "A 12-bit 100kS/s SAR ADC for Biomedical Application." International Journal of u- and e- Service, Science and Technology 9, no. 8 (2016): 17–22. http://dx.doi.org/10.14257/ijunesst.2016.9.8.02.

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Fu, Yikun, Haisong Li, and Yihu Jiang. "A high precision comparator design for 12-bit SAR ADC." Journal of Physics: Conference Series 2849, no. 1 (2024): 012006. http://dx.doi.org/10.1088/1742-6596/2849/1/012006.

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Abstract:

Abstract A comparator circuit applied to a 12-bit successive approximation analog-to-digital converter (SAR ADC) is proposed in this paper. The circuit is designed based on 0.18 μm CMOS technology, consisting of an open-loop comparator, a regenerative comparator, and buffer circuits. The open-loop comparator adopts a differential input structure and incorporates cross-coupled pairs to enhance gain, introducing reset and clamping techniques to improve speed. The regenerative comparator employs a positive feedback structure to enhance response speed. Additionally, a novel biasing circuit using e

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