Relevant bibliographies by topics / 180 nm CMOS

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic '180 nm CMOS'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "180 nm CMOS"

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Bin Wan Jusoh, Wan Mohammad Ehsan Aiman, Siti Hawa Ruslan, Nabihah Ahmad, Warsuzarina Mat Jubadi, and Rahmat Sanudin. "Comparative study of symmetrical OTA performance in 180 nm, 130 nm and 90 nm CMOS technology." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 1 (April 1, 2019): 230. http://dx.doi.org/10.11591/ijeecs.v14.i1.pp230-240.

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<span>In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) performance between 180 nm, 130 nm and 90 nm CMOS technology have been done thoroughly to find the relationship between voltage supply and bias current with performance parameters (gain, power consumption and Common-Mode Rejection Ratio (CMRR)). The OTA which adopts symmetrical topology is designed carefully and simulated using Synopsys HSpice software and the results are carefully analyzed and compared. The symmetrical OTA designed in 90 nm CMOS technology is found to be the best because the power consumed is only 9.83 µW from ±0.9 V voltage supply and the OTA achieved 55.9 dB of the DC gain. The CMRR of the symmetrical 90 nm OTA is 140 dB which is sufficient to reject the common-mode signals in electrocardiogram (ECG) input signal. The symmetrical 90 nm OTA is suitable to be implemented as bioamplifier in ECG signal detection system as it consumed low power and has a high CMRR characteristic.</span>
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Huang, R. G., D. Gnani, C. Grace, Yu G. Kolomensky, Y. Mei, and A. Papadopoulou. "Cryogenic characterization of 180 nm CMOS technology at 100 mK." Journal of Instrumentation 15, no. 06 (June 23, 2020): P06026. http://dx.doi.org/10.1088/1748-0221/15/06/p06026.

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O, K. K., S. SANKARAN, C. CAO, E. Y. SEOK, D. SHIM, C. MAO, and R. HAN. "MILLIMETER WAVE TO TERAHERTZ IN CMOS." International Journal of High Speed Electronics and Systems 19, no. 01 (March 2009): 55–67. http://dx.doi.org/10.1142/s0129156409006084.

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The feasibility of CMOS circuits operating at frequencies in the upper millimeter wave and low sub-millimeter frequency regions has been demonstrated. A 140-GHz fundamental mode VCO in 90-nm CMOS, a 410-GHz push-push VCO in 45-nm CMOS, and a 180-GHz detector circuit in 130-nm CMOS have been demonstrated. With the continued scaling of MOS transistors, 1-THz CMOS circuits will be possible. Though these results are significant, output power of signal generators must be increased and acceptable noise performance of detectors must be achieved in order to demonstrate the applicability of CMOS for implementing practical terahertz systems.
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Caglar, Alican, and Mustafa Berke Yelten. "A 180-nm X-Band Cryogenic CMOS LNA." IEEE Microwave and Wireless Components Letters 30, no. 4 (April 2020): 395–98. http://dx.doi.org/10.1109/lmwc.2020.2979341.

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Hao, Han, Lin Du, Andrew G. Richardson, Timothy H. Lucas, Mark G. Allen, Jan Van der Spiegel, and Firooz Aflatouni. "A Wireless Artificial Mechanoreceptor in 180-nm CMOS." IEEE Transactions on Microwave Theory and Techniques 69, no. 6 (June 2021): 2907–20. http://dx.doi.org/10.1109/tmtt.2021.3072398.

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ti, Dip, Rajesh Mehra, and Deep Sehgal. "Efficient Pixel Architecture of CMOS Image Sensor using CMOS 180 nm technology." International Journal of Engineering Trends and Technology 37, no. 3 (July 25, 2016): 161–64. http://dx.doi.org/10.14445/22315381/ijett-v37p226.

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Wang, Albert, and Alyosha Molnar. "A Light-Field Image Sensor in 180 nm CMOS." IEEE Journal of Solid-State Circuits 47, no. 1 (January 2012): 257–71. http://dx.doi.org/10.1109/jssc.2011.2164669.

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Meng, Xu, and Fujiang Lin. "Clock generator IP design in 180 nm CMOS technology." Analog Integrated Circuits and Signal Processing 87, no. 3 (April 11, 2016): 369–77. http://dx.doi.org/10.1007/s10470-016-0737-x.

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Wakita, Kosuke, Eiichi Sano, Masayuki Ikebe, Stevanus Arnold, Taiichi Otsuji, Yuma Takida, and Hiroaki Minamide. "Design and Fabrication of Terahertz Detectors Based on 180-nm CMOS Process Technology." International Journal of High Speed Electronics and Systems 25, no. 03n04 (September 2016): 1640014. http://dx.doi.org/10.1142/s0129156416400140.

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A CMOS cascode amplifier, biased near the threshold voltage of a MOSFET, for terahertz direct detection is proposed. A CMOS terahertz imaging circuit (size: 250 × 180 ìm) is designed and fabricated on the basis of low-cost 180-nm CMOS process technology. The imaging circuit consists of a microstrip patch antenna, an impedance-matching circuit, and a direct detector. It achieves a responsivity of 51.9 kV/W at 0.915 THz and a noise equivalent power (NEP) of 358 pW/Hz1/2 at a modulation frequency of 31 Hz. NEP is estimated to be reduced to 42 pW/Hz1/2 at 100 kHz. These results suggest that cost-efficient terahertz imaging is possible in the near future.
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Mata-Hernandez, Diana, Daniel Fernández, Saoni Banerji, and Jordi Madrenas. "Resonant MEMS Pressure Sensor in 180 nm CMOS Technology Obtained by BEOL Isotropic Etching." Sensors 20, no. 21 (October 23, 2020): 6037. http://dx.doi.org/10.3390/s20216037.

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This work presents the design and characterization of a resonant CMOS-MEMS pressure sensor manufactured in a standard 180 nm CMOS industry-compatible technology. The device consists of aluminum square plates attached together by means of tungsten vias integrated into the back end of line (BEOL) of the CMOS process. Three prototypes were designed and the structural characteristics were varied, particularly mass and thickness, which are directly related to the resonance frequency, quality factor, and pressure; while the same geometry at the frontal level, as well as the air gap, were maintained to allow structural comparative analysis of the structures. The devices were released through an isotropic wet etching step performed in-house after the CMOS die manufacturing, and characterized in terms of Q-factor vs. pressure, resonant frequency, and drift vs. temperature and biasing voltage.
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Dissertations / Theses on the topic "180 nm CMOS"

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Shah, Julin Mukeshkumar. "Compressive Sensing Analog Front End Design in 180 nm CMOS Technology." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440381988.

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Lacerda, Fábio de, and Instituto de Engenharia Nuclear. "Conversor DSB-SSB a capacitores chaveados por Transformador de Hilbert em tecnologia CMOS de 180 nm/." Instituto de Engenharia Nuclear, 2017. http://carpedien.ien.gov.br:8080/handle/ien/1907.

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Este trabalho trata da realização de um circuito integrado analógico para a conversão de sinais com modulação em amplitude de banda dupla (Double Sideband ou DSB) para modulação de banda simples (Single Sideband ou SSB). Implementado por circuitos de tempo discreto a capacitores chaveados, utiliza-se de um filtro com resposta infinita ao impulso (Infinite Input Response ou IIR) para compor um transformador de Hilbert como alternativa a implementações digitais, que se aproveitam da grande capacidade de processamento paralelo dos circuitos digitais para a obtenção do transformador de Hilbert por meio de filtros com resposta finita ao impulso (Finite Impulse Response ou FIR) de ordem elevada. Fabricado em tecnologia CMOS de 180 nm com capacitores do tipo metal-metal (MiM), a adoção de filtros estruturalmente passa-tudo reduz significativamente a sensibilidade do conversor ao descasamento de capacitores. Para alimentação de 1,8 V e sinais diferenciais de até 1 V, resultados experimentais mostram que o conversor atinge taxa de rejeição de imagem (Image Rejection Ratio ou IRR) maior que 39,5 dB para modulação Lower Sideband (LSB) e 38,0 dB para modulação Upper Sideband (USB) para sinais de entrada na faixa de 25% a 75% da frequência da portadora, valores estes superiores a propostas analógicas anteriores e comparáveis a propostas digitais do estado da arte em circuitos integrados. Com área de silício de 1,09 mm2, o conversor consome apenas 17,7 mW para frequência de amostragem de 1 MHz enquanto sua IRR apresentou desvio padrão de apenas 0,5 dB dentre 20 amostras avaliadas.
The realization of an analog integrated circuit for conversion of Double-Sideband (DSB) amplitude-modulated signals into Single-Sideband (SSB) is presented. Implemented by discrete-time switched-capacitor circuits, it adopts an Infinite Impulse Response (IIR) filter to realize a Hilbert transformer as alternative to digital implementations which take advantage of high processing capacity from parallel digital circuits to obtain the Hilbert transformer by means of high-order Finite Impulse Response (FIR) filters. Fabricated in a 180 nm CMOS technology with metal-metal (MiM) capacitors, the use of structurally all-pass filters greatly reduces the converter’s sensitivity to capacitor mismatch. For 1.8 V power supply and 1 V differential input/output signals, experimental results show the converter achieves Image Rejection Ratio (IRR) greater than 39.5 dB for Lower-Sideband (LSB) modulation and 38.0 dB for Upper-Sideband (USB) modulation for input signals ranging from 25% to 75% of the carrier frequency. These figures are higher than previous analog circuit proposals and comparable to digital implementations of state-of-the-art integrated circuits. Its silicon area is 1.09 mm2 and the converter consumes only 17.7 mW for 1 MHz sampling frequency while its IRR presents standard deviation of only 0.5 dB among 20 chip samples.
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Puech, Gabriel. "Conception d'un ADC de résolution 8 bits basse consommation et 2 GHz de fréquence d'échantillonnage en technologie CMOS 180 nm." Thesis, Université Clermont Auvergne‎ (2017-2020), 2017. http://www.theses.fr/2017CLFAC094/document.

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Après un rappel du contexte dans lequel ce travail de recherche a été conduit, le 1er chapitre présente les caractéristiques communes aux convertisseurs analogiques numériques (ADC) avec leurs figures de mérites. Un état de l’art exhaustif sur les ADC réalisés et plus particulièrement avec le nœud technologique CMOS 1 180 nm y est présenté. Ce travail préliminaire permet de donner un aperçu du défi relevé. Les architectures multi-étapes à échantillonnage analogique ont été éliminées de l’étude du fait des limitations de la technologie pour les contraintes de performances de l’ADC. Le chapitre 2 présente plus en détail les différentes implémentations possibles d’une famille d’ADC à échantillonnage numérique, les flash. Le portage de l’architecture TIQ est détaillé dans ce chapitre. Le chapitre 3 détaille l’étude et le portage en CMOS 180 nm des ADC à échantillonnage numérique à repliement de signal. Cette première partie conclut par le choix de l’architecture flash. La conception des briques de bases de l’ADC flash est détaillée dans les chapitres constituant la partie II du document. Le chapitre 4 est dédié à l’étude et au portage en CMOS 180 nm des étages de comparateurs latchés responsables de l’échantillonnage à 2 GHz de l’ADC flash. La non linéarité ramenée en entrée de l’architecture retenue ayant défini les contraintes sur l’étage de pré-amplification, celui ci est présenté dans le chapitre 5. Le chapitre 5, présente les différentes charges actives étudiées pour l’étage de pré-amplification. Le passage en différentiel passif avec le comparateur full différentiel et l’architecture retenue y sont détaillés. La technique du QV et son portage sur l’architecture de préamplificateur retenu sont présentés. Le décodeur thermométrique 2 binaire est présenté dans le chapitre 6. Deux implémentations de cette logique de décodage sont étudiées et portées. L’une est réalisée à partir d’un code de description matériel (VHDL) et la synthèse de cellules numériques en logique CMOS pull-up pull-down 3 . L’autre est réalisé à partir de multiplexeurs 1 bit et des flip flop à verrou en logique Pass gates complémentaire. Le chapitre 7 présente les limitations et l’implémentation de l’interpolation avec l’emploi des pré-amplificateurs et du comparateur latché retenus. L’étude de l’insertion de paires de suiveurs en drain commun, nécessaire à la polarisation des étages de pré-amplification y est présentée. Enfin, les analyses de tirage de Monte Carlo en mismatch 4 des résistances comme échelle de références sont comparées pour différents dimensionnements et topologies. Le synoptique global de l’ADC est présenté avec les cellules et techniques retenues. L’approche bottom-up incontournable pour la conception de circuits analogiques ou full custom présentée dans cette deuxième partie conclut sur le choix de concevoir un ASIC de preuve de concept. Ce dernier contient ainsi les briques de bases ayant une valeur ajoutée et potentiellement critiques pour la conversion de signaux. L’approche Top-down pour la conception est ainsi détaillée dans la 3e partie en partant du synoptique global de l’ASIC de preuve de concept envoyé en fonderie de circuit multi projet BuBlC1. contenant les cellules critiques à tester. La conception front-end de l’ASIC BuBlC1 avec notamment l’arbre d’horloge et les pads d’entrées sorties est présentée dans le chapitre 8. La phase de back-end avec les layouts des cellules retenues dans la partie II ainsi que leur intégration dans des ensembles (clusters) est présentée dans le chapitre 9 avec le padring et l’intégration finale des macro-ensembles (Cores analogiques et numériques)
After a a brief recall of the context this research work have been carried, the 1st chapter present the common analog to digital converters (ADC) characteristics with their figures of merit (FoM). A relevant state of the art on realized ADC architectures is presented. A particular emphasis has been done on 180 nm CMOS process node. This preliminary work gives a pertinent overview of the faced challenge. Multi step analog sampling architectures have been avoided from the study because of the transistors limited frequency performances. Chapter 2 presents the different implementations of the Flash digital sampling ADC family architecture. The TIQ architecture embedding in the 180 nm CMOS process are detailed in this chapter. Chapter 3 details the study and the design of an other digital sampling ADC family architecture on 180 nm CMOS process i.e. the signal folding architecture. This 1st part of the document conclude with the choice of the Flash ADC architecture. The building bloc design for this ADC are detailed in the following chapters constituting the part II. Chapter 4 is dedicated to the study and the design on 180 nm CMOS process of the latch comparator responsible of the 2 GHz sampling constraint of the overall ADC. As the retained comparator architecture input refereed non linearity defined the gain constraints of the preamplifier stage, the preamplifier is presented in the next chapter. Chapter 5 present the different characteristics and techniques of the quantifier stage. The comparator preamplifier stage with its different actives loads, its passive full differential transposition and the retained architecture are detailed. The QV technique and its embedding in the retained preamplifier architecture are presented. The thermometric 1 to binary encoder tree is presented in chapter 6. Two implementations of this encoding are studied and design on the Front-End (FE) level. The 1st one is a pipelined Wallace tree realized with a register transfer level (RTL) code on VHDL hardware description language. The synthesis flow on CMOS pull-up pull-down 2 combinatorial logic and rising edge flip flops are used for this architecture. The other architecture is designed using 1 bits multiplexers combinatorial pipelined with pass gated D latches with a full custom schematic implementation. Chapter 7 presents the limitations and the embedding of the interpolation with the retained preamplifier and comparator latch. The study of common drain source follower (CDSF) pairs insertion, mandatory for the biasing of the preamplifier input stage to reach the 8 bits resolution is studied with details. Finally, Monte Carlo sampling mismatch 3 analysis on the resistor references are studied by comparing different topologies and sizing. The overall ADC synoptic is presented with the retained cells and techniques. The bottom-up design approach, mandatory for analog and full-custom design, exposed in this 2nd part conclude on the choice to design a proof of concept ASIC (BuBlC1) including all the critical piece of circuits of the overall ADC with added value and potentially critical for signal conversion. The top-down approach for this ASIC design is detailed in the IIIrd part with the overall ASIC synoptic of the BuBlC1 ASIC sent to multi project wafer (MPW) foundry run integrating all the critical cells.The FE design of this ASIC with its clock tree and its input/output PAD are presented in chapter 8. The Back-End design with the retained cells layout in part II with the cells integration in clusters are presented in chapter 9 with the pad-ring and final integration in digital and analog macro-cells cores
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Truyen, David. "Etude par simulation composant 3D des effets singuliers SEU et SET induits par ions lourds sur le noeud technologique CMOS bulk 180 nm." Montpellier 2, 2007. http://www.theses.fr/2007MON20139.

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Johansson, Jimmy. "Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-138446.

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Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.
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Arnim, Klaus von [Verfasser]. "Digitale Schaltungstechniken für Sub-100-nm-CMOS-Technologien / Klaus von Arnim." Kiel : Universitätsbibliothek Kiel, 2009. http://d-nb.info/1019813423/34.

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Mehdi, Ghulam. "Highly Linear Mixer for On-chip RF Test in 130 nm CMOS." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8001.

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The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as much advanced test equipments and instruments are needed to carry out the sophisticated performance tests. To avoid this higher cost and to reduce the test time, the alternative is to perform on-chip test. .In RF transceivers, loopback is an on-chip test technique in which Tx signal, instead of radiating through antenna is fed to the Rx chain through a test attenuator (TA) during the test mode. A highly linear offset mixer is needed to implement this on-chip loopback test for these transceivers. The aim of this thesis work is to design a highly linear upconversion offset mixer for loopback test in CMOS technology. This mixer is designed for Bluetooth and GSM/EDGE standards.

Few highly linear mixer architectures were simulated in 0.35um AMS process using Cadence SpectreRF software. When compared with active mixers, passive mixer consumes no dc power and there is significant reduction in silicon area overhead. The thesis presents a highly linear passive mixer with very low conversion loss and noise figure. The mixer is designed in 0.13um AMS CMOS process for higher cut off frequency and improved conversion loss. Pre and Post layout simulation results of the designed mixer are presented.

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Arora, Rajan. "Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50140.

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The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.
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Strzelecki, Joseph Benito. "Wideband Automatic Gain Control Design in 130 nm CMOS Process for Wireless Receiver Applications." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440773805.

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Pavageau, Christophe. "Utilisation des technologies CMOS SOI 130 nm pour des applications en gamme de fréquences millimétriques." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2005. http://tel.archives-ouvertes.fr/tel-00011744.

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La technologie CMOS SOI (« Silicon On Insulator ») a déjà montré son intérêt pour les circuits numériques par rapport à la technologie CMOS sur substrat massif (« bulk »). Avec l'entrée des technologies CMOS dans l'ère des dimensions nanométriques, les transistors atteignent des fréquences de coupures élevées, ouvrant la voie aux applications hyperfréquences et de ce fait à l'intégration sur la même puce des circuits numériques, analogiques et hyperfréquences. Cependant, la piètre qualité des éléments passifs reste le principal verrou des technologies CMOS pour y parvenir.
Les travaux effectués lors de cette thèse portaient sur l'étude des aptitudes de la technologie CMOS SOI 130 nm de ST-Microelectronics pour des applications hyperfréquences au-delà de 20 GHz. Ils consistaient plus précisément à concevoir des circuits de démonstration pouvant entrer dans la composition d'une chaîne d'émission/réception. Trois amplificateurs distribués en bande K ont d'abord été conçus et mesurés. Malgré des pertes élevées dans les lignes de transmission limitant ainsi la bande passante et le gain, les performances mesurées montrent l'intérêt de cette technologie pour les hyperfréquences. Ensuite, une nouvelle série de démonstrateurs – amplificateurs distribués, amplificateurs faible bruit et mélangeurs actifs – a été conçue en employant des lignes à plus faibles pertes que celles utilisées précédemment. Les résultats de simulation montrent que le produit gain-bande des amplificateurs distribués a doublé en conservant la même architecture. Les simulations des amplificateurs faible bruit et des mélangeurs actifs montrent des performances à l'état de l'art en CMOS.
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Book chapters on the topic "180 nm CMOS"

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Parvathy, P., and N. Saraswathi. "Design and Analysis of a CMOS 180-nm Fractional-N Frequency Synthesizer." In Nanoelectronic Materials and Devices, 37–49. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7191-1_5.

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Krishna Reddy, K., and P. Sreehari Rao. "A High Efficiency Six Phase Voltage Doubler Cell Using 180 nm CMOS Process." In Communications in Computer and Information Science, 29–36. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7219-7_3.

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Simariya, Dipika, R. C. Gurjar, and D. K. Mishra. "Pulse Start-up Technique Based Class C VCO Using 180 nm CMOS Technology." In Lecture Notes in Electrical Engineering, 755–65. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-0275-7_62.

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Juhi Faridi, Mohd Samar Ansari, and Syed Atiqur Rahman. "A Neuromorphic Majority Function Circuit with O(n) Area Complexity in 180 nm CMOS." In Proceedings of the International Conference on Data Engineering and Communication Technology, 473–80. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1675-2_47.

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Soman, Vanitha, and Sudhakar S. Mande. "Design of a Two-Stage Folded Cascode Amplifier Using SCL 180 nm CMOS Technology." In Lecture Notes in Electrical Engineering, 423–30. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-2612-1_41.

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Siddamal, Saroja V., Suhas B. Shirol, Shraddha B. Hiremath, Jayashree Mallidu, and Nalini C. Iyer. "Design and Implementation of ASIC for Time Recorder in TSMC 180 nm CMOS Technology." In Communications in Computer and Information Science, 281–87. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_22.

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Dipu, P., B. Saidulu, K. Aravind, Johny S. Raj, and K. Sivasankaran. "A 4-bit 9 KS/s Distortionless Successive Approximation ADC in 180-nm CMOS Technology." In Advances in Intelligent Systems and Computing, 55–63. New Delhi: Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-2126-5_7.

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Shraddha, B. H., and Nalini C. Iyer. "An Active Mixer Design For Down Conversion in 180 nm CMOS Technology for RFIC Applications." In Emerging Research in Computing, Information, Communication and Applications, 605–19. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5953-8_50.

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Saldanha, Alan, Vijil Gupta, and Vinod Kumar Joshi. "Comparison of Low Current Mismatch CMOS Charge Pumps for Analog PLLs Using 180 nm Technology." In Advances in Intelligent Systems and Computing, 683–92. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3600-3_65.

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Rahali, Ahmed, Karim El Khadiri, Zakia Lakhliai, Hassan Qjidaa, and Ahmed Tahiri. "Design of a CMOS Bandgap Reference Voltage Using the OP AMP in 180 nm Process." In Digital Technologies and Applications, 1655–62. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-73882-2_150.

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Conference papers on the topic "180 nm CMOS"

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Raut, Ketan J., R. V. Kshirsagar, and A. C. Bhagali. "A 180 nm low power CMOS operational amplifier." In 2014 Innovative Applications of Computational Intelligence on Power, Energy and Controls with their impact on Humanity (CIPECH). IEEE, 2014. http://dx.doi.org/10.1109/cipech.2014.7019049.

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Arnold, William H. "Lithography strategies for 180-nm CMOS device fabrication." In Photomask Japan '97, edited by Naoaki Aizaki. SPIE, 1997. http://dx.doi.org/10.1117/12.277248.

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Udupa, Sharanya S., P. S. Sushma, and Chaithra. "ECG analog front-end in 180 nm CMOS technology." In 2017 International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT). IEEE, 2017. http://dx.doi.org/10.1109/icicict1.2017.8342583.

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Enomoto, Tadayoshi, Suguru Nagayama, and Nobuaki Kobayashi. "Low-Power High-Speed 180-nm CMOS Clock Drivers." In 2007 Asia and South Pacific Design Automation Conference. IEEE, 2007. http://dx.doi.org/10.1109/aspdac.2007.357973.

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Tadayoshi Enomoto and Yuki Higuchi. "A low-leakage current power 180-nm CMOS SRAM." In 2008 Asia and South Pacific Design Automation Conference (ASPDAC). IEEE, 2008. http://dx.doi.org/10.1109/aspdac.2008.4483914.

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Suna, Ahmet, Ismail Cevik, and Mustafa Berke Yelten. "A High Speed 180 NM CMOS Cryogenic SAR ADC." In 2018 18th Mediterranean Microwave Symposium (MMS). IEEE, 2018. http://dx.doi.org/10.1109/mms.2018.8611968.

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Tomic, Dubravko, Josip Mikulic, Gregor Schatzberger, Johannes Fellner, and Adrijan Baric. "Programmable low-frequency divider in 180-nm CMOS technology." In 2020 43rd International Convention on Information, Communication and Electronic Technology (MIPRO). IEEE, 2020. http://dx.doi.org/10.23919/mipro48935.2020.9245285.

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Tolic, Ivan Porin, Josip Mikulic, Gregor Schatzberger, and Adrijan Baric. "Design of CMOS Temperature Sensors Based on Ring Oscillators in 180-nm and 110-nm technology." In 2020 43rd International Convention on Information, Communication and Electronic Technology (MIPRO). IEEE, 2020. http://dx.doi.org/10.23919/mipro48935.2020.9245244.

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Wang, Tianyang, Marlon Barbero, Pierre Barrillon, Ivan Berdalović, Christian Bespin, Siddharth Bhat, Patrick Breugnon, et al. "Depleted Monolithic Active Pixel Sensors in the LFoundry 150 nm and TowerJazz 180 nm CMOS Technologies." In The 28th International Workshop on Vertex Detectors. Trieste, Italy: Sissa Medialab, 2020. http://dx.doi.org/10.22323/1.373.0026.

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Jianhong Xiao, Weinan Gao, Xiaojing Xu, Dave Chang, Jiang Cao, Runhua Sun, Vijay Periasamy, et al. "A 180 mW multistandard TV tuner in 28 nm CMOS." In 2016 IEEE Symposium on VLSI Circuits. IEEE, 2016. http://dx.doi.org/10.1109/vlsic.2016.7573502.

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