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Shah, Julin Mukeshkumar. "Compressive Sensing Analog Front End Design in 180 nm CMOS Technology." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440381988.
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Lacerda, Fábio de, and Instituto de Engenharia Nuclear. "Conversor DSB-SSB a capacitores chaveados por Transformador de Hilbert em tecnologia CMOS de 180 nm/." Instituto de Engenharia Nuclear, 2017. http://carpedien.ien.gov.br:8080/handle/ien/1907.
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Este trabalho trata da realização de um circuito integrado analógico para a conversão de sinais com modulação em amplitude de banda dupla (Double Sideband ou DSB) para modulação de banda simples (Single Sideband ou SSB). Implementado por circuitos de tempo discreto a capacitores chaveados, utiliza-se de um filtro com resposta infinita ao impulso (Infinite Input Response ou IIR) para compor um transformador de Hilbert como alternativa a implementações digitais, que se aproveitam da grande capacidade de processamento paralelo dos circuitos digitais para a obtenção do transformador de Hilbert por meio de filtros com resposta finita ao impulso (Finite Impulse Response ou FIR) de ordem elevada. Fabricado em tecnologia CMOS de 180 nm com capacitores do tipo metal-metal (MiM), a adoção de filtros estruturalmente passa-tudo reduz significativamente a sensibilidade do conversor ao descasamento de capacitores. Para alimentação de 1,8 V e sinais diferenciais de até 1 V, resultados experimentais mostram que o conversor atinge taxa de rejeição de imagem (Image Rejection Ratio ou IRR) maior que 39,5 dB para modulação Lower Sideband (LSB) e 38,0 dB para modulação Upper Sideband (USB) para sinais de entrada na faixa de 25% a 75% da frequência da portadora, valores estes superiores a propostas analógicas anteriores e comparáveis a propostas digitais do estado da arte em circuitos integrados. Com área de silício de 1,09 mm2, o conversor consome apenas 17,7 mW para frequência de amostragem de 1 MHz enquanto sua IRR apresentou desvio padrão de apenas 0,5 dB dentre 20 amostras avaliadas.
The realization of an analog integrated circuit for conversion of Double-Sideband (DSB) amplitude-modulated signals into Single-Sideband (SSB) is presented. Implemented by discrete-time switched-capacitor circuits, it adopts an Infinite Impulse Response (IIR) filter to realize a Hilbert transformer as alternative to digital implementations which take advantage of high processing capacity from parallel digital circuits to obtain the Hilbert transformer by means of high-order Finite Impulse Response (FIR) filters. Fabricated in a 180 nm CMOS technology with metal-metal (MiM) capacitors, the use of structurally all-pass filters greatly reduces the converter’s sensitivity to capacitor mismatch. For 1.8 V power supply and 1 V differential input/output signals, experimental results show the converter achieves Image Rejection Ratio (IRR) greater than 39.5 dB for Lower-Sideband (LSB) modulation and 38.0 dB for Upper-Sideband (USB) modulation for input signals ranging from 25% to 75% of the carrier frequency. These figures are higher than previous analog circuit proposals and comparable to digital implementations of state-of-the-art integrated circuits. Its silicon area is 1.09 mm2 and the converter consumes only 17.7 mW for 1 MHz sampling frequency while its IRR presents standard deviation of only 0.5 dB among 20 chip samples.
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Puech, Gabriel. "Conception d'un ADC de résolution 8 bits basse consommation et 2 GHz de fréquence d'échantillonnage en technologie CMOS 180 nm." Thesis, Université Clermont Auvergne (2017-2020), 2017. http://www.theses.fr/2017CLFAC094/document.
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Après un rappel du contexte dans lequel ce travail de recherche a été conduit, le 1er chapitre présente les caractéristiques communes aux convertisseurs analogiques numériques (ADC) avec leurs figures de mérites. Un état de l’art exhaustif sur les ADC réalisés et plus particulièrement avec le nœud technologique CMOS 1 180 nm y est présenté. Ce travail préliminaire permet de donner un aperçu du défi relevé. Les architectures multi-étapes à échantillonnage analogique ont été éliminées de l’étude du fait des limitations de la technologie pour les contraintes de performances de l’ADC. Le chapitre 2 présente plus en détail les différentes implémentations possibles d’une famille d’ADC à échantillonnage numérique, les flash. Le portage de l’architecture TIQ est détaillé dans ce chapitre. Le chapitre 3 détaille l’étude et le portage en CMOS 180 nm des ADC à échantillonnage numérique à repliement de signal. Cette première partie conclut par le choix de l’architecture flash. La conception des briques de bases de l’ADC flash est détaillée dans les chapitres constituant la partie II du document. Le chapitre 4 est dédié à l’étude et au portage en CMOS 180 nm des étages de comparateurs latchés responsables de l’échantillonnage à 2 GHz de l’ADC flash. La non linéarité ramenée en entrée de l’architecture retenue ayant défini les contraintes sur l’étage de pré-amplification, celui ci est présenté dans le chapitre 5. Le chapitre 5, présente les différentes charges actives étudiées pour l’étage de pré-amplification. Le passage en différentiel passif avec le comparateur full différentiel et l’architecture retenue y sont détaillés. La technique du QV et son portage sur l’architecture de préamplificateur retenu sont présentés. Le décodeur thermométrique 2 binaire est présenté dans le chapitre 6. Deux implémentations de cette logique de décodage sont étudiées et portées. L’une est réalisée à partir d’un code de description matériel (VHDL) et la synthèse de cellules numériques en logique CMOS pull-up pull-down 3 . L’autre est réalisé à partir de multiplexeurs 1 bit et des flip flop à verrou en logique Pass gates complémentaire. Le chapitre 7 présente les limitations et l’implémentation de l’interpolation avec l’emploi des pré-amplificateurs et du comparateur latché retenus. L’étude de l’insertion de paires de suiveurs en drain commun, nécessaire à la polarisation des étages de pré-amplification y est présentée. Enfin, les analyses de tirage de Monte Carlo en mismatch 4 des résistances comme échelle de références sont comparées pour différents dimensionnements et topologies. Le synoptique global de l’ADC est présenté avec les cellules et techniques retenues. L’approche bottom-up incontournable pour la conception de circuits analogiques ou full custom présentée dans cette deuxième partie conclut sur le choix de concevoir un ASIC de preuve de concept. Ce dernier contient ainsi les briques de bases ayant une valeur ajoutée et potentiellement critiques pour la conversion de signaux. L’approche Top-down pour la conception est ainsi détaillée dans la 3e partie en partant du synoptique global de l’ASIC de preuve de concept envoyé en fonderie de circuit multi projet BuBlC1. contenant les cellules critiques à tester. La conception front-end de l’ASIC BuBlC1 avec notamment l’arbre d’horloge et les pads d’entrées sorties est présentée dans le chapitre 8. La phase de back-end avec les layouts des cellules retenues dans la partie II ainsi que leur intégration dans des ensembles (clusters) est présentée dans le chapitre 9 avec le padring et l’intégration finale des macro-ensembles (Cores analogiques et numériques)After a a brief recall of the context this research work have been carried, the 1st chapter present the common analog to digital converters (ADC) characteristics with their figures of merit (FoM). A relevant state of the art on realized ADC architectures is presented. A particular emphasis has been done on 180 nm CMOS process node. This preliminary work gives a pertinent overview of the faced challenge. Multi step analog sampling architectures have been avoided from the study because of the transistors limited frequency performances. Chapter 2 presents the different implementations of the Flash digital sampling ADC family architecture. The TIQ architecture embedding in the 180 nm CMOS process are detailed in this chapter. Chapter 3 details the study and the design of an other digital sampling ADC family architecture on 180 nm CMOS process i.e. the signal folding architecture. This 1st part of the document conclude with the choice of the Flash ADC architecture. The building bloc design for this ADC are detailed in the following chapters constituting the part II. Chapter 4 is dedicated to the study and the design on 180 nm CMOS process of the latch comparator responsible of the 2 GHz sampling constraint of the overall ADC. As the retained comparator architecture input refereed non linearity defined the gain constraints of the preamplifier stage, the preamplifier is presented in the next chapter. Chapter 5 present the different characteristics and techniques of the quantifier stage. The comparator preamplifier stage with its different actives loads, its passive full differential transposition and the retained architecture are detailed. The QV technique and its embedding in the retained preamplifier architecture are presented. The thermometric 1 to binary encoder tree is presented in chapter 6. Two implementations of this encoding are studied and design on the Front-End (FE) level. The 1st one is a pipelined Wallace tree realized with a register transfer level (RTL) code on VHDL hardware description language. The synthesis flow on CMOS pull-up pull-down 2 combinatorial logic and rising edge flip flops are used for this architecture. The other architecture is designed using 1 bits multiplexers combinatorial pipelined with pass gated D latches with a full custom schematic implementation. Chapter 7 presents the limitations and the embedding of the interpolation with the retained preamplifier and comparator latch. The study of common drain source follower (CDSF) pairs insertion, mandatory for the biasing of the preamplifier input stage to reach the 8 bits resolution is studied with details. Finally, Monte Carlo sampling mismatch 3 analysis on the resistor references are studied by comparing different topologies and sizing. The overall ADC synoptic is presented with the retained cells and techniques. The bottom-up design approach, mandatory for analog and full-custom design, exposed in this 2nd part conclude on the choice to design a proof of concept ASIC (BuBlC1) including all the critical piece of circuits of the overall ADC with added value and potentially critical for signal conversion. The top-down approach for this ASIC design is detailed in the IIIrd part with the overall ASIC synoptic of the BuBlC1 ASIC sent to multi project wafer (MPW) foundry run integrating all the critical cells.The FE design of this ASIC with its clock tree and its input/output PAD are presented in chapter 8. The Back-End design with the retained cells layout in part II with the cells integration in clusters are presented in chapter 9 with the pad-ring and final integration in digital and analog macro-cells cores
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Truyen, David. "Etude par simulation composant 3D des effets singuliers SEU et SET induits par ions lourds sur le noeud technologique CMOS bulk 180 nm." Montpellier 2, 2007. http://www.theses.fr/2007MON20139.
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Johansson, Jimmy. "Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-138446.
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Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.
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Arnim, Klaus von [Verfasser]. "Digitale Schaltungstechniken für Sub-100-nm-CMOS-Technologien / Klaus von Arnim." Kiel : Universitätsbibliothek Kiel, 2009. http://d-nb.info/1019813423/34.
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Mehdi, Ghulam. "Highly Linear Mixer for On-chip RF Test in 130 nm CMOS." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8001.
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The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as much advanced test equipments and instruments are needed to carry out the sophisticated performance tests. To avoid this higher cost and to reduce the test time, the alternative is to perform on-chip test. .In RF transceivers, loopback is an on-chip test technique in which Tx signal, instead of radiating through antenna is fed to the Rx chain through a test attenuator (TA) during the test mode. A highly linear offset mixer is needed to implement this on-chip loopback test for these transceivers. The aim of this thesis work is to design a highly linear upconversion offset mixer for loopback test in CMOS technology. This mixer is designed for Bluetooth and GSM/EDGE standards.
Few highly linear mixer architectures were simulated in 0.35um AMS process using Cadence SpectreRF software. When compared with active mixers, passive mixer consumes no dc power and there is significant reduction in silicon area overhead. The thesis presents a highly linear passive mixer with very low conversion loss and noise figure. The mixer is designed in 0.13um AMS CMOS process for higher cut off frequency and improved conversion loss. Pre and Post layout simulation results of the designed mixer are presented.
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Arora, Rajan. "Trade-offs between performance and reliability of sub 100-nm RF-CMOS technologies." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50140.
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The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.
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Strzelecki, Joseph Benito. "Wideband Automatic Gain Control Design in 130 nm CMOS Process for Wireless Receiver Applications." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440773805.
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Pavageau, Christophe. "Utilisation des technologies CMOS SOI 130 nm pour des applications en gamme de fréquences millimétriques." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2005. http://tel.archives-ouvertes.fr/tel-00011744.
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La technologie CMOS SOI (« Silicon On Insulator ») a déjà montré son intérêt pour les circuits numériques par rapport à la technologie CMOS sur substrat massif (« bulk »). Avec l'entrée des technologies CMOS dans l'ère des dimensions nanométriques, les transistors atteignent des fréquences de coupures élevées, ouvrant la voie aux applications hyperfréquences et de ce fait à l'intégration sur la même puce des circuits numériques, analogiques et hyperfréquences. Cependant, la piètre qualité des éléments passifs reste le principal verrou des technologies CMOS pour y parvenir.Les travaux effectués lors de cette thèse portaient sur l'étude des aptitudes de la technologie CMOS SOI 130 nm de ST-Microelectronics pour des applications hyperfréquences au-delà de 20 GHz. Ils consistaient plus précisément à concevoir des circuits de démonstration pouvant entrer dans la composition d'une chaîne d'émission/réception. Trois amplificateurs distribués en bande K ont d'abord été conçus et mesurés. Malgré des pertes élevées dans les lignes de transmission limitant ainsi la bande passante et le gain, les performances mesurées montrent l'intérêt de cette technologie pour les hyperfréquences. Ensuite, une nouvelle série de démonstrateurs – amplificateurs distribués, amplificateurs faible bruit et mélangeurs actifs – a été conçue en employant des lignes à plus faibles pertes que celles utilisées précédemment. Les résultats de simulation montrent que le produit gain-bande des amplificateurs distribués a doublé en conservant la même architecture. Les simulations des amplificateurs faible bruit et des mélangeurs actifs montrent des performances à l'état de l'art en CMOS.
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Yang, Lianfeng. "Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications." Thesis, University of Glasgow, 2004. http://theses.gla.ac.uk/5349/.
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Drift-Diffusion, Hydrodynamic and Monte Carlo simulations have been used in this work to simulate strained Si/SiGe devices for RF and CMOS applications. For numerical simulations of Si/SiGe devices, strain effects on the band structure of Si have been analyzed and analytical expressions are presented for parameters related to the bandgap and band alignment of Si/SiGe heterostructure. Optimization of n-type buried strained Si channel Si/SiGe MODFETs has been carried out in order to achieve high RF performance and high linearity. The impact of both lateral and vertical device geometries and different doping strategies has been investigated. The impact of the Ge content of the SiGe buffer on the performance of p-type surface channel strained Si/SiGe MOSFETs has been studied. Hydrodynamic device simulations have been used to assess the device performance of p-type strained Si/SiGe MOSFETs down to 35 nm gate lengths. Well-tempered strained Si MOSFETs with halo implants around the source/drain regions have been simulated and compared with those devices possessing only a single retrograde channel doping. The calibrations in respect of sub-100 nm Si and strained Si MOSFETs fabricated by IBM lead to a scaling study of those devices at 65 nm, 45 nm and 35 nm gate lengths. Using Drift-Diffusion simulations, ring oscillator circuit behaviour has been evaluated. Strained Si on insulator (SSOI) circuits have also been simulated and compared with strained Si circuits, Si circuits employing conventional surface channel MOSFETs along with SOI devices. Ensemble Monte Carlo simulations have been used to evaluate the device performance of n-type strained Si MOSFETs. A non-perturbative interface roughness scattering model has been used and validated by calibrating with respect to experimental mobility behaviour and device characteristics. The impact of interface roughness on the performance enhancement of strained Si MOSFETs has been investigated and evidence for reduced interface roughness scattering is presented, i.e., a smoother interface is suggested in strained Si MOSFETs. A 35 nm gate length Toshiba Si MOSFET has been simulated and the performance enhancement of 35 nm strained Si MOSFETs over the Toshiba Si device is predicted. Monte Carlo simulations are also employed to investigate the performance degradation due to soft-optical phonon scattering, which arises with the introduction of high-K gate dielectrics. Based on the device structures of the calibrated sub-100 nm n-type conventional and strained Si IBM MOSFETs, significant current degradation has been observed in devices with high-K gate dielectrics, HfO2 and Al2O3.
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Pavageau, Christophe Danneville François Picheta Laurence. "Utilisation des technologies CMOS SOI 130 nm pour des applications en gamme de fréquences millimétriques." Villeneuve d'Ascq : Université des sciences et technologies de Lille, 2007. https://iris.univ-lille1.fr/dspace/handle/1908/388.
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Reproduction de : Thèse de doctorat : Microondes et microtechnologies : Lille 1 : 2005.N° d'ordre (Lille 1) : 3704. Résumé en français et en anglais. Titre provenant de la page de titre du document numérisé. Bibliogr. à la suite de chaque chapitre. Liste des publications.
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Le, Neel Olivier. "Développement et caractérisation d'une filière CMOS W/AL 0,5 micron sur substrat soi mince (100 nm)." Rennes 1, 1991. http://www.theses.fr/1991REN10154.
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Le silicium-sur-isolant (soi) a connu un regain d'interet ces 10 dernieres annees avec l'avenement de nouveaux materiaux de bonne qualite cristalline. De nombreux laboratoires ont tente de montrer les possibilites de gain en performances apportees par ce materiau dans les filieres cmos vlsi. C'est dans ce cadre que nous avons mene une etude sur la faisabilite d'une filiere submicronique sur soi. Cette etude presente les specificites et les avantages potentiels des dispositifs mos realises sur soi. Nous avons eu l'occasion d'etudier les performances des dispositifs sur films epais et sur films minces. Nous avons etudie les effets parasites associes: echauffement, canal parasite de flancs, transistor face arriere et effet bipolaire lateral. Ce dernier apparait aujourd'hui comme la principale limitation de cette technologie sur soi en films minces. Note etude a dans le meme temps consiste a preparer une filiere cmos 0,5 micron double metal (w-al). Le passage a des films tres minces a necessite le developpement d'outils specifiques de suivi de filiere. Il a aussi et peut-etre surtout, demande la definition et l'analyse d'etapes de procede specifiques d'un procede cmos submicronique sur soi: isolement, ajustements de tensions de seuil, alignement de photos. . . Notre analyse des procedes disponibles nous a amene a donner des limitations dans la course vers l'amincissement du film soi. Nos conclusions montrent que des procedes specifiques sont necessaires pour une filiere cmos sur soi et que des circuits faible consommation ne seront obtenus, en technologies profondement submicroniques, que par de grandes avancees sur le dispositif lui-meme et au prix de modifications electriques sur les circuits: conception, alimentation. . .
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Dang, Jin [Verfasser]. "Design and Characterization of K-Band Receiver Front-End Integrated Circuits in 130 nm CMOS / Jin Dang." Aachen : Shaker, 2015. http://d-nb.info/1080762132/34.
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Obermann, Theresa [Verfasser]. "Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology / Theresa Obermann." Bonn : Universitäts- und Landesbibliothek Bonn, 2017. http://d-nb.info/1140525980/34.
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Kanoun, Moez. "Conception d'un convertisseur temps-numérique dédié aux applications de tomographie optique diffuse en technologie CMOS 130 nm." Thèse, Université de Sherbrooke, 2014. http://hdl.handle.net/11143/6015.
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La mesure de temps de vol de photons et/ou de temps de propagation d’ondes RF et ultra large bande est devenue une technique essentielle et indispensable pour de nombreuses applications telles qu’en géolocalisation en intérieur, en détection LASER et en imagerie biomédicale, notamment en tomographie optique diffuse (TOD) avec des mesures dans le domaine temporel (DT). De telles mesures nécessitent des convertisseurs temps-numérique aptes à mesurer des intervalles de temps très courts avec grande précision, et ce, à des résolutions temporelles allant de quelques picosecondes à quelques dizaines de picosecondes.
Les scanners TOD-DT ont généralement recours à des cartes électroniques de comptage de photons uniques intégrant essentiellement des convertisseurs temps-numérique hybrides (un mixte de circuits monolithiques et non-monolithiques). Dans le but de réduire le temps d’acquisition de ces appareils et d’augmenter leur précision, plusieurs mesures à différentes positions et longueurs d’ondes doivent pouvoir être effectuées en parallèle, ce qui exige plusieurs cartes de comptage de photons. L’implémentation de tels dispositifs en technologie CMOS apporte de multiples avantages particulièrement en termes de coût, d’intégration et de consommation de puissance.
Cette thèse apporte une solution architecturale d’un convertisseur temps-numérique à 10-bits dédié aux applications de TOD-DT. Le convertisseur réalisé en technologie CMOS 0,13 μm d’IBM et occupant une surface en silicium de 1,83 x 2,23 mm[indice supérieur 2] incluant les plots de connexion, présente une résolution temporelle de 12 ps sur une fenêtre de 12 ns pour une consommation en courant de 4,8 mA. Les avantages de l’architecture proposée par rapport à d’autres réalisations rapportées dans la littérature résident dans son immunité face aux variations globales du procédé de fabrication, l’indépendance de la résolution temporelle vis-à-vis de la technologie ciblée et la faible gigue temporelle qu’il présente.
Le circuit intégré réalisé trouvera plusieurs champs d’applications autres que la TOD notamment dans les tomographes d’émission par positrons, les boucles à verrouillage de phase numériques et dans les systèmes de télédétection et d’imagerie 3D.
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Huang, Amy. "On the plasma induced degradation of organosilicate glass (OSG) as an interlevel dielectric for sub 90 nm CMOS /." Online version of thesis, 2008. http://hdl.handle.net/1850/5899.
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Rinderknecht, Jochen. "Phase formation and size effects in nanoscale silicide layers for the sub-100 nm microprocessor technology." Doctoral thesis, [S.l.] : [s.n.], 2005. http://deposit.ddb.de/cgi-bin/dokserv?idn=976612445.
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Rinderknecht, Jochen. "Phase formation and size effects in nanoscale silicide layers for the sub-100 nm microprocessor technology." Doctoral thesis, Technische Universität Dresden, 2004. https://tud.qucosa.de/id/qucosa%3A24562.
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Silizide spielen ein wesentliche Rolle in den technologisch fortschrittlichsten CMOS Bauteilen. Sie finden Verwendung als Kontaktmaterial auf den Aktivgebieten und dem Silizium Gatter von Transistoren. Diese Arbeit beschäftigt sich mit den Systemen: Co-Si, Co-Ni-Si und Ni-Si. Sowohl in situ Hochtemperatur-SR-XRD Experimente als auch CBED wurden zur Phasenidentifikation herangezogen. AES erlaubte es, Elementverteilungen in Schichtstapeln zu bestimmen. Für Studien über Agglomerationserscheinungen wurde REM eingesetzt. TEM und analytisches TEM trugen nicht nur zu Einblicken in Schichtstrukturen und Kornformen bei, sondern lieferten auch Daten zu Elementverteilungen in Silizidschichten. Diese Dissertation gliedert sich in zwei Hauptteile. Der erste Teil beschäftigt sich mit den Phasenbildungsabfolgen und den Phasenbildungs- und Umwandlungstemperaturen in nanoskaligen dünnen Schichten. Als Trägermaterial wurden einkristalline und polykristalline Siliziumsubstrate verwendet. Der Einfluß verschiedener Dotierungen im Vergleich zu undotierten Substraten sowie die Beeinflussung der Silizidierung durch eine Deckschicht wurden untersucht. Im zweiten Teil waren Größeneffekte verschiedener Schichtdicken und Agglomerationserscheinungen Gegenstand von Untersuchungen. Unterschiede bei der Silizidierung in Zusammenhang mit unterschiedlichen Schichtdicken wurden bestimmt. Darüberhinaus wurde eine ternäre CoTiSi Phase gefunden und identifiziert. Außerdem konnte die stark eingeschränkte Mischbarkeit der Monosilizide CoSi und NiSi gezeigt werden. Der thermische Ausdehnungskoeffizient von NiSi im Temperaturbereich 400?700°C und sein nicht-lineares Verhalten wurden bestimmt.Silicides are an essential part of state-of-the-art CMOS devices. They are used as contact material on the active regions as well as on the Si gate of a transistor. In this work, investigations were performed in the systems Co-Si, Co-Ni-Si, and Ni-Si. In situ high temperature SR-XRD and CBED techniques were used for phase identification. AES enabled the determination of elemental concentrations in layer stacks. SEM was applied to agglomeration studies. TEM imaging and analytical TEM provided insights into layer structures, grain morphology as well as information about the distribution of chemical elements within silicide layers. This thesis is divided into two main parts. The first part deals with the phase formation sequences and the phase formation and conversion temperatures in nanoscale thin films on either single crystal or polycrystalline Si substrates. The effect of different types of dopants vs. no doping and the impact of a capping layer on the phase formation and conversion temperatures were studied. In the second part, size effects and agglomeration of thin silicide films were investigated. The effect of different layer thicknesses on the silicidation process was studied. Additionally, the degree of agglomeration of silicide films was calculated. Furthermore, the ternary CoTiSi phase was found and identified as well as the severely limited miscibility of the monosilicides CoSi and NiSi could be shown. The CTE of NiSi between 400?700 ±C and its non-linear behavior was determined.
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Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.
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This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.
The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.
In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.
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Assaad, Maher. "Design and modeling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications." Thesis, University of Glasgow, 2009. http://theses.gla.ac.uk/707/.
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Abstract This thesis describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The proposed design was implemented and fabricated using the 130 nm CMOS technology offered by UMC (United Microelectronics Corporation). Different PLL-based CDR circuits topologies were investigated in terms of architecture and speed. Based on the investigation, we proposed a new concept of quarter-rate (i.e. the clocking speed in the circuit is 2.5 GHz for 10 Gb/s data rate) and dual-loop topology which consists of phase-locked and frequency-locked loop. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. A new quarter-rate phase detector based on the non-linear early-late phase detector concept has been used to achieve the multi-Giga bit/s speed and to eliminate the need of the front-end data pre-processing (edge detecting) units usually associated with the conventional CDR circuits. An eight-stage differential ring oscillator running at 2.5 GHz frequency center was used for the voltage-controlled oscillator (VCO) to generate low-jitter multi-phase clock signals. The transistor level simulation results demonstrated excellent performances in term of locking speed and power consumption. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modelled at gate level using the Verilog-A language and time-domain simulated.
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DUTRA, Odilon de Oliveira. "Implementação de Neurônio Artificial em Tecnologia CMOS IBM 130 nm utilizando o Modelo de Izhikevich em Topologia Translinear Dinâmica com Transistores Halo-Implantados." reponame:Repositório Institucional da UNIFEI, 2015. http://repositorio.unifei.edu.br:8080/xmlui/handle/123456789/123.
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Este trabalho descreve a implementação do modelo neural de Izhikevich em circuitos dinâmicos translineares - DTL - através da utilização de dispositivos halo-implantados em tecnologia 130 nm. Um desenho em forma matricial de ordem x é capaz de, não apenas, substancialmente aumentar a impedância de saída de tais transistores haloimplantados devido à diminuição do efeito LDIBL, mas também melhorar o descasamento e a degradação da transcondutância, tornando-os elementos translineares aplicáveis a circuitos de ultra-baixa-tensão e ultra-baixa-potência. O neurônio proposto foi simulado com sucesso em IBM CMOS 130 nm. O mesmo é capaz de gerar os 20 padrões previstos pelo modelo para neurônios tálamo-corticais como outros trabalhos com implementações diferentes, mas melhorando diversos aspectos como a utilização de baixíssima tensão de alimentação de 250 mV. Mesmo não tendo sido possível a medição dos diversos padrões, a medição de diversos espelhos de corrente implementados no chip para auxílio da polarização do circuito, bem como a caracterização das matrizes, medição do comportamento estático de um filtro passa-baixas DTL que implementa a acomodação do neurônio e também a comparação de um padrão neural fictício com sua simulação demonstraram funcionamentos muito similares aos obtidos nas simulações, indicando que a topologia adotada é uma boa opção para a implementação de circuitos DTL em ultra-baixa-tensão e ultra-baixa-potência.
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Desaulniers, Lamy Étienne. "Réalisation d’un convertisseur temps-numérique pour une application de détection monophotonique." Mémoire, Université de Sherbrooke, 2015. http://hdl.handle.net/11143/6754.
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Le Groupe de recherche en appareillage médical de Sherbrooke possède une expertise unique dans la conception de scanners à tomographie d’émission par positrons. Le fonctionnement de la tomographie d’émission par positrons repose sur la détection de photons d’annihilation colinéaires par un agencement de cristaux scintillateurs, photodétecteurs, convertisseurs temps-numérique et électronique de traitement. Une partie du groupe de recherche s’oriente vers l’utilisation des matrices de photodiodes à avalanches opérées en mode Geiger, afin d’obtenir une meilleure résolution temporelle du système et un seuil de détection plus faible que les générations précédentes,ce qui permet de détecter les premiers photons émis par le cristal scintillateur.
Le convertisseur temps-numérique (TDC) développé se veut un bloc polyvalent et réutilisable mesurant des intervalles de temps avec grande précision. Son développement cible des applications de détection monophotoniques avec estampilles temporelles comme la tomographie optique dffuse, les caméras 3D ou la tomographie d’émission par positrons. Il s’intègre ici dans un circuit intégré en CMOS 130 nm assemblé verticalement avec plusieurs gaufres et dédié à la détection en tomographie d’émission par positron. La méthodologie de conception du convertisseur temps-numérique s’inspire d’une approche en signaux mixtes avec suprématie du numérique.
En simulation, le TDC développé arbore une résolution de 14,5 ps, une non-linéarité différentielle de 1 bits de poids faible, une non-linéarité intégrale de 2,2 bits de poids faible, une fréquence de conversion de 11,1 millions d’échantillons par seconde, une plage dynamique de 5 ns, une puissance moyenne consommée en moyenne de 4,5 mW et une taille de 0,029 mm². Un mécanisme pour améliorer la résolution du TDC a été intégré dans un exemplaire du TDC. Son utilisation a permis d’obtenir une résolution de 12,6 ps sur un exemplaire du circuit fabriqué. Ces travaux ont permis d’explorer l’architecture en oscillateur vernier avec anneaux et d’en faire ressortir plus clairement les avantages, les inconvénients et les écueils à surveiller lors de la conception.
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Boisvert, Alexandre. "Conception d'un circuit d'étouffement pour photodiodes à avalanche en mode Geiger pour intégration hétérogène 3D." Mémoire, Université de Sherbrooke, 2014. http://hdl.handle.net/11143/6153.
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Le Groupe de Recherche en Appareillage Médical de Sherbrooke (GRAMS) travaille actuellement sur un programme de recherche portant sur des photodiodes à avalanche monophotoniques (PAMP) opérées en mode Geiger en vue d'une application à la tomographie d’émission par positrons (TEP). Pour opérer dans ce mode, la PAMP, ou SPAD selon l’acronyme anglais (Single Photon Avalanche Diode), requiert un circuit d'étouffement (CE) pour, d’une part, arrêter l’avalanche pouvant causer sa destruction et, d’autre part, la réinitialiser en mode d’attente d’un nouveau photon. Le rôle de ce CE comprend également une électronique de communication vers les étages de traitement avancé de signaux. La performance temporelle optimale du CE est réalisée lorsqu’il est juxtaposé à la PAMP. Cependant, cela entraîne une réduction de la surface photosensible ; un élément crucial en imagerie. L’intégration 3D, à base d'interconnexions verticales, offr une solution élégante et performante à cette problématique par l’empilement de circuits intégrés possédant différentes fonctions (PAMP, CE et traitement avancé de signaux). Dans l’approche proposée, des circuits d’étouffement de 50 [mu]m x 50 [mu]m réalisés sur une technologie CMOS 130 nm 3D Tezzaron, contenant chacun 112 transistors, sont matricés afin de correspondre à une matrice de PAMP localisée sur une couche électronique supérieure. Chaque circuit d'étouffement possède une gigue temporelle de 7,47 ps RMS selon des simulations faites avec le logiciel Cadence. Le CE a la flexibilité d'ajuster les temps d'étouffement et de recharge pour la PAMP tout en présentant une faible consommation de puissance ( ~ 0,33 mW à 33 Mcps). La conception du PAMP nécessite de supporter des tensions supérieures aux 3,3 V de la technologie. Pour répondre à ce problème, des transistors à drain étendu (DEMOS) ont été réalisés. En raison de retards de production par les fabricants, les circuits n’ont pu être testés physiquement par des mesures. Les résultats de ce mémoire sont par conséquent basés sur des résultats de simulations avec le logiciel Cadence.
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Huang, Shih-Yun, and 黃詩芸. "The Design of 180-nm CMOS 256-Pixel Sensing and Biphasic Current Stimulation Chips with Bidirectional-Sharing Electrodes and Charge Pump for Subretinal Prosthesis." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/eq66hv.
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Liao, Jung-Hsing, and 廖容興. "THE DESIGN OF 180-NM CMOS 480-PIXEL SENSING AND BIPHASIC CURRENT STIMULATION CHIPS WITH FOUR DIRECTIONAL SHARING ELECTRODES AND CHARGE PUMP FOR SUBRETINAL PROSTHESIS." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/9u4376.
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碩士國立交通大學
電子研究所
106
A photovoltaic-cell-powered CMOS 480-pixel implantable chip is proposed for subretinal prostheses. In the proposed chip, the divisional power supply scheme (DPSS) and the active pixel sensor (APS) are adopted to improve the efficiency of output stimulation currents and the image sensitivity. The proposed chip consists of totally 480 photodiode array with 32 DPSS divisions, control signal generator circuits, and photovoltaic cells. It is designed and fabricated in 180-nm CMOS image sensor (CIS) technology. The chip size is 3.1mm x 3.1mm. At first, the chip have not any output function. After FIB, this chip measured frequency of 32-phase control signals is 30 Hz under signal light intensity of 505.4 lux and background IR intensity of 94 mW/cm2. The measured output stimulation current is 9.0 μA under 10-kΩ load. Under the equivalent electrode impedance load, the measured frequency of 32-phase control signals is 38 Hz. The measured peak output stimulation current is 9.0 μA and the amount of injected charges per pixel is 9.8 nC. The measurement results have verified the correct function of the proposed subretinal implant chip after FIB.
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Sung, Wei-Jie, and 宋偉傑. "THE DESIGN OF 180-NM CMOS 256-PIXEL SENSING AND BIPHASIC STIMULATION CHIPS WITH ON-CHIP PHOTOVOLTAIC CELLS AND DIVISIONAL POWER SUPPLY SCHEME FOR SUBRETINAL PROSTHESES." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/gnd233.
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碩士國立交通大學
電子工程學系 電子研究所
104
A photovoltaic-cell-powered CMOS 256-pixel implantable chip is proposed for subretinal prostheses. In the proposed chip, the divisional power supply scheme (DPSS) and the active pixel sensor (APS) are adopted to improve the efficiency of output stimulation currents and the image sensitivity. The proposed chip consists of a 16x16 photodiode array with 8 DPSS divisions, control signal generator circuits, and photovoltaic cells. It is designed and fabricated in 180-nm CMOS image sensor (CIS) technology. The chip size is 3mm x 3mm. The DPSS11 measured frequency of eight-phase control signals is 47.68 Hz under signal light intensity of 5 mW/cm2 and background IR intensity of 80 mW/cm2. The measured output stimulation current is 19.9 μA under 10-kΩ load. Under the equivalent electrode impedance load, the measured frequency of eight-phase control signals is 45.45 Hz. The measured peak output stimulation current is 19.52 μA and the amount of injected charges per pixel is 1.1 nC. The DPSS12 measured frequency of eight-phase control signals is 30.2 Hz under signal light intensity of 0.4 mW/cm2 and background IR intensity of 80 mW/cm2. The measured output stimulation current is 19.95 μA under 10-kΩ load. Under the equivalent electrode impedance load, the measured frequency of eight-phase control signals is 30.2 Hz. The measured peak output stimulation current is 19.84 μA and the amount of injected charges per pixel is 1.64 nC. The measurement results have verified the correct function of the proposed subretinal implant chip. DPSS11—CMOS CIS 256-pixel subretinal chip version I DPSS12-- CMOS CIS 256-pixel subretinal chip version II
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Rezaee, Leila. "Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology." Thesis, 2008. http://hdl.handle.net/10012/4155.
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In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies.
In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature.
In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides.
In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide.
In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed.
An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks.
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Harish, B. P. "Process Variability-Aware Performance Modeling In 65 nm CMOS." Thesis, 2006. http://hdl.handle.net/2005/1080.
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With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation.
We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM).
To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets.
Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.
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Wang, Chun, and 王淳. "A 100-GHz Power Amplifier Design in 40-nm CMOS Process." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/12539437183740398588.
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碩士國立中央大學
電機工程學系
105
This thesis proposes a 100-GHz power amplifier design in TSMC 40-nm CMOS process. The power amplifier applies to the 200-GHz transmitter circuit. To avoid braking the next stage circuit, the power amplifier does not add the power combiner design which is designed for increasing the output power. The first part is the basic theories related to the design of power amplifiers, including the DC bias point of transistor and the load line theory. The second part is the design of the 100-GHz two stage power amplifiers. The common source mode is chosen in this design for its high gain characteristic. To increase the stability and gain , the cross couple capacitors is added for resonating the parasitic capacitors of the transistors. The transformers in this power amplifier are worked as the impedance matching network and balun. The power amplifier exhibits saturation output power of 9.49 dBm, maximum power-added efficiency (PAE) of 6.95%, and the output power at 1-dB gain compression point of 7.42 dBm. The 3-dB bandwidths is 31%. The third part is the design of the 200-GHz transmitter. This circuit consists of a voltage control oscillator (VCO), a driver amplifier, a power amplifier, a doubler, and an ASK modulator. The VCO generates the 100-GHz signal, and then it gets enough output power by driver amplifier and power amplifier. The operating frequency will be raised up to 200-GHz by doubler. The signal will be modulated with a digital data signal by ASK modulator in the end. This transmitter provides output power of -0.95 dBm and a data rate of 20 Gb/s at 200 GHz.
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Vidago, Fábio Daniel dos Santos. "A Downconversion Beamforming RF Front-End in 130 nm CMOS technology." Master's thesis, 2016. http://hdl.handle.net/10362/20371.
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Due to the exponential growth of wireless data communications an increasing number
of components compete for space in the frequency spectrum. Nowadays, different approaches have been addressed in order to overcome this problem. One of these approaches is using spatial filters instead of time-domain ones. Since most wireless devices operate
by transferring/receiving signals to/from all directions, interfering signals are becoming
an increasing problem. Thus steering the transmission/reception of signals in a specific
direction alleviates this problem, which is performed by employing multiple antennas.
In the scope of the spatial filtering approach, a 1 GHz downconvertion 4-element
phased array receiver front-end is presented in this thesis, implemented in 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The phase shifting of the beamforming receiver is implemented with a switched-capacitor vector modulator, that excels in its linearity and low power consumption. This receiver also provides a spatial rejection of more than 20 dB and good input matching.
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Sousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Dissertação, 2009. http://hdl.handle.net/10216/57854.
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Estágio realizado no CERN e orientado pelo Doutor Paulo Rodrigues Simões MoreiraTese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
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Sousa, Filipe José Pereira Alves de. "Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology." Master's thesis, 2009. http://hdl.handle.net/10216/57854.
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Estágio realizado no CERN e orientado pelo Doutor Paulo Rodrigues Simões MoreiraTese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
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Park, Peter. "A 4PAM/2PAM Coaxial Cable Receiver Analog Front-end Targeting 40Gb/s in 90-nm CMOS." Thesis, 2008. http://hdl.handle.net/1807/11160.
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A 4-PAM/2-PAM receiver analog front-end (AFE) targeting 20GSymbol/s for use with coaxial cable channels is presented. Behavioral simulations incorporate a transmitter, scalable coaxial cable model, and the proposed receiver architecture, targeting cable loss of 32dB at 10GHz. To accommodate links of varying lengths, the AFE includes a variable-gain amplifier (VGA) and analog peaking equalizer. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89mm2 in a 90-nm CMOS process and dissipates 138mW from a 1.3V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s 2-PAM data stream transmitted over coaxial cable with 7.5dB loss at 10GHz.
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Tomkins, Alexander. "W-Band Passive and Active Circuits in 65-nm Bulk CMOS for Passive Imaging Applications." Thesis, 2010. http://hdl.handle.net/1807/24285.
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The design and implementation of mm-wave switches, variable attenuators, and a passive imaging system in 65-nm CMOS are presented. The design and analysis of shunt switches is presented with a demonstration circuit showing record performance for a single-pole single-throw switch with 1.6dB loss and 30dB isolation at 94GHz. Single-pole double-throw (SPDT) switches are shown, with 4dB insertion loss in the W-band (75-110GHz), and the only reported SPDT switch operating in the D-band (110-170GHz). A novel technique for implementing digitally controlled variable attenuation is presented, resulting in variable attenuation between 4 and 30dB in the W-band. Finally, a W-band radiometer is described integrating a record-high gain CMOS LNA, SPDT switch, and peak detector. This is the highest-frequency imaging system in CMOS with this level of integration, offering a responsivity over 90kV/W, and a noise-equivalent power less than 0.2pW/√Hz.
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Sarvari, Siamak. "A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS." Thesis, 2010. http://hdl.handle.net/1807/29987.
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This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied.
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Dong, Yunzhi. "A High-speed Fiber-optic Receiver for Plastic Optical Fiber Applications in 65 nm CMOS process." Thesis, 2012. http://hdl.handle.net/1807/33978.
Full textAbstract:
This dissertation explores a few techniques to realize a low-cost monolithic fiber-optic receiver with large-area photo detectors in advanced CMOS processes that could potentially support multi-gigabit digital data across 10 to 20 meters plastic optical fibers (POF). The first techniques investigated in this dissertation are the use of an external pseudo-differential photo detector chip to reduce the impact of the inductive parasitics, and the use of a cross-coupled regulated-cascode (CC-RGC) buffer to relieve the DC voltage headroom issues found in conventional regulated-cascode (RGC) buffers in technologies with low power supply voltages. The second technique investigated in this thesis is the super-Gm transimpedance amplifier (SGM-TIA) that can be used to produce a very small input impedance in order to drive a very large parasitic capacitance exhibited by an integrated photo detector in advanced CMOS processes. The third technique investigated is a linear equalizer with multiple shunt-shunt feedbacks that can be utilized to produce a slowly-rising peaking response in order to compensate for the frequency-dependent losses exhibited by the integrated NW/P-sub photo detector. Two prototype POF receiver test chips have been implemented in TSMC’s 65 nm CMOS processes and non-return-to-zero optical data transmissions have been demonstrated at data rates up to 3.125 Gbps and 4.25 Gbps, respectively, with a 2.5 Gbps grade 670 nm vertical-cavity surface-emitting laser based electro-optical transmitter.
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Wu, Chun-Tung, and 吳俊東. "A 1.2V 10bits 100-MS/s Pipelined Analog-to-Digital Converter in 90 nm CMOS Technology." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57294340146917364857.
Full textAbstract:
碩士國立中山大學
資訊工程學系研究所
98
The trend toward higher-level circuit integration is the result of demand for lower cost and smaller feature size. The goal of this trend is to have a single-chip solution, in which analog and digital circuits are placed on the same die with advanced CMOS technology. The complete integration of a system may include a digital processor, memory, ADC, DAC, signal conditioning amplifiers, frequency translation, filtering, reference voltage/current generator, etc. Although advanced fabrication technology benefits digital circuits, it poses great challenges for analog circuits. For instance, the scaling of CMOS devices degrades important analog performance such as output resistance, lowering amplifier gain. Simply lowering the power supply voltage in analog circuits does not necessarily result in lower power dissipation. The many design constraints common to the design of analog circuits makes it difficult to curb their power consumption. This is especially true for already complicated analog systems like ADCs; reducing their appetite for power requires careful analysis of system requirements and special strategies. This thesis describes a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers and so on. The ADC is designed in a 90nm CMOS technology with a 1.2V supply voltage.
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Lin, Yu-Sheng, and 林育生. "Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/71728309638341650656.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
93
This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices. In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thicknesses. In chapter 3, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with high-k gate dielectric. With the same physical thickness or effective thickness, we compare it with conventional oxide. In chapter 4, we discuss the tunneling effect on capacitance behavior. With the same physical thickness or effective thickness, we report the tunneling phenomenon with various gate dielectrics. Chapter 5 is related to 2D device physics, we discuss FIBL(fringing-induced barrier lowering) in subthreshold region with various gate dielectrics, sidewalls, and drain voltages.