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Relevant bibliographies by topics / 28FDSOI

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Journal articles
Dissertations / Theses
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Academic literature on the topic '28FDSOI'

Author: Grafiati

Published: 4 June 2021

Last updated: 10 February 2022

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Journal articles on the topic "28FDSOI"

1

Arabi, M., X. Federspiel, F. Cacho, et al. "Temperature dependence of TDDB at high frequency in 28FDSOI." Microelectronics Reliability 100-101 (September 2019): 113422. http://dx.doi.org/10.1016/j.microrel.2019.113422.

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2

"Enhanced Scan Segmentation for Low Power DFT." International Journal of Innovative Technology and Exploring Engineering 8, no. 9 (2019): 1557–61. http://dx.doi.org/10.35940/ijitee.h7428.078919.

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Excessive test power dissipation during scan testing of an SOC may cause reliability and yield concerns for the circuit under test (CUT). We propose an enhanced scan segmentation method using logic cluster controllability (LoCCo) technique for scan chain stitching to reduce test power efficiently. After LoCCo based scan stitching, since the trailing edge of scan chains contain very less switching transitions, we optimize the number of segments needed. This enables segmentation hardware reduction and still achieve lower power scan test compared to conventional method. Test cases prepared from ITC’99 standard circuits and industrial designs in 40nm CMOS and 28FDSOI technology were used for comparison. LoCCo based scan segmentation gave a shift power reduction of up-to 21.7% over conventional scan segmentation. Up-to 8.6%, shift power gain was observed even with 25% reduced segmentation when enhanced scan segmentation technique is used

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Dissertations / Theses on the topic "28FDSOI"

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Penzes, Maxime. "Caractérisation et simulation de défauts induits par laser 1340 nm continu sur la technologie 28FDSOI en analyse de défaillance électrique." Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0028/document.

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Face à la densité importante d’intégration des transistors et du nombre de niveau de métallisation, la localisation de défaut en analyse se fait principalement par la face arrière du composant. Cette analyse par la face arrière impose l’utilisation systématique de lentille à immersion solide et de la microscopie à balayage laser afin de limiter la contrainte de la résolution spatiale et de la sensibilité. Les objectifs sont de déterminer les dégradations induites par un laser 1340 nm continu sur la technologie 28FDSOI et de fournir un outil de simulation permettant de prédire la dose admissible par les transistors. L’étude commence par la reproduction et la caractérisation du défaut induit par le laser. Les résultats montrent principalement une diffusion des interconnexions grille-contacts en NiPtSi. Basé sur ces observations, un modèle de stimulation laser thermique est construit, puis testé sur une structure élémentaire. Les résultats montrent que la température peut atteindre des valeurs suffisamment élevées pour provoquer la diffusion du siliciure et expliquer les observations. Dans la dernière partie, le modèle est mis à l’épreuve sur des structures réelles. Le défaut est caractérisé paramétriquement en utilisant la cartographie de fréquence. Parallèlement, la simulation est appliquée sur ces mêmes structures. Les résultats montrent une bonne capacité du modèle à prédire le seuil de dégradation des transistors sous stimulation thermique laser<br>Faced with the high density of integration of the transistors and the number of metallization level, fault localization in analysis is mainly done by the rear face of the component. This backside analysis requires the systematic use of solid immersion lenses and laser scanning microscopy to limit the stress of spatial resolution and sensitivity. The objectives are to determine the degradation induced by a continuous 1340 nm laser on the 28FDSOI technology and to provide a simulation tool for predicting the allowable dose by the transistors. The study begins with the reproduction and characterization of the laser-induced defect. The results mainly show a diffusion of grid-contact interconnections in NiPtSi. Based on these observations, a model of thermal laser stimulation is built and then tested on an elemental structure. The results show that the temperature can reach sufficiently high values to cause the diffusion of the silicide and to explain the observations. In the last part, the model is put to the test on real structures. The defect is characterized parametrically using frequency mapping. Simultaneously, the simulation is applied to these same structures faithfully. The results show a good ability of the model to predict the degradation threshold of the transistors under laser thermal stimulation

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Book chapters on the topic "28FDSOI"

1

Ilakal, Anand, and Anuj Grover. "Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies." In Communications in Computer and Information Science. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_41.

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Conference papers on the topic "28FDSOI"

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Dwivedi, Varun Kumar, Meenakshi Didharia, Madhvi Sharma, and Manoj Kumar Sharma. "Comparative Study of Analog Matching Structures in 28FDSOI." In 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID). IEEE, 2019. http://dx.doi.org/10.1109/vlsid.2019.00111.

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2

Planes, Nicolas, S. Kohler, A. Cathelin, C. Charbuillet, P. Scheer, and F. Arnaud. "28FDSOI technology for low-voltage, analog and RF applications." In 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2016. http://dx.doi.org/10.1109/icsict.2016.7998825.

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3

Singh, Saurabh Kumar, and Gautam Dey Kanungo. "Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI." In 2015 28th International Conference on VLSI Design (VLSID). IEEE, 2015. http://dx.doi.org/10.1109/vlsid.2015.49.

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4

Bansal, Nitin, Saurabh Kumar Singh, Hemant Shukla, and Madhvi Sharma. "A 0.29ps FOM Fast Transient any Cap Stable LVR in 28FDSOI." In 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). IEEE, 2018. http://dx.doi.org/10.1109/vlsid.2018.89.

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5

Vallet, Mathieu, Olivier Richard, Yann Deval, and Didier Belot. "A very low power CMOS 28FDSOI programmable fractional frequency divider for Wifi-WiGig." In 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2014. http://dx.doi.org/10.1109/s3s.2014.7028234.

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Arfaoui, W., X. Federspiel, A. Bravaix, P. Mora, A. Cros, and D. Roy. "Application of compact HCI model to prediction of process effect in 28FDSOI technology." In 2014 IEEE International Integrated Reliability Workshop Final Report (IIRW). IEEE, 2014. http://dx.doi.org/10.1109/iirw.2014.7049513.

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7

Dhar, Siddhartha, Johan Bourgeat, and Chittoor Parthasarathy. "Towards a TCAD Model for NMOS Drivers in 28FDSOI under TLP & (vf)-TLP Transient Condition." In 2019 41st Annual EOS/ESD Symposium (EOS/ESD). IEEE, 2019. http://dx.doi.org/10.23919/eos/esd.2019.8870008.

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