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Journal articles on the topic '28nm'

Author: Grafiati

Published: 9 March 2023

Last updated: 31 July 2025

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1

Kalia, Kartik, Khyati Nanda, Arushi Aggarwal, Akshita Goel, and Shivani Malhotra. "Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA." Advanced Materials Research 1098 (April 2015): 37–43. http://dx.doi.org/10.4028/www.scientific.net/amr.1098.37.

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In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM

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2

Chen, Fu Ping, Hai Bo Lei, Xiao Yan Zhang, et al. "High Performance, Eco-Friendly SPM Cleaning Technology Using Integrated Bench-Single Wafer Cleaning System." Solid State Phenomena 314 (February 2021): 133–39. http://dx.doi.org/10.4028/www.scientific.net/ssp.314.133.

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Batch SPM systems do not meet the current clean specification/requirements below 28nm. Single wafer SPM systems use a high volume of chemistry which runs to drain, while meeting the cleaning specifications below 28nm. The work in this paper describe the use of a batch SPM system and a single wafer clean in an integrated system, Ultra-C Tahoe which results in meeting the technical specification and using less that 80% of the SPM chemistry used in single wafer systems. The data collected shows this new system meet the specifications, whilst saving more than 80%of SPM chemistry.

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3

Zhang, Beichao, Bin Zhang, Haibo Xiao, et al. "Thin Film Challenges in 28nm Technology Node." ECS Transactions 44, no. 1 (2019): 391–94. http://dx.doi.org/10.1149/1.3694344.

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4

Aguiar, V. A. P., N. H. Medina, N. Added, et al. "Thermal neutron induced upsets in 28nm SRAM." Journal of Physics: Conference Series 1291 (July 2019): 012025. http://dx.doi.org/10.1088/1742-6596/1291/1/012025.

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5

Rochefeuille, E., F. Alicalapa, A. Douyère, and T. P. Vuong. "FDSOI 28nm performances study for RF energy scavenging." IOP Conference Series: Materials Science and Engineering 321 (March 2018): 012009. http://dx.doi.org/10.1088/1757-899x/321/1/012009.

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6

., Anshu Gaur. "HDL IMPLEMENTATION OF AMBA AHB ON 28NM FPGA." International Journal of Research in Engineering and Technology 06, no. 06 (2017): 148–53. http://dx.doi.org/10.15623/ijret.2017.0606024.

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7

Gupta, Arpit, Aarushi Sapra, Alisha Nagpal, and Sanchit Sharma. "Energy Efficient Traffic Light Controller Design on 28nm FGPA." International Journal of Smart Home 9, no. 10 (2015): 133–44. http://dx.doi.org/10.14257/ijsh.2015.9.10.15.

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8

Chandra Verma, Puneet, Pragya Agarwal, Apurva Omer, Bhaskar Gururani, and Sanchit Verma. "Designing Green ECG Machine Based on Artix7 28nm FPGA." Gyancity Journal of Engineering and Technology 3, no. 1 (2017): 38–44. http://dx.doi.org/10.21058/gjet.2017.31006.

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9

Chang, Woong-Joo, Chae-Jun Lee, Joon-Hyung Kim, and Tae-Hwan Jang. "Cryogenic CMOS LNA in 28nm CMOS Process for Quantum Computing." Journal of the Institute of Electronics and Information Engineers 61, no. 10 (2024): 25–31. https://doi.org/10.5573/ieie.2024.61.10.25.

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10

Phu Phu, Tran Nguyen, Dang Phuong Gia Han, Nguyen Cong Luong, and Nguyen Van Cuong. "Design A Synchronous Single-Port Sram 1024x32xMUX4 Using 28NM Technology." International Journal of Computing and Digital Systems 10, no. 1 (2021): 103–9. http://dx.doi.org/10.12785/ijcds/100110.

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11

Shi, I., E. Tian, and C. Ren. "Defect Investigation of the Develop Process on 28nm Contact Mask." ECS Transactions 60, no. 1 (2014): 199–204. http://dx.doi.org/10.1149/06001.0199ecst.

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12

Tong, H., B. Zhang, H. Deng, et al. "Siconi Process Applications Study for 28nm Technology Node and Beyond." ECS Transactions 60, no. 1 (2014): 447–51. http://dx.doi.org/10.1149/06001.0447ecst.

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13

Saxena, Abhay, Swapnil Gaidhani, Anamika Pant, and Chandrashekhar Pate. "Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA." International Journal of Computer Trends and Technology 42, no. 2 (2016): 72–76. http://dx.doi.org/10.14445/22312803/ijctt-v42p112.

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14

Tudor, Bogdan, Joddy Wang, Zhaoping Chen, Robin Tan, Weidong Liu, and Frank Lee. "An accurate MOSFET aging model for 28nm integrated circuit simulation." Microelectronics Reliability 52, no. 8 (2012): 1565–70. http://dx.doi.org/10.1016/j.microrel.2011.12.008.

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15

Verma, Gaurav, Shikhar Maheshwari, Sukhbani Kaur, et al. "Low Power Squarer Design Using Ekadhikena Purvena on 28nm FPGA." International Journal of Control and Automation 9, no. 5 (2016): 281–88. http://dx.doi.org/10.14257/ijca.2016.9.5.27.

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16

Jin, Rui Min, Ding Zhen Li, Lan Li Chen, Xiang Ju Han, and Jing Xiao Lu. "Solid-Phase Crystallization of a-Si:H by RTA." Applied Mechanics and Materials 44-47 (December 2010): 4151–53. http://dx.doi.org/10.4028/www.scientific.net/amm.44-47.4151.

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Amorphous silicon films prepared by PECVD on glass substrate has been crystallized by rapid thermal annealing (RTA) at the same temperature for different time. From X-ray diffraction (XRD) and scanning electronic microscope (SEM), it is found that the grain size is biggest crystallized at 720°C for 8 min, an average grain size of 28nm or so is obtained. The thin film is smoothly and perfect structure.

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17

Banijamali, Bahareh, Suresh Ramalingam, and Raghunandan Chaware. "Advanced Thermal Study of Very High Power TSV Interposer and Interconnects for 28nm Technology FPGA." International Symposium on Microelectronics 2011, no. 1 (2011): 000665–68. http://dx.doi.org/10.4071/isom-2011-wp1-paper2.

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TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. This paper presents the thermal study of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um

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18

THARAYIL NARAYANAN, Aravind, Wei DENG, Dongsheng YANG, Rui WU, Kenichi OKADA, and Akira MATSUZAWA. "A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI." IEICE Transactions on Electronics E100.C, no. 3 (2017): 259–67. http://dx.doi.org/10.1587/transele.e100.c.259.

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19

Liao, C. I., T. C. Hsuan, C. C. Chien, et al. "High Quality Silicon Cap Layer for 28nm and Beyond PMOS Processes." ECS Transactions 50, no. 9 (2013): 419–24. http://dx.doi.org/10.1149/05009.0419ecst.

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20

Xing, B., J. Hao, G. Deng, J. Zhao, and Q. Wu. "Studies of the Water-Spot like Defect in 28nm Metal Layer." ECS Transactions 60, no. 1 (2014): 225–29. http://dx.doi.org/10.1149/06001.0225ecst.

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21

Diao, L., X. Meng, Q. Han, et al. "Defect Free HDIS Process for Sub 28nm HKMG Using Reducing Chemistry." ECS Transactions 60, no. 1 (2014): 313–18. http://dx.doi.org/10.1149/06001.0313ecst.

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22

Zhou, M., Q. Chai, Y. Chen, et al. "K Repair and RC Improvement in 28nm Logic Devices and Beyond." ECS Transactions 60, no. 1 (2014): 459–61. http://dx.doi.org/10.1149/06001.0459ecst.

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23

Lai, Jerander, Yi-Wei Chen, Nien-Ting Ho, et al. "NiPt salicide process improvement for 28nm CMOS with Pt(10%) additive." Microelectronic Engineering 92 (April 2012): 137–39. http://dx.doi.org/10.1016/j.mee.2011.05.028.

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24

Bhalla, Simran, Tanmeet Kaur, Kashish Bansal, Itanshu Ahuja, and Sabia Chawla. "LVCMOS IO Standard Based High Performance RAM Design on 28nm FPGA." International Journal of Control and Automation 9, no. 9 (2016): 213–20. http://dx.doi.org/10.14257/ijca.2016.9.9.21.

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25

Mahajan, Devanshi, and Daizy Gupta. "LVCMOS and BLVDS Based Energy Efficient Counter Design on 28nm FPGA." Gyancity Journal of Engineering and Technology 1, no. 2 (2015): 31–41. http://dx.doi.org/10.21058/gjet.2015.1206.

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26

Kilic, Mustafa, Themistoklis G. Mavrogordatos, and Yusuf Leblebici. "A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS." Analog Integrated Circuits and Signal Processing 97, no. 3 (2018): 397–404. http://dx.doi.org/10.1007/s10470-018-1222-5.

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27

Jia, Xiao Lin, Su Ping Li, Hai Jun Zhang, Jiang Tao Zhu, and He Long Hu. "Hydrothermal Synthesis of Nanosized Mullite Powders." Key Engineering Materials 368-372 (February 2008): 806–8. http://dx.doi.org/10.4028/www.scientific.net/kem.368-372.806.

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Nanosized mullite powders were prepared by hydrothermal method with bauxite as precursor. The effects of mineralizer, hydrothermal temperature, hydrothermal time, dispersant on the phase, crystal size and secondary granularity of the powders were discussed. The properties of the prepared powders were characterized by XRD, SEM, and ZETASIZER. The results show that the spherical nanosized mullite powders with crystal size of 28nm are prepared under the conditions of 0.92 mol·L-1 concentration of NaOH, less than 85% filling ratio, 110°C for 6 h with bauxite calcined at 1040°C as starting material

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28

Lee, Win Der, and Mu Chun Wang. "Early Effect for 28nm HK/MG PMOSFETs after Post Deposition Annealing Treatment." Advanced Materials Research 910 (March 2014): 40–43. http://dx.doi.org/10.4028/www.scientific.net/amr.910.40.

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Exposing the Early effect (or called channel-length modulation effect) at deep subnano node high-k/metal gate (HK/MG) process is still beneficial to IC designers to reduce the obsession in design. This effect contributes the operating point in circuit concern and process adjustment. For the long channel device, the intercept under various gate voltages focuses on one point consistent with conventional device. However, the divergent phenomenon was observed at the short channel tested device due to the higher strain effect, causing the non-uniform electrical field distribution in channel.

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29

Pandey, Bishwajeet, Vandana Thind, Simran Kaur Sandhu, Tamanna Walia, and Sumit Sharma. "SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA." International Journal of Security and Its Applications 9, no. 7 (2015): 267–74. http://dx.doi.org/10.14257/ijsia.2015.9.7.23.

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30

Zhao, J., X. Song, L. Zhou, et al. "Ultra Low-k Damage Control and k Recovery for 28nm RC Improvement." ECS Transactions 52, no. 1 (2013): 607–12. http://dx.doi.org/10.1149/05201.0607ecst.

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31

Bazizi, E. M., A. Zaka, G. Dilliway, et al. "Investigation of Embedded SiGe Source/Drain for 28nm HKMG PFET Performance Enhancement." ECS Transactions 53, no. 3 (2013): 27–32. http://dx.doi.org/10.1149/05303.0027ecst.

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32

Zu, Y., C. Liu, S. J. Zhang, and Q. Wu. "28nm Overlay Control Improvement By Wafer Quality Enhancement and Mask Registration Control." ECS Transactions 60, no. 1 (2014): 179–85. http://dx.doi.org/10.1149/06001.0179ecst.

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33

Shen, M., Y. L. Zu, Q. Shu, Q. Wu, and J. Liu. "Sub-Resolution Assist Features Challenge and Solution in 28nm Active Area Lithography." ECS Transactions 60, no. 1 (2014): 257–62. http://dx.doi.org/10.1149/06001.0257ecst.

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34

Zhang, Bin, Yang Hui Xiang, Hao Deng, Shibi Guo, and Beichao Zhang. "A High-Quality Spacer Oxide Formation for 28nm Technology Node and Beyond." ECS Transactions 44, no. 1 (2019): 407–10. http://dx.doi.org/10.1149/1.3694347.

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35

Litty, Antoine, Sylvie Ortolland, Dominique Golanski, and Sorin Cristoloveanu. "Dual Ground Plane EDMOS in 28nm FDSOI for 5V power management applications." Solid-State Electronics 113 (November 2015): 42–48. http://dx.doi.org/10.1016/j.sse.2015.05.011.

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36

Ramon, Hannes, Xin Yin, Johan Bauwelinck, et al. "Low-Power 56Gb/s NRZ Microring Modulator Driver in 28nm FDSOI CMOS." IEEE Photonics Technology Letters 30, no. 5 (2018): 467–70. http://dx.doi.org/10.1109/lpt.2018.2799004.

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37

Bravaix, A., F. Cacho, X. Federspiel, C. Ndiaye, S. Mhira, and V. Huard. "Potentiality of healing techniques in hot-carrier damaged 28nm FDSOI CMOS nodes." Microelectronics Reliability 64 (September 2016): 163–67. http://dx.doi.org/10.1016/j.microrel.2016.07.092.

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38

Madhok, Shivani, Navdeep Singh, Furqan Fazili, et al. "SSTL IO Standard Based Energy Efficient Digital Clock Design on 28nm FPGA." International Journal of Control and Automation 8, no. 6 (2015): 35–42. http://dx.doi.org/10.14257/ijca.2015.8.6.05.

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39

Madhok, Shivani, Navdeep Singh, Jasleen Kaur, Khyati Nanda, Sweety Dabas, and Minal Dhankar. "HSTL IO Standard Based Energy Efficient FIR Filter Design on 28nm FPGA." International Journal of Control and Automation 8, no. 7 (2015): 47–54. http://dx.doi.org/10.14257/ijca.2015.8.7.05.

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40

Gupta, Daizy, Devanshi Mahajan, Bishwajeet Pandey, Amanpreet Kaur, Amit Yadav, and Apoorv Verma. "High Performance Energy Efficient Different Counters Design and Implementation on 28nm FPGA." International Journal of Control and Automation 9, no. 9 (2016): 151–62. http://dx.doi.org/10.14257/ijca.2016.9.9.15.

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41

Zhang, Hui, Dawei Dong, Haijun Wang, et al. "A 14-bit 2.6GS/s RF sampling pipelined ADC in 28nm CMOS." Microelectronics Journal 164 (October 2025): 106795. https://doi.org/10.1016/j.mejo.2025.106795.

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42

Andrieu, François. "(Invited) Advanced Non-Volatile-Memory Embedded with CMOS: Performance and Challenges." ECS Meeting Abstracts MA2025-01, no. 36 (2025): 1729. https://doi.org/10.1149/ma2025-01361729mtgabs.

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The microcontroller (MCU) market is progressively adopting alternatives to the NOR Flash as the embedded technology solutions below the 28nm node. Foundries already propose Magnetic Random Access Memory (MRAM) or oxide-based Resistive RAM (ReRAM) that are integrated in the Back-End-Of-the-Line (BEOL) above CMOS from 22nm node down to 12nm [1], [2], [3], [4], [5]. Another company offers the Phase-Change-Memory (PCM) as the resistive element at the 28nm and 18nm [6], [7]. The physics behind the switching mechanisms of these devices is different and so their comparative advantages/drawbacks. In t

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43

Kwon, Woon-Seong, Myongseob Kim, Jonathan Chang, et al. "Enabling a Manufacturable 3D Technologies and Ecosystem using 28nm FPGA with Stack Silicon Interconnect Technology." International Symposium on Microelectronics 2013, no. 1 (2013): 000217–22. http://dx.doi.org/10.4071/isom-2013-tp11.

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Technology challenges and solutions in the development and manufacturing of Stacked Silicon Interconnect (SSI) Technology have been investigated with the established foundry and OSAT ecosystem. Key enabling technologies, such as TSV processing, interposer backside manufacturing yield enhancement, new stacking technology, interposer warpage control, micro-bump (μ-bump) processes and joining, that comprise the building blocks for SSI technology were developed. Xilinx 28nm FPGA with stacked silicon interconnect technology (SSIT) platform is used to develop and optimize the seamless integration of

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44

Wartenberg, Philipp, Andreas Fritscher, Bernd Richter, et al. "3‐4: Invited Paper: A 2.5µm Dot Pitch 0.18” OLED Microdisplay on 28nm CMOS Backplane." SID Symposium Digest of Technical Papers 54, no. 1 (2023): 13–16. http://dx.doi.org/10.1002/sdtp.16475.

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This paper reports on the most recent results of a 2.5um dot pitch 0.18” OLED microdisplay which has been realized in a 28nm CMOS backplane. It proves the general feasibility of small‐node CMOS technologies for microdisplays enabling the integration of far more functionality in the backplane. This has been successfully demonstrated by integrating a complete frame buffer in the backplane which comes with substantial benefits in terms of driving the system from a low‐bandwidth data source. This results in significant power savings and smaller sized systems which improves ergonomics which is anot

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45

Han, Yuanyuan, Tongde Li, Xu Cheng, et al. "Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 7 (2021): 2962–75. http://dx.doi.org/10.1109/tcsi.2021.3074699.

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46

Broussous, Lucile, Remy Fabre, Thomas Massin, Hiwadezu Ishikawa, Fabrice Buisine, and Alain Lamaury. "BEOL Post-Etch Clean Robustness Improvement with Ultra-Diluted Hf for 28nm Node." Solid State Phenomena 282 (August 2018): 244–49. http://dx.doi.org/10.4028/www.scientific.net/ssp.282.244.

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For 28 nm and beyond, severe specifications in terms of dimensions and materials integrity still drive further cleaning process improvements. As the global “HF budget” drastically decreases with interconnections dimensions, HF solution dilution and process time both decreased stepwise. However, very short recipes with process time shorter than 15s start to suffer from lack of robustness, in particular for the monitoring of inline parameters such as flow-rates and temperature. In this paper, we highlighted that a first matching of silicon oxide consumption was usefull to select temperature and

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47

Shu, Q., Q. Wu, Y. Zu, et al. "Study Of Gate Critical Dimension Uniformity (CDU) Budget and Improvement at 28nm Node." ECS Transactions 52, no. 1 (2013): 193–98. http://dx.doi.org/10.1149/05201.0193ecst.

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48

Hsuan, T. C., Y. C. Hu, M. C. Hsu, et al. "Advanced Spectroscopic Ellipsometry Application for Multi-Layers SiGe at 28nm Node and Beyond." ECS Transactions 58, no. 7 (2013): 137–44. http://dx.doi.org/10.1149/05807.0137ecst.

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49

Madhok, Shivani, Inderpreet Kaur, Vanshaj Taxali, Vandana Thind, Sweety Dabas, and Tushar Madhok. "LVCMOS Based Energy Efficient Sindhi Unicode Reader for Natural Processing on 28nm FPGA." International Journal of u- and e-Service, Science and Technology 8, no. 8 (2015): 207–14. http://dx.doi.org/10.14257/ijunesst.2015.8.8.21.

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50

Hsien, Y. H., H. K. Hsu, T. C. Tsai, et al. "Process development of high-k metal gate aluminum CMP at 28nm technology node." Microelectronic Engineering 92 (April 2012): 19–23. http://dx.doi.org/10.1016/j.mee.2011.04.013.

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