Relevant bibliographies by topics / 3-prescaler

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic '3-prescaler'

Author: Grafiati
Published: 4 June 2021
Last updated: 14 February 2022

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Journal articles on the topic "3-prescaler"

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Li, Xiaoran, Jian Gao, Zhiming Chen, and Xinghua Wang. "High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler." Electronics 9, no. 5 (2020): 725. http://dx.doi.org/10.3390/electronics9050725.

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This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers.
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Wan, Meilin, Zhenzhen Zhang, Wang Liao, Kui Dai, and Xuecheng Zou. "A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks." Journal of Circuits, Systems and Computers 24, no. 07 (2015): 1550109. http://dx.doi.org/10.1142/s0218126615501091.

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A dual-modulus prescaler (divide-by-2/3) using complementary clocking NMOS-like blocks is presented in this paper. The prescaler can work properly for both differential and single phase input clocks. For differential input clocks, the prescaler achieves not only high operating frequency but also low power consumption since it consists of only five NMOS-like blocks. For single phase input clock, the operating frequency range is further expanded by utilizing a complementary clocks generator. Simulation results show that, in 180-nm standard CMOS technology, the proposed prescaler achieves operating frequency range of 1.7–9.0 GHz for differential input clocks and 0.5–10.2 GHz for single phase input clock. And the maximum power consumption from 1.8 V power supply is 0.92 mW and 1.32 mW for differential and single phase input clocks respectively.
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Shen, Tianchen, Jiabing Liu, Chunyi Song, and Zhiwei Xu. "A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs." Electronics 8, no. 5 (2019): 589. http://dx.doi.org/10.3390/electronics8050589.

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A high-speed, low-power divide-by-3/4 prescaler based on an extended true single-phase clock D-flip flop (E-TSPC DFF) is presented. We added two more transistors and a mode control signal to the conventional E-TSPC based divide-by-4 divider to achieve the function of the divide-by-3/4 dual modulus frequency divider. The designed divide-by-3/4 achieved higher speed and lower power operation with mode control compared with the conventional ones. The prescaler was comprised of sixteen transistors and integrates an inverter in the second DFF to provide output directly. The power consumption was minimized due to the reduced number of stages and transistors. In addition, the prescaler operating speed was also improved due to a reduced critical path. We compared the simulation results with conventional E-TSPC based divide-by-3/4 dividers in the same process, where the figure-of-merit (FoM) of the proposed divider was 17.4–75.5% better than conventional ones. We have also fabricated the prescaler in a 40 nm complementary metal oxide semiconductor (CMOS) process. The measured highest operating frequency was 9 GHz with 0.303 mW power consumption under 1.35 V power supply, which agrees with the simulation well. The measurement results demonstrate that the proposed divider achieves high-speed and low-power operation.
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Mizuno, M., H. Suzuki, M. Ogawa, M. Sato, and H. Ichikawa. "A 3-mW 1.0-GHz silicon-ECL dual-modulus prescaler IC." IEEE Journal of Solid-State Circuits 27, no. 12 (1992): 1794–98. http://dx.doi.org/10.1109/4.173107.

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Wu, Jianhui, Zixuan Wang, Xincun Ji, and Cheng Huang. "A low-power high-speed true single phase clock divide-by-2/3 prescaler." IEICE Electronics Express 10, no. 2 (2013): 20120913. http://dx.doi.org/10.1587/elex.10.20120913.

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Jiang, Wenjian, Fengqi Yu, and Qinjin Huang. "A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler." IEICE Electronics Express 14, no. 1 (2017): 20160446. http://dx.doi.org/10.1587/elex.13.20160446.

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Krishna, M. V., Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, and Wei Meng Lim. "Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 1 (2010): 72–82. http://dx.doi.org/10.1109/tcsi.2009.2016183.

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Yu, X. P., Z. H. Lu, W. M. Lim, and K. S. Yeo. "0.6mW 6.3 GHz 40nm CMOS divide‐by‐2/3 prescaler using heterodyne phase‐locking technique." Electronics Letters 49, no. 7 (2013): 471–72. http://dx.doi.org/10.1049/el.2013.0584.

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Shih, Yi-Shing, and Jenn-Hwan Tarng. "A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler." IEICE Electronics Express 3, no. 12 (2006): 276–80. http://dx.doi.org/10.1587/elex.3.276.

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Craninckx, J., та M. S. J. Steyaert. "A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS". IEEE Journal of Solid-State Circuits 31, № 7 (1996): 890–97. http://dx.doi.org/10.1109/4.508200.

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Dissertations / Theses on the topic "3-prescaler"

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Veale, Gerhardus Ignatius Potgieter. "Low phase noise 2 GHz Fractional-N CMOS synthesizer IC." Diss., 2010. http://hdl.handle.net/2263/27921.

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Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2.<br>Dissertation (MEng)--University of Pretoria, 2010.<br>Electrical, Electronic and Computer Engineering<br>unrestricted
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Book chapters on the topic "3-prescaler"

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Lu, Shibin, Ying Meng, Feifei Wang, and Xianwei Jiang. "A Low-Power Dual-Modulus Prescaler in 90nm CMOS Technology." In Advances in Mechanical and Electronic Engineering. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31528-2_27.

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Conference papers on the topic "3-prescaler"

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Wenjian Jiang and Fengqi Yu. "A novel high-speed divide-by-3/4 prescaler." In 2016 IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC). IEEE, 2016. http://dx.doi.org/10.1109/imcec.2016.7867258.

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Yan, Shilin, Song Jia, Wenyi Tang, Jiyu Chen, Ziyi Wang, and Weiting Li. "A 16/17 prescaler based on novel TSPC 2/3 devider scheme." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021575.

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Xuan Jiahui, Wang Zhigong, Tang Lu, and Xu Jian. "A 3-GHz dual-modulus prescaler based on improved master-slave DFF." In 2010 12th IEEE International Conference on Communication Technology (ICCT). IEEE, 2010. http://dx.doi.org/10.1109/icct.2010.5688989.

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Tooprakai, Siraphop, Sompong Wisetphanichkij, and Apirak Tudsorn. "A 1.1-V low power true single-phase clock 2/3 prescaler." In 2017 International Electrical Engineering Congress (iEECON). IEEE, 2017. http://dx.doi.org/10.1109/ieecon.2017.8075903.

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Ji, Xincun, Xu Yan, Guo Fengqi, and Yufeng Guo. "High speed low power true single phase clock CMOS divide by 2/3 prescaler." In 2017 International Conference on Circuits, Devices and Systems (ICCDS). IEEE, 2017. http://dx.doi.org/10.1109/iccds.2017.8120455.

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Krishna, M. Vamshi, M. A. Do, C. C. Boon, K. S. Yeo, and Wei Meng Lim. "A 1.8-V 6.5-GHz low power wide band single-phase clock CMOS 2/3 prescaler." In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2010. http://dx.doi.org/10.1109/mwscas.2010.5548580.

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Lawang, Itthiphat, Apirak Tudsorn, and Siraphop Tooprakai. "1V High Speed E-TSPC 2/3 Prescalers." In 2019 5th International conference on Engineering, Applied Sciences and Technology (ICEAST). IEEE, 2019. http://dx.doi.org/10.1109/iceast.2019.8802598.

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Tooprakai, Siraphop, and Apirak Tudsorn. "A 1.2 V low-power true single-phase clock CMOS 2/3 prescalers." In 2014 International Conference on Information Science, Electronics and Electrical Engineering (ISEEE). IEEE, 2014. http://dx.doi.org/10.1109/infoseee.2014.6946210.

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Hirao, T., T. Ikeda, and N. Katoh. "A 2.1-GHz 56-mW Two-Modulus Prescaler IC Using Salicide Base Contact Technology." In 1985 Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1985. http://dx.doi.org/10.7567/ssdm.1985.b-4-3.

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