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Journal articles on the topic '32 Bit CSLA'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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2

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

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In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

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3

Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (2018): 369. http://dx.doi.org/10.3390/electronics7120369.

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Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing bi

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4

Yogayata, Shrivastava, Verma Tarun, and Jain Rita. "Design and Implementation of Low Power High Speed 32-Bit HCSA." International Journal of VLSI and Embedded Systems 5 (April 17, 2014): 893–98. https://doi.org/10.5281/zenodo.33236.

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In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing

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5

Aditya, Srinivas, and Ramesh K.B. "Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder." Journal of Optoelectronics and Communication 6, no. 3 (2024): 18–26. https://doi.org/10.5281/zenodo.12720733.

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<em>Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced

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6

Kamna, nayak, and Patra K.Pitambar. "Study of High Speed 32-Bit Data Processing Using CSLA." Association for International Journal in Computer Science & Electronics 4, no. 3 (2015): 1–9. https://doi.org/10.5281/zenodo.33244.

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Modern applications demand extremely low power and fast speed in computer architectures for battery-operated devices like Laptop and others. In this work, the main focus is on the low power consumption and provides high speed to the processors. Low-power and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The selection behind the carry select adder is that it is very much efficient in terms of delay. The main focus in this work is to improve the speed of the 32-bit processor and in this case

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7

PinnikaVenkateswarlu and Kalpana Ragutla. "An Efficient SQRT Architecture of Carry Select Adder Design by HA and Common Boolean Logic." SSRG International Journal of Electronics and Communication Engineering 1, no. 8 (2014): 36–41. https://doi.org/10.5281/zenodo.33082.

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As we are aware that carry select adder is the fastest one amongdata processing element, on the other hand due to having pairs of ripple carry adder structure traditional carry select adder consumes more area. So proposed scheme is to developa low power and low area half adder based (CSLA) using simple using common Boolean logic (CBL), where it employs one half adders to perform the summation operation for the common Boolean logic (CBL) and carry zero respectively. Half adder and CBL have to be designed where half adder requires one XOR gate, one AND gate where CBL requires only one NOT as wel

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8

Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic." Iraqi Journal for Electrical and Electronic Engineering 21, no. 2 (2025): 88–98. https://doi.org/10.37917/ijeee.21.2.9.

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Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode

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9

Malti, Aryanan, and Singh Chauhan Jaikaran. "Design Area-Efficient and high speed 32bit CSLA." International Journal of advancement in electronics and computer engineering 4, no. 8 (2015): 555–59. https://doi.org/10.5281/zenodo.45401.

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Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

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10

Priya, Meshram, Mahendra Mithilesh, and Jawarkar Parag. "Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder." International Journal for Research in Emerging Science and Technology 2, no. 5 (2015): 96–99. https://doi.org/10.5281/zenodo.33092.

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In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based o

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11

Suguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.

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In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL

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12

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

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The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry t

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13

Malti, Aryayan, and Singh Chauhan Jaikaran. "Efficient Method for Area-Efficient 32bit CSLA." International Journal of Emerging Technology and Advanced Engineering 6, no. 2 (2016): 81–85. https://doi.org/10.5281/zenodo.46811.

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Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

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14

D.Gandhe, Sumeet, and Venkatesh Giripunje. "FPGA Implementation of Area Efficient and Delay Optimized 32-Bit SQRT CSLA with First Addition Logic." International Journal of Computer Applications 95, no. 22 (2014): 43–49. http://dx.doi.org/10.5120/16730-7024.

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15

Balasubramanian, Padmanabhan, Douglas Maskell, and Nikos Mastorakis. "Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic." Electronics 7, no. 10 (2018): 243. http://dx.doi.org/10.3390/electronics7100243.

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Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-pha

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16

Mendez, Tanya, Subramanya G. Nayak, Vasanth Kumar P., Vijay S. R., and Vishnumurthy Kedlaya K. "Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending." Electronics 11, no. 15 (2022): 2461. http://dx.doi.org/10.3390/electronics11152461.

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The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain op

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17

Jayakrishna, P., P. Sravani, R. Sakshitha Reddy, and S. Ashritha. "Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 6 (2023): 1353–61. http://dx.doi.org/10.22214/ijraset.2023.53550.

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Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the thre

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18

Ravikumar, N., M. Vishwanath, and B. Durga Malleswara Reddy. "An Area Efficient 32-bit Carry-select Adder for Low Power Applications." International Journal of Computer and Communication Technology, April 2016, 111–14. http://dx.doi.org/10.47893/ijcct.2016.1349.

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CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum [1]. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input Cin=0 and cin=1, then the final sum and carry are selected by the multiplexers (mux). The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the

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19

"Enhanced 32-Bit Adder Implementation using Different Configurations of Adders." International Journal of Recent Technology and Engineering 8, no. 4 (2019): 12606–11. http://dx.doi.org/10.35940/ijrte.d9771.118419.

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Adders play a essential role with in the digital signal process systems. The 32-bit configuration is commonly used in few computerized systems and processors. In this paper, detail study about the implementation of 32-bit adders like Ripple Carry Adder (RCA), Carry Select adder (CSLA) and Carry Increment adder (CINA) is done for various configurational full adders using VHDL. The outcomes are acquired by executing VHDL in Xilinx ISE 14.5 with speed grade -5 of Spartan 3E family device.

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20

Penchalaiah, Usthulamuri, and V. G. Siva Kumar. "Design and Implementation of Low Power and Area Efficient Architecture for High Performance ALU." Parallel Processing Letters, October 19, 2021. http://dx.doi.org/10.1142/s0129626421500171.

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Digital Signal Processors (DSP) have a ubiquitous presence in almost all civil and military signal processing applications, including mission critical environments like nuclear reactors, process control etc. Arithmetic and Logic units (ALU), being the heart of any digital signal processor, play critical and decisive roles in achieving the required parameter benchmarks and the overall efficiency and robustness of the digital signal processor. State of the art research has shown successful traction with the performance requirements of critical Multiply-Accumulate (MAC) parameters, like reduced p

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21

V, Govındaraj, Ezhılazhagan CHENGUTTUVAN, and Dhanasekar SUBRAMANIYAM. "Design of Power and Area Efficient Carry Skip Adder and FIR filter Implementation." El-Cezeri Fen ve Mühendislik Dergisi, December 7, 2022. http://dx.doi.org/10.31202/ecjse.1162711.

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Adders are used in processing units such as Arithmetic and Logic Units (ALUs) as an essential building block, and in many blocks of microprocessor chips critical path, adders occupy an important place. Hence reducing power, area and increasing the speed of adders are significantly important. This paper proposes a modified structure of Carry Skip Adder (CSKA) with a reduction in consumption of power and area without affecting the speed when compared with the conventional adder structures. In order to get better effectiveness of the modified CSKA by including concatenation, incrementation scheme

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22

Prasanna, Mishra. "An Efficient Design of FSM Based 32-Bit Unsigned Pipelined Multiplier Using Verilog HDL." An Efficient Design of FSM Based 32-Bit Unsigned Pipelined Multiplier Using Verilog HDL 11, no. 1 (2023). https://doi.org/10.5281/zenodo.8031578.

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This paper shows a modification to FSM based 32-bit pipelined multiplier. It uses carry look ahead adders (CLA’s) and Carry Select Adders (CSA) in place of ripple carry adders (RCA’s) in 32-bit FSM based pipelined multiplier for reducing the carry propagation delay. The proposed hardware design is based on shift and add algorithm for multiplication process.

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23

E.pramila, T.mangaiyarthilagam, and Nranjana CP. "An Area Energy-Efficient VLSI Architecture using Hybrid Wide-Operand adder." international journal of engineering technology and management sciences, July 28, 2022, 331–36. http://dx.doi.org/10.46647/ijetms.2022.v06i04.0054.

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Consumer electronics markets have raised demand for high-speed, low- power adders with big operands for use in new portable systems. Traditional fast adder architectures, such as parallelprefix adders, consume a lot of power when I have a lot of operands. One of the most promising ways for achieving a trade-off between delay and power consumption for the addition of big operands is the hybrid design. This reduces the area of the summation blocks at the significant positions without sacrificing speed. Furthermore, My provides a new hybrid adder architecture for large operands, based on the conc

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