Relevant bibliographies by topics / 32-bit processor

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic '32-bit processor'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "32-bit processor"

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Phanindra, K. "32-Bit MIPS RISC Processor." International Journal for Research in Applied Science and Engineering Technology V, no. X (2017): 1119–23. http://dx.doi.org/10.22214/ijraset.2017.10162.

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Hayes, W. P., R. N. Kershaw, L. E. Bays, et al. "A 32-bit VLSI digital signal processor." IEEE Journal of Solid-State Circuits 20, no. 5 (1985): 998–1004. http://dx.doi.org/10.1109/jssc.1985.1052427.

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Tanaka, Shigeya, Takashi Hotta, Masahiro Iwamura, et al. "A 70-MHz, 32-bit BiCMOS processor." Electronics and Communications in Japan (Part II: Electronics) 74, no. 6 (1991): 44–52. http://dx.doi.org/10.1002/ecjb.4420740605.

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Huang, Sheng-Chieh, Liang-Gee Chen, and Thou-Ho Chen. "A 32-bit logarithmic number system processor." Journal of VLSI signal processing systems for signal, image and video technology 14, no. 3 (1996): 311–19. http://dx.doi.org/10.1007/bf00929624.

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Kim, Ji-Hoon, Jong-Yeol Lee, and Ando Ki. "Core-A: A 32-bit Synthesizable Processor Core." IEIE Transactions on Smart Processing and Computing 4, no. 2 (2015): 83–88. http://dx.doi.org/10.5573/ieiespc.2015.4.2.083.

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Voevodin, V. P., V. N. Govorun, A. M. Davidenko, et al. "The 780/E 32-bit specialised processor-emulator." Computer Physics Communications 57, no. 1-3 (1989): 532–35. http://dx.doi.org/10.1016/0010-4655(89)90281-6.

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Matsushita, Y., T. Jibiki, H. Takahashi, and T. Takamizawa. "A 32/24 bit digital audio signal processor." IEEE Transactions on Consumer Electronics 35, no. 4 (1989): 785–92. http://dx.doi.org/10.1109/30.106896.

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Ashith, M. B. "1024-Bit/2048-Bit RSA Implementation on 32-Bit Processor for Public Key Cryptography." IETE Technical Review 19, no. 4 (2002): 203–5. http://dx.doi.org/10.1080/02564602.2002.11417032.

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Lee, Kwang-Min, and Sungkyung Park. "Low-Gate-Count 32-Bit 2/3-Stage Pipelined Processor Design." Journal of the Institute of Electronics and Information Engineers 53, no. 4 (2016): 59–67. http://dx.doi.org/10.5573/ieie.2016.53.4.059.

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Burud, Mr Anand S., and Dr Pradip C. Bhaskar. "Processor Design Using 32 Bit Single Precision Floating Point Unit." International Journal of Trend in Scientific Research and Development Volume-2, Issue-4 (2018): 198–202. http://dx.doi.org/10.31142/ijtsrd12912.

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Dissertations / Theses on the topic "32-bit processor"

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Maamar, Ali Hussein. "A 32-bit self-checking RISC processor using Dong's Code." Thesis, University of Newcastle Upon Tyne, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.285335.

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Jönsson, Patricia. "Evaluation in which context a 32-bit, rather than an 8-bit processor may be appropriate to use, based on power consumption." Thesis, Malmö högskola, Fakulteten för teknik och samhälle (TS), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20846.

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Uttrycket Internet of Things växer sig större och större och världen är på väg att ha 50miljarder uppkopplade enheter till 2020. IoT-enheter är beroende av att ha en låg effektförbrukningoch därför är en processor med låg effektförbrukning viktigt att ha. Denna studieutför tester på två strömsnåla processorer för att komma fram till vilken processor somär mest lämplig till vilken IoT-produkt. Testningen utgick från tre applikationer som i sintur baseras på verkliga IoT-situationer. De tre applikationerna har olika intesitetsnivåer. Iden första applikationen arbetar processorerna inte särskilt
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Fang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor." Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2021<br>Cataloged from the official PDF of thesis.<br>Includes bibliographical references (pages 139-140).<br>We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and
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Su, Chien-Chang, and 蘇健彰. "Integrated Software Development Environment for a 32-bit / 16-bit Processor Family." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/3gpzv5.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>95<br>To the general purpose microprocessors, we often need to change microprocessors’ hardware architecture because of customized purpose. But already existing application program is incompatible to the new hardware architecture, and increase the product’s development period. In this thesis, we discuss the modification of two kinds of hardware architecture, include new instruction set extension and change the size of datapath to deal with specific application. To the former, our laboratory develop a 32-bit microprocessor SYS32-TM, increase MME instruction set to
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Darwish, Mohammad Mostafa. "Formal verification of a 32-bit pipelined RISC processor." Thesis, 1994. http://hdl.handle.net/2429/5260.

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Designing a microprocessor is a significant undertaking. Modern RISC processors are no exception. Although RISC architectures originally were intended to be simpler than CISC processors, modern RISC processors are often very complex, partially due to the prominent use of pipelining. As a result, verifying the correctness of a RISC design is an extremely difficult task. Thus, it has become of great importance to find more efficient design verification techniques than traditional simulation. The objective of this thesis is to show that symbolic trajectory evaluation is such a technique. F
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Li, Wen-jie, and 李文傑. "A Scalable RSA Cryptographic Processor with 32-Bit Modular Multiplier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/26789610187671920567.

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碩士<br>國立高雄大學<br>電機工程學系碩士班<br>94<br>With the popularity of the portable electronic devices, the chip area and power consumption must be reduced, and because of this, we propose a scalable RSA cryptosystem chip, which is implemented with a 32-bit core. Our design provides the trade-off between security and computation time. If the security is more important, we can choose longer key to get higher security. Otherwise, the shorter key could be chosen to reduce the computation time. To realize the chip of this design, we used Cadence, Synopsys and TSMC 0.35um cell library to simulate and implement.
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XIE, REN-FA, and 謝仁發. "A 32-bit hybrid floating-point binary and logarithmic number system processor." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/10886867769518457164.

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Chen, Chien-Chih, and 陳建志. "The Linux Porting and Integration Verification of An Academic 32-bit Processor." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/32566192674843841485.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>101<br>For improving the performance and application of microprocessor, it is necessary to integrate pipelined core, exception control unit, cache unit and memory management unit (MMU). The operating system is an effective way for microprocessor integration verification. However, it is not a feasible debugging methodology to detect the exact design bug while operating system booting crash. We found the main execution features of operating system are the data transfer and exception handling. We propose an integration verification methodology based on these execution
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Peng, Yi Xiong, and 彭義雄. "ASIC Design and Implementation of 32-Bit LNS Addition and Subtraction Processor." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/17662755757560652760.

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Hsin, Wei-Kuo, and 辛威虢. "Efficient MP3 Decoder System using a 32-bit Low-Power Embedded Processor Core." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/61855656677322982581.

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碩士<br>國立交通大學<br>電子工程系所<br>97<br>This thesis presents the research result of an efficient MP3 decoder system using a 32-bit low-power embedded processor core, named ACARM9 (ACademic ARM9). The ISA (Instruction Set Architecture) of ACARM9 adopts the ARM V5E architecture but owns more efficient multiplication instructions. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the code of high level programming language (C, C++) written by users to the assembly code, and then can assemble the assembly code to the low level machine code for ACARM9 use. It indicate
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Books on the topic "32-bit processor"

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Corporation, Intel. 16-/32-bit embedded processor handbook. Intel Corporation, 1990.

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(Europe), NEC Electronics. 32-bit digital signal processors data book. NEC Electronics, 1993.

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Smith, Simon L. Exp the Scientific Word Processor Version 5.0: 32-Bit Application for Windows 95 and Windows Nt. Brooks/Cole Pub Co, 1997.

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Intel. 16-/32-Bit Embedded Processors. Intel Corporation (CA), 1991.

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Book chapters on the topic "32-bit processor"

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Civera, Pierluigi, Dante Del Corso, Gianluca Piccinini, and Maurizio Zamboni. "A 32 Bit Processor for Compiled Prolog." In The Kluwer International Series in Engineering and Computer Science. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4613-1619-0_2.

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Bit, Abhishek. "64-Bit Custom Math ISA in Configurable 32-Bit RISC Processor." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1420-3_60.

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Kim, Hyun-Gyu, and Hyeong-Cheol Oh. "A Low-Power DSP-Enhanced 32-Bit EISC Processor." In High Performance Embedded Architectures and Compilers. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11587514_20.

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Patra, Sumit, Sunil Kumar, Swati Verma, and Arvind Kumar. "Design and Implementation of 32-bit MIPS-Based RISC Processor." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9775-3_68.

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Mangalwedhe, Sneha, Roopa Kulkarni, and S. Y. Kulkarni. "Low Power Implementation of 32-Bit RISC Processor with Pipelining." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8234-4_27.

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Anjana, S. J., K. Padmakumar, Joji Daniel, et al. "Pre-Silicon Validation of 32-Bit Indigenous Processor for Space Applications." In Transactions on Computational Science and Computational Intelligence. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-49500-8_17.

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Le-Huu, Khoi-Nguyen, Thanh T. Vu, Diem N. Ho, and Anh-Vu Dinh-Duc. "Towards a VLIW Architecture for the 32-Bit Digital Signal Processor Core." In Lecture Notes in Electrical Engineering. Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-642-41674-3_109.

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Shashidar, R., R. Santhosh Kumar, A. M. MahalingaSwamy, and M. Roopa. "FPGA Implementation of Low Power Pipelined 32-Bit RISC Processor Using Clock Gating." In Proceedings of the International Conference on Data Engineering and Communication Technology. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1678-3_74.

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Tillich, Stefan, and Johann Großschädl. "Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11894063_22.

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Tillich, Stefan, Christoph Herbst, and Stefan Mangard. "Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis." In Applied Cryptography and Network Security. Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-72738-5_10.

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Conference papers on the topic "32-bit processor"

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George, Mark, and Julie Brichacek. "Radiation hardened 32-bit processor (RH32)." In 15th International Communicatons Satellite Systems Conference and Exhibit. American Institute of Aeronautics and Astronautics, 1994. http://dx.doi.org/10.2514/6.1994-1104.

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Singh, Narendra Bahadur, and Prashant Singh. "Design of 32-bit real numeric processor." In 2013 International Conference on Advanced Electronic Systems (ICAES). IEEE, 2013. http://dx.doi.org/10.1109/icaes.2013.6659368.

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Kim, Ji-Hoon, Duk-Hyun You, Ki-Seok Kwon, Eun-Joo Bae, WonHee Son, and In-Cheol Park. "Design of high-performance 32-bit embedded processor." In 2008 International SoC Design Conference (ISOCC). IEEE, 2008. http://dx.doi.org/10.1109/socdc.2008.4815746.

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Oh, Hyun Woo, Kwon Neung Cho, and Seung Eun Lee. "Design of 32-bit Processor for Embedded Systems." In 2020 International SoC Design Conference (ISOCC). IEEE, 2020. http://dx.doi.org/10.1109/isocc50952.2020.9332944.

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Kubde, R. M., D. B. Bhoyar, and R. S. Khedikar. "Design of 32 bit (MIPS) RISC PROCESSOR using FPGA." In ICWET '10: International Conference and Workshop on Emerging Trends in Technology. ACM, 2010. http://dx.doi.org/10.1145/1741906.1742123.

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Aadarsh, Aadarsh, Aditya Kumar, Aditya Yadav, and P. C. Joshi. "Design and Power Analysis of 32-Bit Pipelined Processor." In 2021 International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE). IEEE, 2021. http://dx.doi.org/10.1109/icacite51222.2021.9404622.

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Bhargava, Akansha, and R. S. Ochawar. "Biometric Access Control Implementation Using 32 bit Arm Cortex Processor." In 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies (ICESC). IEEE, 2014. http://dx.doi.org/10.1109/icesc.2014.98.

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Bink, Arjan, and Richard York. "ARM996HS™ the first licensable, clockless 32-bit processor core." In 2006 IEEE Hot Chips 18 Symposium (HCS). IEEE, 2006. http://dx.doi.org/10.1109/hotchips.2006.7477862.

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Ardalan, S., and A. Adibi. "Design, simulation and synthesis of a 32-bit math-processor." In 48th Midwest Symposium on Circuits and Systems, 2005. IEEE, 2005. http://dx.doi.org/10.1109/mwscas.2005.1594390.

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Bertoni, Guido, Luca Breveglieri, Farina Roberto, and Francesco Regazzoni. "Speeding Up AES By Extending a 32 bit Processor Instruction Set." In IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06). IEEE, 2006. http://dx.doi.org/10.1109/asap.2006.62.

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Reports on the topic "32-bit processor"

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Siy, P. F., J. T. Carter, L. R. D'Addario, and D. A. Loeber. Dose Rate and Total Dose Radiation Testing of the Texas Instruments TMS320C30 32-Bit Floating Point Digital Signal Processor. Defense Technical Information Center, 1991. http://dx.doi.org/10.21236/ada239767.

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