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Relevant bibliographies by topics / 32-bit processor / Dissertations / Theses

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Dissertations / Theses on the topic '32-bit processor'

Author: Grafiati

Published: 4 June 2021

Last updated: 4 February 2022

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1

Maamar, Ali Hussein. "A 32-bit self-checking RISC processor using Dong's Code." Thesis, University of Newcastle Upon Tyne, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.285335.

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2

Jönsson, Patricia. "Evaluation in which context a 32-bit, rather than an 8-bit processor may be appropriate to use, based on power consumption." Thesis, Malmö högskola, Fakulteten för teknik och samhälle (TS), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20846.

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Uttrycket Internet of Things växer sig större och större och världen är på väg att ha 50miljarder uppkopplade enheter till 2020. IoT-enheter är beroende av att ha en låg effektförbrukningoch därför är en processor med låg effektförbrukning viktigt att ha. Denna studieutför tester på två strömsnåla processorer för att komma fram till vilken processor somär mest lämplig till vilken IoT-produkt. Testningen utgick från tre applikationer som i sintur baseras på verkliga IoT-situationer. De tre applikationerna har olika intesitetsnivåer. Iden första applikationen arbetar processorerna inte särskilt

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3

Fang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor." Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2021<br>Cataloged from the official PDF of thesis.<br>Includes bibliographical references (pages 139-140).<br>We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and

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4

Su, Chien-Chang, and 蘇健彰. "Integrated Software Development Environment for a 32-bit / 16-bit Processor Family." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/3gpzv5.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>95<br>To the general purpose microprocessors, we often need to change microprocessors’ hardware architecture because of customized purpose. But already existing application program is incompatible to the new hardware architecture, and increase the product’s development period. In this thesis, we discuss the modification of two kinds of hardware architecture, include new instruction set extension and change the size of datapath to deal with specific application. To the former, our laboratory develop a 32-bit microprocessor SYS32-TM, increase MME instruction set to

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5

Darwish, Mohammad Mostafa. "Formal verification of a 32-bit pipelined RISC processor." Thesis, 1994. http://hdl.handle.net/2429/5260.

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Designing a microprocessor is a significant undertaking. Modern RISC processors are no exception. Although RISC architectures originally were intended to be simpler than CISC processors, modern RISC processors are often very complex, partially due to the prominent use of pipelining. As a result, verifying the correctness of a RISC design is an extremely difficult task. Thus, it has become of great importance to find more efficient design verification techniques than traditional simulation. The objective of this thesis is to show that symbolic trajectory evaluation is such a technique. F

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6

Li, Wen-jie, and 李文傑. "A Scalable RSA Cryptographic Processor with 32-Bit Modular Multiplier." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/26789610187671920567.

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碩士<br>國立高雄大學<br>電機工程學系碩士班<br>94<br>With the popularity of the portable electronic devices, the chip area and power consumption must be reduced, and because of this, we propose a scalable RSA cryptosystem chip, which is implemented with a 32-bit core. Our design provides the trade-off between security and computation time. If the security is more important, we can choose longer key to get higher security. Otherwise, the shorter key could be chosen to reduce the computation time. To realize the chip of this design, we used Cadence, Synopsys and TSMC 0.35um cell library to simulate and implement.

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7

XIE, REN-FA, and 謝仁發. "A 32-bit hybrid floating-point binary and logarithmic number system processor." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/10886867769518457164.

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8

Chen, Chien-Chih, and 陳建志. "The Linux Porting and Integration Verification of An Academic 32-bit Processor." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/32566192674843841485.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>101<br>For improving the performance and application of microprocessor, it is necessary to integrate pipelined core, exception control unit, cache unit and memory management unit (MMU). The operating system is an effective way for microprocessor integration verification. However, it is not a feasible debugging methodology to detect the exact design bug while operating system booting crash. We found the main execution features of operating system are the data transfer and exception handling. We propose an integration verification methodology based on these execution

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9

Peng, Yi Xiong, and 彭義雄. "ASIC Design and Implementation of 32-Bit LNS Addition and Subtraction Processor." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/17662755757560652760.

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10

Hsin, Wei-Kuo, and 辛威虢. "Efficient MP3 Decoder System using a 32-bit Low-Power Embedded Processor Core." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/61855656677322982581.

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碩士<br>國立交通大學<br>電子工程系所<br>97<br>This thesis presents the research result of an efficient MP3 decoder system using a 32-bit low-power embedded processor core, named ACARM9 (ACademic ARM9). The ISA (Instruction Set Architecture) of ACARM9 adopts the ARM V5E architecture but owns more efficient multiplication instructions. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the code of high level programming language (C, C++) written by users to the assembly code, and then can assemble the assembly code to the low level machine code for ACARM9 use. It indicate

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11

Hsu, Je-Ling, and 許哲霖. "Ultra Low-Power and High-Performance 32-Bit Embedded Processor with JPEG Decoder System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/33455761081632868123.

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碩士<br>國立交通大學<br>電子工程系所<br>96<br>This thesis presents the research result of an ultra low-power and high-performance 32-bit embedded processor with JPEG decoder system. This processor is named ACARM7 (ACademic ARM7). The ISA (Instruction Set Architecture) of ACARM7 adopts the ARM V4 architecture. Hence the ADS (ARM Develop Suite) can be directly used. ADS can first be used to compile the high level programming language (C, C++) written by users to the assembly language, and then can assemble the assemble language to the low level machine code for ACARM7 use. It indicates the high usability of A

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12

Liu, Hwang Lin, and 劉皇麟. "An Implementation and Layout of a 32-Bit Arithmetic Co- processor (with Improvement of Accuracy for Logarithmic Conversion)." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/79968939307844242470.

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碩士<br>逢甲大學<br>資訊工程研究所<br>82<br>Logarithms have long been used as a tool in mathematics to simplify the process, e.g., they reduce multiplication and division problems to addition and subtraction. In this thesis, we have worked out for the VLSI layout of the Three Partition with Hybrid ROMs strategy. The CAD package MAGIC was used to implement and simulate the VLSI layout. Now we have passed the examination of the Chip Implementation Center, and produced the chips. Finally, we initialed a n

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13

Liu, Huang Lin, and 劉皇麟. "An implementation and layout of a 32-bit arithmetic co-processor (with improvement of accuracy for logarithmic conversion)." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/02453557392387793738.

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14

Chen, Yi-Hung Edward, and 陳奕宏. "Improvement and Discussion of MFCC Algorithm on 32-bit Fixed-point Processors." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/52339443995174628395.

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碩士<br>國立清華大學<br>資訊系統與應用研究所<br>94<br>In this thesis, we investigate the possibility of porting the computation of floating-point MFCCs to fixed-point ones. In particular, we focus on the platform of 32-bit fixed-point processors. We have closely checked the scaling factors during each stage of the computation of MFCC by using a data-driven approach. These scaling factors are carefully chosen such that the highest precision is achieved with low probabilities of overflow. Moreover, we have proposed a binary-search-based table lookup such that the required table size is reduced. In summary, the pr

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15

Huang, Wu-Xian, and 黃武顯. "A Study on Improving Spoken Mandarin Assessment over 32-bit Fixed-point processors." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/64390866548487441755.

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碩士<br>國立清華大學<br>資訊工程學系<br>95<br>This thesis explores the possibility of improving the performance of our Mandarin speech assessment systems on 32-bit fix-point platform. For improving efficiency, we have proposed several methods for reduce computation, such that the response time of the system can be as short as possible without degrading its performance. For improving effectiveness, we have also proposed four score-correction rules that can be used to give a more consistent scores of speech assessment. We have implemented these methods and rules on a PMP (personal media player) based Mandarin

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