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Journal articles on the topic '32-bit processor'

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Published: 4 June 2021

Last updated: 4 February 2022

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1

Phanindra, K. "32-Bit MIPS RISC Processor." International Journal for Research in Applied Science and Engineering Technology V, no. X (October 23, 2017): 1119–23. http://dx.doi.org/10.22214/ijraset.2017.10162.

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2

Hayes, W. P., R. N. Kershaw, L. E. Bays, J. R. Boddie, E. M. Fields, R. L. Freyman, C. J. Garen, et al. "A 32-bit VLSI digital signal processor." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 998–1004. http://dx.doi.org/10.1109/jssc.1985.1052427.

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3

Tanaka, Shigeya, Takashi Hotta, Masahiro Iwamura, Tatsumi Yamauchi, Tadaaki Bandoh, Atsuo Hotta, Seiji Iwamoto, and Shigemi Adachi. "A 70-MHz, 32-bit BiCMOS processor." Electronics and Communications in Japan (Part II: Electronics) 74, no. 6 (1991): 44–52. http://dx.doi.org/10.1002/ecjb.4420740605.

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4

Huang, Sheng-Chieh, Liang-Gee Chen, and Thou-Ho Chen. "A 32-bit logarithmic number system processor." Journal of VLSI signal processing systems for signal, image and video technology 14, no. 3 (December 1996): 311–19. http://dx.doi.org/10.1007/bf00929624.

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5

Kim, Ji-Hoon, Jong-Yeol Lee, and Ando Ki. "Core-A: A 32-bit Synthesizable Processor Core." IEIE Transactions on Smart Processing and Computing 4, no. 2 (April 30, 2015): 83–88. http://dx.doi.org/10.5573/ieiespc.2015.4.2.083.

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6

Voevodin, V. P., V. N. Govorun, A. M. Davidenko, An V. Ekimov, N. S. Ivanova, V. I. Kovaltsov, Yu M. Kozyaev, et al. "The 780/E 32-bit specialised processor-emulator." Computer Physics Communications 57, no. 1-3 (December 1989): 532–35. http://dx.doi.org/10.1016/0010-4655(89)90281-6.

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7

Matsushita, Y., T. Jibiki, H. Takahashi, and T. Takamizawa. "A 32/24 bit digital audio signal processor." IEEE Transactions on Consumer Electronics 35, no. 4 (1989): 785–92. http://dx.doi.org/10.1109/30.106896.

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8

Ashith, M. B. "1024-Bit/2048-Bit RSA Implementation on 32-Bit Processor for Public Key Cryptography." IETE Technical Review 19, no. 4 (July 2002): 203–5. http://dx.doi.org/10.1080/02564602.2002.11417032.

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9

Lee, Kwang-Min, and Sungkyung Park. "Low-Gate-Count 32-Bit 2/3-Stage Pipelined Processor Design." Journal of the Institute of Electronics and Information Engineers 53, no. 4 (April 25, 2016): 59–67. http://dx.doi.org/10.5573/ieie.2016.53.4.059.

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10

Burud, Mr Anand S., and Dr Pradip C. Bhaskar. "Processor Design Using 32 Bit Single Precision Floating Point Unit." International Journal of Trend in Scientific Research and Development Volume-2, Issue-4 (June 30, 2018): 198–202. http://dx.doi.org/10.31142/ijtsrd12912.

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11

Poduel, Bikash, Prasanna Kansakar, Sujit R. Chhetri, and Shashidhar Ram Joshi. "Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL." Nepal Journal of Science and Technology 15, no. 1 (February 3, 2015): 81–88. http://dx.doi.org/10.3126/njst.v15i1.12021.

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This paper is delineating the design and implementation of high performance, synthesizable 32-bit pipelined Reduced Instruction Set Computer (RISC) Core. The design of the Harvard Architecture based 32-bit RISC Core involves design of 32-bit Data-path Unit, Control Unit, 32-bit Instruction Memory, 32-bit Data Memory, Register file with each register of size 32 bit. The processor is divided into Fetch, Decode, Execute and Write Back block in order to implement a four-stage pipeline. A 2*16 LCD is connected to the processor IO block to show the instruction execution sequence for demonstration in FPGA. The RISC Core is designed using Verilog HDL and VHDL and is tested in ISIM Simulator. The implementation of the processor is done in a Spartan 3E Starter Board using Xilinx ISE 14.7. All of the instructions incorporated with the processor have been tested successfully both in simulation and hardware implementation in FPGA.DOI: http://dx.doi.org/10.3126/njst.v15i1.12021 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 81-88

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12

Bink, Arjan, and Richard York. "ARM996HS: The First Licensable, Clockless 32-Bit Processor Core." IEEE Micro 27, no. 2 (March 2007): 58–68. http://dx.doi.org/10.1109/mm.2007.28.

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13

Benhadjyoussef, Noura, Wajih Elhadjyoussef, Mohsen Machhout, Rached Tourki, and Kholdoun Torki. "Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions." Journal of Circuits, Systems and Computers 24, no. 10 (October 25, 2015): 1550158. http://dx.doi.org/10.1142/s0218126615501583.

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Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm2 and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

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14

Niwa, A., and T. Yamada. "A 32-Bit Custom VLSI Processor for Communications Network Nodes." IEEE Journal on Selected Areas in Communications 4, no. 1 (January 1986): 192–99. http://dx.doi.org/10.1109/jsac.1986.1146288.

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15

Suzuki, K., M. Yamashina, T. Nakayama, M. Izumikawa, M. Nomura, H. Igura, H. Heiuchi, et al. "A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor." IEEE Journal of Solid-State Circuits 29, no. 12 (1994): 1464–73. http://dx.doi.org/10.1109/4.340419.

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16

Tiwari, Vivek, and Mike Tien-Chien Lee. "Power Analysis of a 32-bit Embedded Microcontroller." VLSI Design 7, no. 3 (January 1, 1998): 225–42. http://dx.doi.org/10.1155/1998/89432.

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A new approach for power analysis of microprocessors has recently been proposed [14]. The idea is to look at the power consumption in a microprocessor from the point of view of the actual software executing on the processor. The basic component of this approach is a measurement based, instruction-level power analysis technique. The technique allows for the development of an instruction-level power model for the given processor, which can be used to evaluate software in terms of the power consumption, and for exploring the optimization of software for lower power. This paper describes the application of this technique for a comprehensive instruction-level power analysis of a commercial 32-bit RISC-based embedded microcontroller. The salient results of the analysis and the basic instruction-level power model are described. Interesting observations and insights based on the results are also presented. Such an instruction-level power analysis can provide cues as to what optimizations in the micro-architecture design of the processor would lead to the most effective power savings in actual software applications. Wherever the results indicate such optimizations, they have been discussed. Furthermore, ideas for low power software design, as suggested by the results, are described in this paper as well.

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17

Maladkar, Kishan. "Design and Implementation of a 32-bit Floating Point Unit." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 14, 2021): 731–36. http://dx.doi.org/10.22214/ijraset.2021.35052.

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A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.

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18

Carballo, P. P., R. Sarmiento, and A. Núñez. "Integer and control units for a GaAs 32-bit RISC processor." Microprocessing and Microprogramming 37, no. 1-5 (January 1993): 105–8. http://dx.doi.org/10.1016/0165-6074(93)90026-h.

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19

Priya, K. Hari, and Chinthakindi Roja Sree. "Design of 32 Bit Low Power RISC Processor for DSP Applications." International Journal of Engineering Trends and Technology 34, no. 1 (April 25, 2016): 5–14. http://dx.doi.org/10.14445/22315381/ijett-v34p202.

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20

Dang, Dung, Daniel J. Pack, and Steven F. Barrett. "Embedded Systems Design with the Texas Instruments MSP432 32-bit Processor." Synthesis Lectures on Digital Circuits and Systems 11, no. 3 (October 26, 2016): 1–574. http://dx.doi.org/10.2200/s00728ed1v01y201608dcs051.

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21

P. Indira, M. Kamaraju, and Ved Vyas Dwivedi. "Design and Analysis of A 32-bit Pipelined MIPS Risc Processor." International Journal of VLSI Design & Communication Systems 10, no. 5 (October 31, 2019): 1–18. http://dx.doi.org/10.5121/vlsic.2019.10501.

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22

Zhang, Song, Yi Zhang, Lian Fa Bai, and Wen Jiang Li. "Design on Embedded Processor with Configurable Divider." Applied Mechanics and Materials 336-338 (July 2013): 1504–9. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1504.

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By analyzing Cortex-M3 Instruction Set and AHB Bus protocol, a Cortex-M3 Instruction Set compatible 32-bit RISC embedded microprocessor with built-in an optimized 5+2-stage pipeline was realized in this paper. The performance of the 32-bit RISC processor is optimized by deepening pipeline and optimizing functional modules compared with Cortex-M3. According to division instructions, a configurable hardware divider in different realization ways was realized for different applications. The design of the system architecture was completed using Verilog hardware description language (Verilog HDL) and Top-down methodology. The logic function was corrected by VCS simulation FPGA verification. Design Compiler synthesis result shows that, the maximal dominant frequency of the RISC embedded microprocessor could be up to 95MHz with the 0.18um CMOS process of SMIC, and is improved by 31.94% compared with STM32 Cortex-M3 (72MHz).

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23

Park, Sungkyung, and Chester Sungchung Park. "Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750132. http://dx.doi.org/10.1142/s0218126617501328.

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Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5[Formula: see text]m W, and 0.06[Formula: see text]m W, respectively, at 10[Formula: see text]MHz in a 0.18[Formula: see text][Formula: see text]m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50[Formula: see text][Formula: see text]W/MHz with 10,800 gates in a 0.18[Formula: see text][Formula: see text]m CMOS process.

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24

Komori, S., H. Takata, T. Tamura, F. Asai, T. Ohno, O. Tomisawa, T. Yamasaki, K. Shima, H. Nishikawa, and H. Terada. "A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme." IEEE Journal of Solid-State Circuits 24, no. 5 (October 1989): 1341–47. http://dx.doi.org/10.1109/jssc.1989.572611.

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25

Pfister. "The Work Station: Parallel Processor Project To Link 512 32-bit Micro." Computer 19, no. 1 (January 1986): 98–99. http://dx.doi.org/10.1109/mc.1986.1663040.

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26

Chen, Xiaoyi, Qingdong Yao, and Peng Liu. "Data bypassing architecture and circuit design for 32-bit digital signal processor." Journal of Electronics (China) 22, no. 6 (November 2005): 640–49. http://dx.doi.org/10.1007/bf02687845.

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27

Wu, Guang Wen, Xiang Sheng Huang, and Wen Long Hu. "A Novel Method for Solution of the Division Operation on ARM7 Microcontroller." Advanced Materials Research 718-720 (July 2013): 2418–21. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.2418.

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Before architecture V7, the hardware of ARM microcontroller family does not support division operation. Although it is easy to program on ARM processors with C language which can implement division operation with library functions, the procedure has much trouble and the efficiency is lower when the function code written in C language is called in assembly program. This paper introduces an algorithm for the division operation on ARM7 processor and also gives corresponding subroutines which can be used directly in assembly program design. The algorithm is similar to the operation theory of the digital circuit which uses subtraction circuit to do division operation. The given subroutines can deal with the division operation between two 32-bit unsigned integers and the division between a 64-bit unsigned integer and a 32-bit unsigned integer.

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28

Oh, Myeong-Hoon. "Architectural Design Issues in a Clockless 32 Bit Processor Using an Asynchronous HDL." ETRI Journal 35, no. 3 (June 1, 2013): 480–90. http://dx.doi.org/10.4218/etrij.13.0112.0598.

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29

Begum, Sd Ameerunnisa, and Dr Sailaja M. "Implementation of a 32 bit RISC processor with memory controller by using VHDL." IJIREEICE 3, no. 8 (August 15, 2015): 110–14. http://dx.doi.org/10.17148/ijireeice.2015.3824.

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30

., Priyavrat Bhardwaj. "DESIGN AND SIMULATION OF A 32-BIT RISC BASED MIPS PROCESSOR USING VERILOG." International Journal of Research in Engineering and Technology 05, no. 11 (November 25, 2016): 166–72. http://dx.doi.org/10.15623/ijret.2016.0511030.

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31

Elliott, I. D., and I. L. Sayers. "Implementation of 32-bit RISC processor incorporating hardware concurrent error detection and correction." IEE Proceedings E Computers and Digital Techniques 137, no. 1 (1990): 88. http://dx.doi.org/10.1049/ip-e.1990.0009.

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32

Han, Liang, Jie Chen, and Xiaodong Chen. "Power optimization for the datapath of a 32-bit reconfigurable pipelined DSP processor." Journal of Electronics (China) 22, no. 6 (November 2005): 650–57. http://dx.doi.org/10.1007/bf02687846.

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33

Sukemi, Sukemi, and Riyanto Riyanto. "Priority based computation: â€œAn Initial study result of paradigm shift on real time computationâ€." Computer Engineering and Applications Journal 6, no. 1 (February 26, 2017): 29–38. http://dx.doi.org/10.18495/comengapp.v6i1.198.

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This research is purposed to increase computer function into a time driven to support real time system. This purposed would the processor can work according to determined time variable and can work optimally in a certained deadline. The first approachment to design some of processor that has a different bit space 64, 32, 16 and 8 bits. Each processor will be separated by selector/arbiter priority of a task. In addition, the design of the above processors are designed as a counter with varying levels of accuracy (variable precision computing). The selection is also done by using statistical control in the task are observed by the appearance of controller mounted on the front of the architecture bit space the second approach above. The last approach to â€˜addâ€™ certainty in the form of interval arithmetic precision cutting task that can be the upper bound and lower bound of the area (bounds). These four approachment can be structured orthogonally into a processor/several processors by introducing a new classifier that serves as a selector or a task arbiter. The results of the four approaches to prove that the processor is prepared by incorporating a variable bitspace adder selectors can provide optimality of 0.43%.

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34

Hyodo, Kazuhito, Hirokazu Noborisaka, and Takashi Yada. "Development of Mechatronics Teaching Materials for Embedded System Engineer Education." Journal of Robotics and Mechatronics 23, no. 5 (October 20, 2011): 611–17. http://dx.doi.org/10.20965/jrm.2011.p0611.

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We have developed a learning environment for embedded system design. The learning environment consists of a multi-purpose controller and terminal devices. The controller consists of main processor (arm) and a multi-core microprocessor (Propeller). The main processor provides the software development environment. The Propeller chip has eight 32-bit processors and can perform simultaneous tasks for multiple users. In addition, the Propeller chip provides a reconfigurable peripheral module. This feature is very useful for the development of educational materials. Teachers can develop various educational materials with this control module.

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35

Brown, Michael C. "Multiple System Configurations in a 32-bit Extreme Environment." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000301–6. http://dx.doi.org/10.4071/hitec-2012-tha12.

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Full computational systems are needed at extreme environments (to 300°C) to increase functionality and reduce cost in the ever advancing oil/gas, geothermal, aeronautic, and automotive industries. Commercially available electronic components are not available to build a reliable system. A single microcontroller device can be used in systems of varying complexity, from small, mid, large, and multiprocessor scale. The 32-bit microcontroller will use a low power silicon-on-insulator CMOS process to increase long term reliability. Communication ports are provided to allow for simple systems with a single processor to complex multiprocessor systems with multiple controlled devices and external memory. As no adequate non-volatile solution is available for extreme conditions, multiple boot options are available to load instructions from external sources. Fault tolerance should be provided by system error detection. Battery backup must be provided for program and data retention. The resulting microcontroller will allow a wide variety of extreme environment systems, from simple to complex.

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36

Kim, HanBit, Seokhie Hong, and HeeSeok Kim. "Lightweight Conversion from Arithmetic to Boolean Masking for Embedded IoT Processor." Applied Sciences 9, no. 7 (April 5, 2019): 1438. http://dx.doi.org/10.3390/app9071438.

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A masking method is a widely known countermeasure against side-channel attacks. To apply a masking method to cryptosystems consisting of Boolean and arithmetic operations, such as ARX (Addition, Rotation, XOR) block ciphers, a masking conversion algorithm should be used. Masking conversion algorithms can be classified into two categories: “Boolean to Arithmetic (B2A)” and “Arithmetic to Boolean (A2B)”. The A2B algorithm generally requires more execution time than the B2A algorithm. Using pre-computation tables, the A2B algorithm substantially reduces its execution time, although it requires additional space in RAM. In CHES2012, B. Debraize proposed a conversion algorithm that somewhat reduced the memory cost of using pre-computation tables. However, they still require ( 2 ( k + 1 ) ) entries of length ( k + 1 ) -bit where k denotes the size of the processed data. In this paper, we propose a low-memory algorithm to convert A2B masking that requires only ( 2 k ) ( k ) -bit. Our contributions are three-fold. First, we specifically show how to reduce the pre-computation table from ( k + 1 ) -bit to ( k ) -bit, as a result, the memory use for the pre-computation table is reduced from ( 2 ( k + 1 ) ) ( k + 1 ) -bit to ( 2 k ) ( k ) -bit. Second, we optimize the execution times of the pre-computation phase and the conversion phase, and determine that our pre-computation algorithm requires approximately half of the operations than Debraize’s algorithm. The results of the 8/16/32-bit simulation show improved speed in the pre-computation phase and the conversion phase as compared to Debraize’s results. Finally, we verify the security of the algorithm against side-channel attacks as well as the soundness of the proposed algorithm.

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37

Seok, Byoungjin, and Changhoon Lee. "Fast implementations of ARX-based lightweight block ciphers (SPARX, CHAM) on 32-bit processor." International Journal of Distributed Sensor Networks 15, no. 9 (September 2019): 155014771987418. http://dx.doi.org/10.1177/1550147719874180.

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Recently, many lightweight block ciphers are proposed, such as PRESENT, SIMON, SPECK, Simeck, SPARX, GIFT, and CHAM. Most of these ciphers are designed with Addition–Rotation–Xor (ARX)-based structure for the resource-constrained environment because ARX operations can be implemented efficiently, especially in software. However, if the word size of a block cipher is smaller than the register size of the target device, it may process inefficiently in the aspect of memory usage. In this article, we present a fast implementation method for ARX-based block ciphers, named two-way operation. Moreover, also we applied SPARX-64/128 and CHAM-64/128 and estimated the performance in terms of execution time (cycles per byte) on a 32-bit Advanced RISC Machines processor. As a result, we achieved a large amount of improvement in execution time. The cycles of round function and key schedule are reduced by 53.31% and 31.51% for SPARX-64/128 and 41.22% and 19.40% for CHAM-64/128.

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38

Keun-Sup Lee, Young Cheol Park, and Dae Hee Youn. "Software optimization of the MPEG-audio decoder using a 32-bit MCU RISC processor." IEEE Transactions on Consumer Electronics 48, no. 3 (August 2002): 671–76. http://dx.doi.org/10.1109/tce.2002.1037059.

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39

Sushma, S., Smruthi Koushika Ravindran, Pavan Rajendar Nadagoudar, and P. Augusta Sophy. "Implementation of a 32 – bit RISC processor with floating point unit in FPGA platform." Journal of Physics: Conference Series 1716 (December 2020): 012047. http://dx.doi.org/10.1088/1742-6596/1716/1/012047.

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40

Choi, Yeongung, Dongmin Jeong, Myeongjin Lee, Wookyung Lee, and Yunho Jung. "FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging." Electronics 10, no. 17 (September 2, 2021): 2133. http://dx.doi.org/10.3390/electronics10172133.

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In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

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RAO, Jinli, Tianyong AO, Shu XU, Kui DAI, and Xuecheng ZOU. "Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor." IEICE Transactions on Information and Systems E101.D, no. 11 (November 1, 2018): 2698–705. http://dx.doi.org/10.1587/transinf.2017icp0019.

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42

GEORGE, REENU, MANOJ G, and S. KANTHALAKSHMI. "Design and Implementation of PWM Stepper Motor Control Based On 32 Bit Arm Cortex Processor." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 3, no. 7 (July 20, 2014): 10617–23. http://dx.doi.org/10.15662/ijareeie.2014.0307048.

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43

Ibrahim, Muhammad Nasir, Namazi Azhari, Adam Baharum, Mariani Idroas, Uswah Khairudin, Johari Kassim, and Mohar Muhammad. "AMIR CPU: World’s First and Only 32-bit Softcore Processor in Schematic on Freeware Platform." Journal of Physics: Conference Series 1090 (September 2018): 012003. http://dx.doi.org/10.1088/1742-6596/1090/1/012003.

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44

Pinto, Rohan, and Kumara Shama. "Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950019. http://dx.doi.org/10.1142/s0218126619500191.

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Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

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Milner, J. J., and A. J. Grandison. "A Fast, Streaming SIMD Extensions 2, Logistic Squashing Function." Neural Computation 20, no. 12 (December 2008): 2967–72. http://dx.doi.org/10.1162/neco.2008.10-06-366.

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Schraudolph proposed an excellent exponential approximation providing increased performance particularly suited to the logistic squashing function used within many neural networking applications. This note applies Intel's streaming SIMD Extensions 2 (SSE2), where SIMD is single instruction multiple data, of the Pentium IV class processor to Schraudolph's technique, further increasing the performance of the logistic squashing function. It was found that the calculation of the new 32-bit SSE2 logistic squashing function described here was up to 38 times faster than the conventional exponential function and up to 16 times faster than a Schraudolph-style 32-bit method on an Intel Pentium D 3.6 GHz CPU.

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Wen, Wu, De Hua He, Hua Feng, and Peng Gu. "The Design of a New Network Cabling Experimental Instrument Based on Embedded System." Advanced Materials Research 328-330 (September 2011): 2427–31. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.2427.

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Structured Cabling is not a demonstrative course, but a course to stimulate students’ learning interest and to improve experiment’s efficiency. Unfortunately there are some disadvantages for experimental instruments on the present market, such as low testing speed, low automation level and less functions, etc. A multi-processor structure is proposed in this paper, which consists of a 32-bit ARM processor S3C2440 and a 8-bit Single Chip Microcomputer STC89LE54. This structure is used to develop a new network cabling experimental instrument, which is based on embedded system. The instrument can achieve precise processing, such as synchronous data acquisition for wire cores of 32 standard network lines according to EIA/TIA568A Standard or EIA/TIA568B Standard, display and data storage, etc. The instrument has characteristics of high efficiency, fast response, automatic identification, and ease of use. It is used to implement consistency between teaching and job training. Therefore it has high practical value.

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Murvay, Pal-Stefan, and Bogdan Groza. "Performance Evaluation of SHA-2 Standard vs. SHA-3 Finalists on Two Freescale Platforms." International Journal of Secure Software Engineering 4, no. 4 (October 2013): 1–24. http://dx.doi.org/10.4018/ijsse.2013100101.

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Embedded devices are ubiquitously involved in a large variety of security applications which heavily rely on the computation of hash functions. Roughly, two alternatives for speeding up computations co-exist in these resource constrained devices: parallel processing and hardware acceleration. Needles to say, multi-core devices are clearly the next step in embedded systems due to clear technological limitations on single processor frequency. Hardware accelerators are long known to be a cheaper approach for costly cryptographic functions. The authors analysis is focused on the five SHA-3 finalists which are also contrasted to the previous SHA-2 standard and to the widespread MD5. On the hardware side, the authors deploy their implementations on two platforms from Freescale: a S12X core equipped with an XGATE coprocessor and a Kinetis K60 core equipped with a crypto co-processor. These platforms differ significantly in terms of computational power, the first is based on a 16-bit Freescale proprietary architecture while the former relies on a more recent 32-bit Cortex core. The authors’ experimental results show mixed performances between the old standard and the new candidates. Some of the new candidates clearly outperform the old standard in terms of both computational speed and memory requirements while others do not. Bottom line, on the 16 bit platform BLAKE and Grøstl are the top performers while on the 32-bit platform Keccak, Blake and Skein give the best results.

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Montiel-Ross, Oscar, Jorge Quiñones, and Roberto Sepúlveda. "Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors." Advances in Fuzzy Systems 2012 (2012): 1–11. http://dx.doi.org/10.1155/2012/475894.

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This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

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Prasad Acharya, G., and M. Asha Rani. "Berger Code Based Concurrent Online Self-Testing of Embedded Processors." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 2 (June 30, 2018): 74. http://dx.doi.org/10.11591/ijres.v7.i2.pp74-81.

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In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX Reduced Instruction Set Computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults.

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Kumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi, and K. Hari Kishore. "Bit wise and delay of vedic multiplier." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.

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The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

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