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Journal articles on the topic '32 NM TECHNOLOGY NODE'

Author: Grafiati

Published: 11 September 2023

Last updated: 31 July 2025

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1

Das, Pankaj Kumar, Anurag Yadav, and Nidhi Chandra. "Analysis of Delay and Dynamic Crosstalk in Spatially Arranged Mixed CNT Bundle Interconnects at Different Technology Nodes." Key Engineering Materials 994 (November 5, 2024): 39–45. http://dx.doi.org/10.4028/p-vcvy4l.

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In the present nanoscale regime, mixed carbon nanotube bundles (MCBs) are considered to be highly promising interconnect options. This research paper introduces a spatially arranged mixed carbon nanotubes (CNTs) bundle (MCB), wherein single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) occupy equal halves in the MCB. An equivalent single conductor (ESC) model for MCB is employed to analyze the interconnect performances in terms of signal transmission delay and dynamic crosstalk delay at different technology nodes (i.e., 32nm, 22nm, and 16 nm). Encouragingly, a significant reduction in si

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Allgair, John, Benjamin Bunday, Aaron Cordes, et al. "Metrology Requirements for the 32 nm Technology Node and Beyond." ECS Transactions 18, no. 1 (2019): 151–60. http://dx.doi.org/10.1149/1.3096443.

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Huang, Zhengfeng, Di Cao, Jianguo Cui, et al. "Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology." Journal of Computer-Aided Design & Computer Graphics 33, no. 3 (2021): 346–55. http://dx.doi.org/10.3724/sp.j.1089.2021.18385.

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4

Huang, Zhengfeng, Yang Guo, Shangjie Pan, et al. "Tri-Node Upsets Self-Recovery Latch Design in 32 nm CMOS Technology." Journal of Computer-Aided Design & Computer Graphics 32, no. 12 (2020): 2013–20. http://dx.doi.org/10.3724/sp.j.1089.2020.18160.

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5

Ono, Kazuo, Kenzo Kurotsuchi, Yoshihisa Fujisaki, Riichiro Takemura, Motoyasu Terao, and Norikatsu Takaura. "Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond." Japanese Journal of Applied Physics 48, no. 4 (2009): 04C160. http://dx.doi.org/10.1143/jjap.48.04c160.

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6

Orlowski, Marius, and Andreas Wild. "Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?" ECS Transactions 3, no. 6 (2019): 3–17. http://dx.doi.org/10.1149/1.2357050.

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Park, Dae-Gyu, Mike Chudzik, and Haizhou Yin. "Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond." ECS Transactions 11, no. 6 (2019): 371–77. http://dx.doi.org/10.1149/1.2778394.

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Hussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET

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9

Kumar, Amresh, and Aminul Islam. "Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node." Microsystem Technologies 23, no. 9 (2016): 4099–109. http://dx.doi.org/10.1007/s00542-016-3055-4.

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10

Andrieu, F., O. Weber, T. Ernst, O. Faynot, and S. Deleonibus. "Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node." Microelectronic Engineering 84, no. 9-10 (2007): 2047–53. http://dx.doi.org/10.1016/j.mee.2007.04.132.

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11

Collaert, N., R. Rooyackers, A. Hikavyy, et al. "Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth." Thin Solid Films 517, no. 1 (2008): 101–4. http://dx.doi.org/10.1016/j.tsf.2008.08.031.

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12

Tosik, Grzegorz, Zbigniew Lisik, and Frederic Gaffiot. "Optical interconnections in future VLSI systems." Journal of Telecommunications and Information Technology, no. 3 (June 25, 2023): 105–8. http://dx.doi.org/10.26636/jtit.2007.3.841.

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This paper is focused on the latency and power dissipation in clock systems, which should be lower when the optical interconnects are applied. Simulation shows that the power consumed by an optical system is lower than that consumed by an electrical one, however the advantages of optics drastically decrease with the number of output nodes in H-tree. Additionally, simple replacement of an electrical system by an optical clock distribution network (CDN) results in high clock skew, which will be higher than 10% of the clock period for the 32 nm technology node.

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13

Sankar, P. A. Gowri, and K. Udhayakumar. "Ternary Flip-Flops Based on Emerging Sub-32 nm Technology Nodes." Journal of Low Power Electronics 10, no. 4 (2014): 602–16. http://dx.doi.org/10.1166/jolpe.2014.1355.

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14

Siddaiah, Premananda Belegehalli, Sahithi Narsepalli, Sanya Mittal, and Abdur Rehman. "Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider." Journal of Electrical Engineering 74, no. 5 (2023): 403–12. http://dx.doi.org/10.2478/jee-2023-0048.

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Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS ci

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15

Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.

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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transist

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Sharma, Vijay Kumar, and Manisha Pattanaik. "Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library." Journal of Circuits, Systems and Computers 25, no. 11 (2016): 1650134. http://dx.doi.org/10.1142/s0218126616501346.

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In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and buffer logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8[Formula: see text]V by using Silvaco’s EDA tools. All generated cells have same cell height of 1.58 [Formula: see text]m. The proposed logic cells attain large leakage and power del

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Trojman, Lionel, Eduardo Holguin, Marco Villegas, Luis-Miguel Procel, and Ramiro Taco. "From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits." Electronics 11, no. 4 (2022): 525. http://dx.doi.org/10.3390/electronics11040525.

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In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD cir

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18

Morgenfeld, Bradley. "Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes." Journal of Micro/Nanolithography, MEMS, and MOEMS 11, no. 1 (2012): 013010. http://dx.doi.org/10.1117/1.jmm.11.1.013010.

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19

Bourgeat, Johan, and Philippe Galy. "Single and compact ESD device Beta-Matrix solution based on bidirectional SCR Network in advanced 28/32 nm technology node." Solid-State Electronics 87 (September 2013): 34–42. http://dx.doi.org/10.1016/j.sse.2013.04.033.

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20

Mannaert, G., L. Witters, Denis Shamiryan, et al. "Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond." Solid State Phenomena 145-146 (January 2009): 253–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.253.

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The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both st

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21

Wada, Masayuki, H. Takahashi, J. Snow, Rita Vos, P. W. Mertens, and H. Shirakawa. "Applicable Solvent Photoresist Strip Process for High-K/Metal Gate." Solid State Phenomena 187 (April 2012): 105–8. http://dx.doi.org/10.4028/www.scientific.net/ssp.187.105.

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In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be acc

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22

Namdari, Ali, Orazio Aiello, and Daniele D. Caviglia. "A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing." Journal of Low Power Electronics and Applications 14, no. 3 (2024): 40. http://dx.doi.org/10.3390/jlpea14030040.

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A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms inp

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23

Hussin, H., N. Soin, M. F. Bukhori, S. Wan Muhamad Hatta, and Y. Abdul Wahab. "Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs." Scientific World Journal 2014 (2014): 1–13. http://dx.doi.org/10.1155/2014/490829.

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We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping inE′center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-kPMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects

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24

Pham, Huyen Thi, Hung Tuan Dao, and Nghia Xuan Pham. "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder." Journal of Science and Technology on Information security 9, no. 01 (2020): 12–19. http://dx.doi.org/10.54654/isj.v9i01.36.

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Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole deco

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25

Jin, Yurin, Yeonho Seo, Sungmi Kim, and Seongik Cho. "Three-Stage Operational Amplifier with Frequency Compensation Using Cascade Zero." Electronics 12, no. 11 (2023): 2361. http://dx.doi.org/10.3390/electronics12112361.

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Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This o

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26

Feruglio, S., F. Andrieu, O. Faynot, and G. Ghibaudo. "Low-temperature electrical characterization of fully depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 gate stack for the 32-nm technology node." Cryogenics 49, no. 11 (2009): 605–10. http://dx.doi.org/10.1016/j.cryogenics.2008.12.004.

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27

Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

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This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors

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28

Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-B

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29

Cho, Sangki, Sueyeon Kim, Insoo Choi, Myounggon Kang, Seungjae Baik, and Jongwook Jeon. "Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor." AIP Advances 13, no. 4 (2023): 045211. http://dx.doi.org/10.1063/5.0141131.

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Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility o

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30

Sharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.

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Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi

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31

Sharma, Neha, and Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS." International Journal of Modeling, Simulation, and Scientific Computing 12, no. 04 (2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.

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With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PV

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32

Ahmed Khan, Imran. "Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications." Journal of Physics: Conference Series 2161, no. 1 (2022): 012050. http://dx.doi.org/10.1088/1742-6596/2161/1/012050.

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Abstract Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature fr

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33

Amin, Abu Bony, Syed Muhammad Shakil, and Muhammad Sana Ullah. "A Theoretical Modeling of Adaptive Mixed CNT Bundles for High-Speed VLSI Interconnect Design." Crystals 12, no. 2 (2022): 186. http://dx.doi.org/10.3390/cryst12020186.

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The aroused quest to reduce the delay at the interconnect level is the main urge of this paper, so as to come across a configuration of carbon nanotube (CNT) bundles, namely, squarely packed bundles of mixed CNTs. The demonstrated approach in this paper makes the mixed CNT bundle adaptable to adopt for high-speed very-large-scale integration (VLSI) interconnects with technology shrinkage. To reduce the delay of the proposed configuration of the mixed CNT bundle, the behavioral change of resistance (R), inductance (L), and capacitance (C) has been observed with respect to both the width of the

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34

Garg, Sandeep, and Tarun K. Gupta. "A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology." Journal of Circuits, Systems and Computers 28, no. 10 (2019): 1950165. http://dx.doi.org/10.1142/s0218126619501652.

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In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum p

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35

Zhu, Yihan, and Takashi Ohsawa. "A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters." Japanese Journal of Applied Physics 61, SC (2022): SC1053. http://dx.doi.org/10.35848/1347-4065/ac44ce.

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Abstract A novel loadless four-transistor static random access memory (4T SRAM) cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32 nm technology node that the read static noise margin (SNM) of the proposed cell reache

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36

Ghasemian, Arsalan, Ebrahim Abiri, Kourosh Hassanli, and Abdolreza Darabi. "HF-QSRAM: Half-Select Free Quaternary SRAM Design with Required Peripheral Circuits for IoT/IoVT Applications." ECS Journal of Solid State Science and Technology 11, no. 1 (2022): 011002. http://dx.doi.org/10.1149/2162-8777/ac4798.

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By using CNFET technology in 32 nm node by the proposed SQI gate, two split bit-lines QSRAM architectures have been suggested to address the issue of increasing demand for storage capacity in IoT/IoVT applications. Peripheral circuits such as a novel quaternary to binary decoder for QSRAM have been offered. Various simulations on temperature, supply voltage, and access frequency have been done to evaluate and ensure the performance of the proposed SQI gate, suggested cells, and quaternary to binary decoder. Moreover, 1000 Monte-Carlo analyses on the fabrication parameters have been done to cla

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37

Bendre, Varsha S., A. K. Kureshi, and Saurabh Waykole. "Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier." Journal of Nanotechnology 2018 (December 4, 2018): 1–15. http://dx.doi.org/10.1155/2018/2301421.

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Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal proc

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38

Bano, Nasreen, M. Nizamuddin, Wakeel Ahmad, Faraz Hashmi, and Ahmed Abdu Alattab. "Design and Performance of Graphene Nanoribbon FET-Based OTA for Fast and Energy-Efficient Electronics in IoT." Journal of Nanoelectronics and Optoelectronics 20, no. 2 (2025): 181–92. https://doi.org/10.1166/jno.2025.3741.

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The analog circuitry of the highest speed, energy efficiency, and miniaturization must lie at the front end as the interface between digital electronics and practical applications in the Internet of Things (IoT) and portable devices. While analog sensors are vital to AI operation, such sensors require a lot of processing and high-performance technology. Advances in deep submicron technology promise very fast, small, and power-efficient analog circuitry. Graphene, possessing such unique qualities as long mean free path, high current density, high electron mobility, and low resistance, becomes a

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Bhuvana, B. P., and V. S. Kanchana Bhaaskaran. "Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures." Journal of Circuits, Systems and Computers 29, no. 01 (2019): 2050016. http://dx.doi.org/10.1142/s0218126620500164.

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This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increa

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40

Lai, Fu-Der, and Jian Long Huang. "Proposed single layer composite film used as high transmission phase shifting masks for the 32, 45, and 65 nm technology nodes." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 25, no. 6 (2007): 1799. http://dx.doi.org/10.1116/1.2790920.

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Dadoria, Ajay Kumar, Kavita Khare, Tarun Kumar Gupta, and R. P. Singh. "New Leakage Reduction Techniques for FinFET Technology with Its Application." Journal of Circuits, Systems and Computers 27, no. 07 (2018): 1850112. http://dx.doi.org/10.1142/s0218126618501128.

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This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32[Formula: see text]nm technology node at 25[Formula: see text]C and 110[

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Bhattacharya, Sandip, Debaprasad Das, and Hafizur Rahaman. "Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network." Journal of Circuits, Systems and Computers 27, no. 01 (2017): 1850001. http://dx.doi.org/10.1142/s0218126618500019.

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The work in this paper presents the analyses of temperature-dependent simultaneous switching noise (SSN) and IR-Drop in multilayer graphene nanoribbon (MLGNR) power interconnects for 16[Formula: see text]nm ITRS technology node. A [Formula: see text] standard cell-based integrated circuit is designed to analyze the SSN and IR-Drop using the proposed temperature-dependent model of MLGNR and Cu interconnect for 10[Formula: see text][Formula: see text]m interconnect length at temperatures (233[Formula: see text]K, 300[Formula: see text]K and 378[Formula: see text]K). Our analysis shows that MLGNR

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Cho, Sangki, Sueyeon Kim, Myounggon Kang, Seungjae Baik, and Jongwook Jeon. "Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices." Micromachines 15, no. 4 (2024): 450. http://dx.doi.org/10.3390/mi15040450.

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Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have t

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Park, Jun-Young, Minhyun Jin, Soo-Youn Kim, and Minkyu Song. "Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips." Electronics 11, no. 6 (2022): 877. http://dx.doi.org/10.3390/electronics11060877.

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In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 10

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Decoster, Stefan, Elisabeth Camerotto, Gayle Murdoch, et al. "Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below." Journal of Vacuum Science & Technology B 40, no. 3 (2022): 032802. http://dx.doi.org/10.1116/6.0001791.

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Ruthenium and molybdenum are candidate materials to replace Cu as the back-end-of-line interconnect metal for the tightest pitch features for future technology nodes. Due to their better figure of merit ρ0 × λ (ρ0 bulk resistivity, λ electron mean free path), it is expected that the resistance of <10 nm wide Ru and Mo metal lines can be significantly reduced compared to Cu. An important advantage for Ru and Mo is that both materials, in contrast to Cu, can be patterned by means of so-called direct metal etch, through reactive ion etching or atomic layer etching and can potentially be implem

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Decoster, Stefan, Elisabeth Camerotto, Gayle Murdoch, et al. "Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below." Journal of Vacuum Science & Technology B 40, no. 3 (2022): 032802. http://dx.doi.org/10.1116/6.0001791.

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Ruthenium and molybdenum are candidate materials to replace Cu as the back-end-of-line interconnect metal for the tightest pitch features for future technology nodes. Due to their better figure of merit ρ0 × λ (ρ0 bulk resistivity, λ electron mean free path), it is expected that the resistance of <10 nm wide Ru and Mo metal lines can be significantly reduced compared to Cu. An important advantage for Ru and Mo is that both materials, in contrast to Cu, can be patterned by means of so-called direct metal etch, through reactive ion etching or atomic layer etching and can potentially be implem

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Kim, Youngbae, Shuai Li, Nandakishor Yadav, and Kyuwon Ken Choi. "A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks." Electronics 10, no. 17 (2021): 2181. http://dx.doi.org/10.3390/electronics10172181.

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We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-th

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Lai, Fu-Der, Jui-Ming Hua, C. Y. Huang, et al. "ArF-line high transmittance attenuated phase shift mask blanks using amorphous Al2O3–ZrO2–SiO2 composite thin films for the 65-, 45- and 32-nm technology nodes." Thin Solid Films 496, no. 2 (2006): 247–52. http://dx.doi.org/10.1016/j.tsf.2005.08.382.

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Bilouk, Sabrina, Carole Pernel, Lucile Broussous, Valentina Ivanova, and Ricardo Nogueira. "Electrochemical Behavior of Cobalt in Post-Via Etch Cleaning Solutions." Solid State Phenomena 145-146 (January 2009): 343–46. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.343.

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The integration of CoWP and CoWB self-aligned barriers (SAB) for 32 nm technology nodes allows improving copper interconnections reliability [1, 3]. However the introduction of such materials in copper interconnection levels drives new challenges for plasma dry etch and wet clean processes. Indeed, during the post-via-etch cleaning step, cobalt and copper can be altered by corrosion. Moreover, a galvanic coupling between cobalt, the major component of SAB, and copper can thermodynamically occur. In this way, the cleaning solution acts as ionic medium providing a contact between the two metals.

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Kang, Bong Kyun, Ji Hyun Jeong, Min Su Kim, Hong Seong Sohn, Ahmed A. Busnaina, and Jin Goo Park. "Acoustic Cavitation Behavior in Isopropyl Alcohol Added Cleaning Solution." Solid State Phenomena 195 (December 2012): 169–72. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.169.

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As the semiconductor manufacturing technology for ultra-high integration devices continue to shrink beyond 32 nm, stringent measures have to be taken to get damage free patterns during the cleaning process. The patterns are no longer cleaned with the megasonic (MS) irradiation in the advanced device node because of severe pattern damages caused by cleaning. Recently, several investigations are carried out to control the cavitation effects of megasonic to reduce the pattern damages. The mechanism of damage caused by an unstable acoustic bubble motion was mainly attributed to the high sound pres

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