Relevant bibliographies by topics / 3D IC

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic '3D IC'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 June 2025

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Journal articles on the topic "3D IC"

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Hyun, Seung-Min, and Chang-Woo Lee. "TSV Core Technology for 3D IC Packaging." Journal of the Korean Welding and Joining Society 27, no. 3 (2009): 4–9. http://dx.doi.org/10.5781/kwjs.2009.27.3.004.

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Keech, John T., Garret Piech, and Scott Pollard. "Fabrication of 3D-IC Interposers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (2013): 001295–321. http://dx.doi.org/10.4071/2013dpc-wp11.

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Interposer fabrication has gained a lot of attention in the area of three-dimensional integrated circuit (3D-IC) integration. Glass has many properties that make it well suited for interposer substrates, such as adjustable coefficient of thermal expansion, advantaged electrical properties and unique forming processes. Furthermore, glass based solutions can also provide significant cost advantages in substrate material, via formation, and subsequent processing. In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer substrates. Leveraging the ability to create through-glass-via (TGV) substrates in as-formed 100 μm thick precision glass, with a pristine surface, can avoid the need for back grinding and polishing operations. This has the potential to eliminate several manufacturing steps for polishing and thinning, while providing associated cost savings. Significant progress has been made in demonstration of TGV technology. Fully populated wafers with 100,000s of through or blind holes (≥ 25 μm diameter) are fabricated today, and 10–20 μm diameters are in development. We will report on important quality parameters measured on TGV wafers and positive implications with respect to product quality and strength. The ability to leverage industry metallization techniques and performance characteristics will also be reported. Finally, we will discuss opportunities to leverage cost-effective glass interposer solutions.
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Pandey, Vinayak. "3D IC: An Industry Overview." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000052–76. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_ta1_065.

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This presentation will provide a comprehensive landscape of the current status of 3D IC including the main trends of utilizing TSV based stacked 3DIC as well as Si interposer based 2.5D IC packages. The differentiation of the market requirements (and cost) that drives technology development and commercialization will be explained and summarized. TSV less 3DIC development options will be discussed. In addition, brief overview of the challenges of ‘transistor level stacking’ will be provided.
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Jiang, Hao, Jasbir N. Patel, and Bozena Kaminska. "Plasmon Rulers for 3D IC Alignment." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–20. http://dx.doi.org/10.4071/2017dpc-tha1_presentation1.

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Li, Feng, Andrew W. Owens, and Qianyi Li. "Microbump Processing for 3D IC Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 001028–49. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp2_049.

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In recent years, the development of microbumps has allowed even smaller sizes of ICs to utilize the flip chip technique. In addition, microbumps have enabled the implementation of three-dimensional (3D) ICs, which drastically improve the spatial efficiency of packaging. However, as the bumps size decreases and the number increases, several process challenges must be considered, for example, the height consistency of bump, the ratio of miss and deformity bump and the yield and strength of interconnection, etc. Therefore, it is increasingly important to study the interconnection technology and materials of high-density microbump interconnection. After briefly introducing the common electronic packaging techniques, including wire bonding, tape-automated bonding and flip chip, this paper reviews microbumps as an advanced bonding technology. Techniques such as Controlled Collapse Chip Connection - New Process(C4NP), printing, insert bump bonding, and self-replication process are discussed and compared. C4NP can achieve low-cost, fine pitch bumping by utilizing varied lead-free solder alloys, which overcomes the limitation of existing bumping technologies. Depending on the microbump size, engraved mask stump, and photosensitive organic mask and squeegee are the two ways for micro-bump printing. The micro-insert bump bonding process is new to stack chips vertically, which has robust bonding structure and a simpler bonding process compared to Cu pillar bonding process. The self-replication process is using the surface tension property of molten solder between the micro bridged bump to get two bumps with same volume and geometries on each faced pairs of lands. The use of two common material for the microbump, Cu, Sn, and its alloys are presented along with the differences in the process for each. As with any technology, a new breakthrough addressing an issue brings with it its own set of shortfalls. Microbumps are no different. The various techniques and materials used to realize the reduced scale bonding method are subject to a number of challenges. Most prominent among them are electromigration, thermomigration, and thermallyinduced mechanical fatigue, which are discussed in this paper.
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Garrou, Philip. "3D IC Technology: the Perfect Storm." International Symposium on Microelectronics 2010, no. 1 (2010): 000001–6. http://dx.doi.org/10.4071/isom-2010-ta1-paper1.

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IC technology, which has traditionally been dominated by dimensional scaling, is facing several technical and economic hurdles as it moves forward. Low K insulation has not been able to meet performance projections, copper traces are becoming more and more resistive, clock rates have been constrained due to thermal issues and multicore processors are demanding major increases in bandwidth and decreases in latency. Economic constraints will also begin limiting the number of IC companies able to develop leading-edge IC designs. Moving past 45 nm digital CMOS scaling will no longer guarantee lower cost and higher performance. All of these issues have crated a “perfect storm scenario” for the widespread adoption of 3D IC technology.
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Thom, J., R. Lipton, U. Heintz, et al. "3D IC for future HEP detectors." Journal of Instrumentation 9, no. 11 (2014): C11005. http://dx.doi.org/10.1088/1748-0221/9/11/c11005.

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Kim, Sungdong. "Thermal Management on 3D Stacked IC." Journal of the Microelectronics and Packaging Society 22, no. 2 (2015): 5–9. http://dx.doi.org/10.6117/kmeps.2015.22.2.005.

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Tang, Jing Jou, and Jan Liang Wu. "3D IC Designs: Myth vs. Reality." ECS Transactions 27, no. 1 (2019): 807–12. http://dx.doi.org/10.1149/1.3360714.

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Kapoor, Dipesh, Cher Ming Tan, and Vivek Sangwan. "Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits." Applied Sciences 10, no. 3 (2020): 748. http://dx.doi.org/10.3390/app10030748.

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Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.
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Dissertations / Theses on the topic "3D IC"

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Viswanathan, Vijayaragavan. "Modeling and design of 3D Imager IC." Phd thesis, Ecole Centrale de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00795558.

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CMOS image sensor based on Active pixel sensor has considerably contributed to the imaging market and research interest in the past decade. Furthermore technology advancement has provided the capability to integrate more and more functionality into a single chip in multiple layers leading to a new paradigm, 3D integration. CMOS image sensor is one such application which could utilize the capability of 3D stacked architecture to achieve dedicated technologies in different layers, wire length reduction, less area, improved performancesThis research work is focused mainly on the early stages of design space exploration using hierarchical approach and aims at reducing time to market. This work investigates the imager from the top-down design perspective. Methodical anal y sis of imager is performed to achieve high level of flexibility and modularity. Re-useable models are developed to explore early design choices throughout the hierarchy. Finally, pareto front (providing trade off solutions) methodology is applied to explore the operating range of individual block at system level to help the designer making his design choice. Furthermore the thermal issues which get aggravated in the 3D stacked chip on the performance of the imager are studied. Systeme based thermal model is built to investigate the behavior of imager pixel matrix and to simulate the pixel matrix at high speed with acceptable accuracy compared to electrical simulations. The modular nature of the model makes simulations with future matrix extension straightforward. Validation of the thermal model with respect to electrical simulations is discussed. Finally an integrated design flow is developed to perform 3D floorplanning and to perform thermal anal y sis of the imager pixel matrix.
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Li, Xiaoming. "Compact thermal modeling for 3D IC design." Diss., Online access via UMI:, 2005.

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Yahalom, Gilad. "Analog-digital co-existence in 3D-IC." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/103677.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 231-246).<br>Ubiquitous mobile communication creates an increasing demand for high data rates, complex modulation schemes and low power design. The cost and performance benefits of conventional lithographic scaling are diminishing as process cost increases exponentially. 3D integration has the potential to keep driving performance forward while keeping cost down. The possibility to integrate separate dies with low-parasitic, dense interconnect and shorter routing provides area and power benefits. However, new challenges must be addressed in order to enable design in this new dimension and provide system level improvements. This thesis explores the impact, challenges and advantages of using 3D integration for combining digital and analog circuits for RF applications. The use of a vertical solenoid inductor in a Voltage Controlled Oscillator (VCO) is proposed. The inductor design utilizes the through-silicon-vias of the 3D stack as part of its geometry. The solenoid inductor exhibits a 28%larger inductance and a 6 dB higher quality factor compared to a conventional planar inductor occupying the same area. The VCO circuit phase noise is improved by 6 dB and exhibits an improved immunity to coupling from adjacent digital clock lines routed on the bottom tier of the 3D stack. An efficient hardware implementation is presented for an LTE uplink channel. The proposed design processes input data for cellular transmission. The core of the computation includes a variable-length, high-order, mixed-radix FFT and IFFT blocks. The use of energy efficient circuits and algorithms enables achieving an energy efficiency of up to 95 pJ/Sample and additional power savings of up to 24% for different operation modes. Both designs are combined along with digital-to-analog conversion to create a partial cellular transmitter in 3D-IC. Highly flexible and configurable design allows for various partitioning of the system. The 3D design has a digital link energy efficiency of up to 0.37 pJ/bit, compared to the 33.3 pJ/bit consumed in a multiple die partitioning and 0.83 pJ/bit for a 2.5D interposer emulated design. The use of the solenoid VCO along with digital-analog partitioning between the die tiers enables high immunity to noise and reduction of spurs at the VCO output.<br>by Gilad Yahalom.<br>Ph. D.
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Elliott, Jane. "3D representation and characterisation of IC topography." Thesis, University of Edinburgh, 1998. http://hdl.handle.net/1842/13788.

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As IC feature sizes reduce and the use of multi-layer metal becomes more widespread, ICs are becoming increasingly topographically complex, and the effects of interconnect on circuit performance ever more significant. The electrical properties of interconnect must be accurately determined, and this can best be done by using 3D simulators which require an appropriate 3D representation of the circuit layout. The choice representation depends on the process used to manufacture the IC, which may include some reduction of topographical complexity using planarisation techniques. A test structure has been developed which can be used to electrically determine the degree of topographical planarity of an inter-metal dielectric. Simulated and experimental results obtained using this test structure are presented and shown to be comparable. Algorithms based on boolean polygon operations have been developed which produce 3D representations of integrated circuit layout directly from the mask data in a matter of minutes. These algorithms have been incorporated into software, 3DTOP, which has been used to automatically produce data for use with 3D capacitance simulators Raphael and FastCap, and with visualisation software POV-Ray. The results of 3D capacitance simulators of planar, semi-conformal and conformal representations of simple IC layouts created using 3DTOP have been compared. These indicate that the choice of 3D representation has a significant effect on simulated capacitance values, and that the importance of choosing the correct representation increases as interconnect track aspect ratios increase. Conventional and 3D extraction techniques have been used to determine the parasitic interconnect capacitances in a single transistor spatial light modulator circuit. The values extracted have been compared, and found to differ by up to 32%. The effect on circuit performance of the extracted capacitances has been shown to be significant.
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DASH, ASSMITRA. "Minimizing Test Time through Test FlowOptimization in 3D-SICs." Thesis, Linköpings universitet, Programvara och system, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-102171.

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3D stacked ICs (3D-SICs) with multiple dies interconnected by through-silicon-vias(TSVs) are considered as a technology driver and proven to have overwhelming advantagesover traditional ICs with a single die in a package in terms of performance, powerconsumption and silicon overhead. However, these “super chips” bring new challengesto the process of IC manufacturing; among which, testing 3D-SICs is the major andmost complex issue to deal with. In traditional ICs, tests can usually be performedat two stages (test instances), namely: a wafer sort and a package test. Whereas for3D-SICs, tests can be performed after each stacking event where a new die is stackedover a partial stack. This expands the set of available test instances. A combination ofselected test instances where a test is performed (active test instance) is known as a testflow. Test time is a major contributor to the total test cost. Test time changes with theselected test flow. Therefore, choosing a cost effective test flow which will minimizesthe test time is absolutely essential.This thesis focuses on finding an optimal test flow which minimizes the test timefor a given 3D-SIC. A mathematical model has been developed to evaluate the test timeof any test flow. Then a heuristic has been proposed for finding a near optimal test flowwhich minimizes the test time. The performance of this approach in terms of computationtime and efficiency has been compared against the minimum test time obtainedby exhaustive search. The heuristic gives good results compared to exhaustive searchwith much lesser computation time.
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Frantz, Ferreira Felipe. "Architectural exploration methods and tools for heterogeneous 3D-IC." Thesis, Ecully, Ecole centrale de Lyon, 2012. http://www.theses.fr/2012ECDL0033/document.

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L'intégration tridimensionnelle (3D), où plusieurs puces sont empilées et interconnectées, est en train de révolutionner l'industrie des semi-conducteurs.Cette technologie permet d'associer, dans un même boîtier, des puces électroniques (analogique, numérique, mémoire) avec des puces d'autres domaines(MEMS, bio-capteurs, optique, etc). Cela ouvre de nombreuses voies d'innovation. Néanmoins, l'absence d'outils de conception assistée ordinateur(CAO) adaptés aux systèmes 3D freine l'adoption de la technologie.Cette thèse contribue à deux problématiques liées à la conception 3D : le partitionnement d'un système sur de multiples puces et l'optimisation hiérarchique de systèmes multiphysiques (hétérogènes).La première partie de la thèse est dédiée au problème de partitionner la fonctionnalité d'un système sur de multiples puces. Un outil de « floorplan » 3D a été développé pour optimiser ce partitionnement en fonction de la surface des puces, de la température d'opération du circuit et de la structure des interconnexions. Ce type d'outil étant complexe, nous proposons de régler ses paramètres de façon automatique par l'utilisation d'algorithmes évolutionnaires.Des résultats expérimentaux sur une suite de benchmarks et sur une architecture multi processeur connecté en réseau démontrent l'efficacité et l'applicabilité des techniques d'optimisation proposées.Dans la deuxième partie, nous présentons une méthodologie de conception hiérarchique qui est adaptée aux systèmes hétérogènes. La méthode combine une approche ascendante et descendante et utilise des courbes de compromis(Fronts de Pareto) comme une abstraction de la performance d'un circuit.La contribution principale de la thèse consiste à utiliser des techniques d'interpolation pour représenter les Fronts de Pareto par des fonctions continues et à leur intégration dans des processus d'optimisation classiques. Cela permet un gain en flexibilité lors de l'étape ascendante du flot (caractérisation) et un gain en temps lors de l'étape descendante (synthèse). Le flot de conception est démontré sur un amplificateur opérationnel ainsi comme sur la synthèse d'un lien optoélectronique avec trois niveaux hiérarchiques<br>3D integration technology is driving a strong paradigm shift in the design of electronic systems. The ability to tightly integrate functions from different technology nodes (analog, digital, memory) and physical domains (MEMS, optics, etc) offers great opportunities for innovation (More than Moore). However, leveraging this potential requires efficient CAD tools to compare architectural choices at early design stages and to co-optimize multiphysics systems.This thesis work is divided into two parts. The first part is dedicated to the problem of partitioning a system into multiple dies. A 3D floorplanning tool was developed to optimize area, temperature and the interconnect structure of a 3DIC. Moreover, a meta-optimization approach based on genetic algorithms is proposed to automatically configure the key parameters of the floorplanner. Tests were carried out on architectural benchmarks and a NoC based multiprocessor to demonstrate the efficiency of the proposed techniques.In the second part of the thesis, a hierarchical design methodology adapted to heterogeneous systems is presented. The method combines the bottom-up and top-down approaches with Pareto-front techniques and response surface modeling. The Pareto front of lower level blocks are extracted and converted into predictive performance models that can be stored and reused in a top-down optimization process. The design flow is demonstrated on an operational amplifier as well as on the synthesis of an optoelectronic data link with three abstraction levels
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Jabbar, Mohamad. "Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00934780.

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Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre dans l'industrie. Sur la base des listes d'interconnexions en déroute, nous procédons à l'analyse des performances d'évaluer le bénéfice de l'architecture 3D par rapport à sa mise en oeuvre 2D. Sur la base du flot de conception 3D proposé en se concentrant sur la vérification temporelle tirant parti de l'avantage du retard négligeable de la structure de microbilles pour les connexions verticales, nous avons mené techniques de partitionnement de NoC 3D basé sur l'architecture MPSoC y compris empilement homogène et hétérogène en utilisant Tezzaron 3D IC technlogy. Conception et mise en oeuvre de compromis dans les deux méthodes de partitionnement est étudiée pour avoir un meilleur aperçu sur l'architecture 3D de sorte qu'il peut être exploitée pour des performances optimales. En utilisant l'approche 3D homogène empilage, NoC topologies est explorée afin d'identifier la meilleure topologie entre la topologie 2D et 3D pour la mise en œuvre MPSoC 3D sous l'hypothèse que les chemins critiques est fondée sur les liens inter-routeur. Les explorations architecturales ont également examiné les différentes technologies de traitement. mettant en évidence l'effet de la technologie des procédés à la performance d'architecture 3D en particulier pour l'interconnexion dominant du design. En outre, nous avons effectué hétérogène 3D d'empilage pour la mise en oeuvre MPSoC avec l'approche GALS de style et présenté plusieurs analyses de conception physiques connexes concernant la conception 3D et la mise en œuvre MPSoC utilisant des outils de CAO 2D. Une analyse plus approfondie de l'effet microbilles pas à la performance de l'architecture 3D à l'aide face-à-face d'empilement est également signalé l'identification des problèmes et des limitations à prendre en considération pendant le processus de conception.
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LIU, BOSUI. "VERTICALLY INTERCONNECTED WIDE-BANDWIDTH MONOLITHIC PLANAR ANTENNAS FOR 3D-IC." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1040154281.

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Sarhan, Hossam. "Design methodology and technology assessment for high-desnity 3D technologies." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT134/document.

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L'impact des interconnections d'un circuit intégré sur les performances et la consommation est de plus en plus important à partir du nœud CMOS 28 nm et au-delà, ayant pour effet de minimiser de plus ne plus la loi de Moore. Cela a motivé l'intérêt des technologies d'empilement 3D pour réduire l'effet des interconnections sur les performances des circuits. Les technologies d'empilement 3D varient suivant différents procédés de fabrication d'où l'on mettra en avant la technologie Trough Silicon Via (TSV) – Collage Cuivre-Cuivre (Cu-Cu) et 3D Monolithique. TSV et Cu-Cu présentent des diamètres d'interconnexions 3D de l'ordre de 10 µm tandis que le diamètre d'une interconnexion 3D Monolithique est 0.1 µm, c'est-à-dire cent fois plus petit. Un tel diamètre d'interconnexion créée de nouveaux challenge en terme de conception de circuit intégré numérique. Dans ce contexte, notre objectif est de proposer des méthodologies de conception de circuits 3D innovantes afin d'utiliser au mieux la densité d'intégration possible et d'évaluer efficacement les gains en performance, surface et consommation potentiels de ces différentes technologies d'empilement par rapport à la conception de circuit 2D.Trois contributions principales constituent cette thèse : La densité d'intégration offerte par les technologies d'empilement étudiées laisse le possibilité de revoir la topologie des cellules de bases en les concevant directement en 3D. C'est ce qui a été fait dans l'approche Cellule sur Buffer (Cell-on-Buffer – CoB), en empilant la fonction logique de base d'une cellule sur l'étage d'amplification. Les simulations montrent des gains substantiels par rapport aux circuits 2D. On a imaginé par la suite désaligner les niveaux d'alimentation de chaque tranche afin de créer une technique de Multi-VDD adaptée à l'empilement 3D pour réduire encore plus la consommation des circuits 3D.Dans un deuxième temps, le partitionnement grain fin des cellules a été étudié. En effet au niveau VLSI, quand on conçoit un circuit de plusieurs milliers voir million de cellules standard en 3D, se pose la question de l'attribution de telle ou telle cellule sur la tranche haute ou basse du circuit 3D afin d'accroitre au mieux les performances et consommation du circuit 3D. Une méthodologie de partitionnement physique est introduite pour cela.Enfin un environnement d'évaluation des performances et consommation des technologies 3D est présenté avec pour objectif de rapidement tester les gains possibles de telle ou telle technologie 3D tout en donnant des directives quant à l'impact des certains paramètres technologiques 3D sur les performances et consommation<br>Scaling limitations of advanced technology nodes are increasing and the BEOL parasitics are becoming more dominant. This has led to an increasing interest in 3D technologies to overcome such limitations and to continue the scaling predicted by Moore's Law. 3D technologies vary according to the fabrication process which creates a wide spectrum of technologies including Through-Silicon-VIA (TSV), Copper-to-Copper (CuCu) and Monolithic 3D (M3D). TSV and CuCu provide 3D contacts of pitch around 5-10um while M3D scales down 3D via pitch extremely to 0.11um. Such high-density capability of Monolithic 3D technology creates new design paradigms. In this context, our objective is to propose innovative design methodologies to well utilize M3D technology and introduce a technology assessment framework to evaluate different M3D technology parameters from design perspective.This thesis can be divided into three main contributions. As creating 3D standard cells become achievable thanks to M3D technology, a new 3D standard cell approach has been introduced which we call it ‘3D Cell-on-Buffer' (3DCoB). 3DCoB cells are created by splitting 2D cells into functioning gates and driving buffers stacked over each other. The simulation results show gain in timing performances compared to 2D. By applying an additionally Multi-VDD low-power approach, iso-performance power gain has been achieved. Afterwards cell-on-cell design approach has been explored where a partitioning methodology is needed to distribute cells between different tiers, i.e. determine which cell is placed on which tier. A physical-aware partitioning methodology has been introduced which improves power-performance-area results comparing to the state-of-the-art partitioning techniques. Finally a full high-density 3D technology assessment study is presented to explore the trade-offs between different 3D technologies, block complexities and partitioning methodologies
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Panth, Shreepad Amar. "Physical design methodologies for monolithic 3D ICs." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53542.

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The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored. Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed. Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences. Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.
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Books on the topic "3D IC"

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3D IC stacking technology. McGraw-Hill Professional, 2011.

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Lau, John. 3D IC Integration and Packaging. McGraw-Hill Education, 2015.

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3D and IC Integration of MEMS. Wiley & Sons, Limited, John, 2021.

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Xiao, Hong. 3D IC Devices, Technologies, and Manufacturing. SPIE, 2016. http://dx.doi.org/10.1117/3.2234473.

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Reliability Of Rohscompliant 2d And 3d Ic Interconnects. McGraw-Hill Professional Publishing, 2010.

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Horng, Tzyy-Sheng Jason, and Lih-Tyng Hwang. 3D IC and RF Sips: Advanced Stacking and Planar Solutions for 5G Mobility. Wiley & Sons, Incorporated, John, 2018.

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Horng, Tzyy-Sheng Jason, and Lih-Tyng Hwang. 3D IC and RF SiPs: Advanced Stacking and Planar Solutions for 5G Mobility. Wiley & Sons, Incorporated, John, 2018.

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Book chapters on the topic "3D IC"

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Lau, John H. "3D IC Integration and 3D IC Packaging." In Semiconductor Advanced Packaging. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1376-0_7.

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Kumar, Adesh, Gaurav Verma, Vijay Nath, and Sushabhan Choudhury. "IC Packaging: 3D IC Technology and Methods." In Lecture Notes in Electrical Engineering. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-2999-8_25.

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Garrou, Philip, Peter Ramm, and Mitsumasa Koyanagi. "3D IC Integration Since 2008." In Handbook of 3D Integration. Wiley-VCH Verlag GmbH & Co. KGaA, 2014. http://dx.doi.org/10.1002/9783527670109.ch01.

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Lim, Sung Kyu. "Steiner Routing for 3D IC." In Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4419-9542-1_2.

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Lim, Sung Kyu. "Buffer Insertion for 3D IC." In Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4419-9542-1_3.

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Xie, Yang, Chongxi Bao, and Ankur Srivastava. "3D/2.5D IC-Based Obfuscation." In Hardware Protection through Obfuscation. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-49019-9_12.

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Kandlikar, Satish G., and Amlan Ganguly. "Fundamentals of Heat Dissipation in 3D IC Packaging." In 3D Microelectronic Packaging. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-44586-1_10.

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Lau, John H. "3D IC Heterogeneous Integration by FOWLP." In Fan-Out Wafer-Level Packaging. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8884-1_11.

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Takahashi, Hiroshi, Senling Wang, Shuichi Kameyama, et al. "Trends in 3D Integrated Circuit (3D-IC) Testing Technology." In Three-Dimensional Integration of Semiconductors. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-18675-7_8.

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Kandlikar, Satish G., and Amlan Ganguly. "Fundamentals of Heat Dissipation in 3D IC Packaging and Thermal-Aware Design." In 3D Microelectronic Packaging. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7090-2_13.

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Conference papers on the topic "3D IC"

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Brochard, Nicolas, Jamel Nebhen, and Dominique Ginhac. "3D-IC." In ICDSC '16: 10th international conference on distributed smart camera. ACM, 2016. http://dx.doi.org/10.1145/2967413.2967433.

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Wu, Xin. "3D-IC technologies and 3D FPGA." In 2015 International 3D Systems Integration Conference (3DIC). IEEE, 2015. http://dx.doi.org/10.1109/3dic.2015.7334564.

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Samal, Sandeep Kumar, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim. "Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology." In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2016. http://dx.doi.org/10.1109/s3s.2016.7804405.

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Whipple, Thomas, Taranjit Kukal, Keith Felton, and Vassilios Gerousis. "IC-package co-design and analysis for 3D-IC designs." In 2009 IEEE International Conference on 3D System Integration (3DIC). IEEE, 2009. http://dx.doi.org/10.1109/3dic.2009.5306589.

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Pan, Stephen H., Norman Chang, and Ji Zheng. "IC-Package Thermal Co-Analysis in 3D IC Environment." In ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASMEDC, 2011. http://dx.doi.org/10.1115/ipack2011-52240.

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Abstract:
Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology and its applications to accurately and efficiently predict power and temperature distribution for 3D ICs.
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Wilson, John. "Automatic thermal calibration of detailed IC package models." In 2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM). IEEE, 2016. http://dx.doi.org/10.1109/3dpeim.2016.7570549.

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Taklo, Maaike M. Visser, Nicolas Lietaer, Hannah Rosquist Tofteberg, et al. "3D MEMS and IC Integration." In 2008 MRS Fall Meetin. Materials Research Society, 2008. http://dx.doi.org/10.1557/proc-1112-e04-04.

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Keech, John, Satish Chaparala, Aric Shorey, Garrett Piech, and Scott Pollard. "Fabrication of 3D-IC interposers." In 2013 IEEE 63rd Electronic Components and Technology Conference (ECTC). IEEE, 2013. http://dx.doi.org/10.1109/ectc.2013.6575825.

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Kyung, Chong-Min. "Designer's Issues in 3D IC." In 2009 IEEE 8th International Conference on ASIC (ASICON). IEEE, 2009. http://dx.doi.org/10.1109/asicon.2009.5351293.

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Wong, S. Simon, and Abbas El Gamal. "The prospect of 3D-IC." In 2009 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2009. http://dx.doi.org/10.1109/cicc.2009.5280818.

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Reports on the topic "3D IC"

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Mohapatra, Sucheta. Dynamic Through-Silicon Via Clustering in 3D IC Floorplanning for Early Performance Optimization. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.7437.

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Larmat, Carene, Monica Maceira, and Yasuyuki Kato. YEARLY REPORT FOR THE PERIOD Jan-Dec 2012 IC PROJECT W12c_earthuq “ High-Performance Computing for Uncertainty Quantification of 3D Earth Models”. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1074574.

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