Relevant bibliographies by topics / 3D integrated circuit

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic '3D integrated circuit'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "3D integrated circuit"

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Koo, Jae-Mo, Sungjun Im, Linan Jiang, and Kenneth E. Goodson. "Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures." Journal of Heat Transfer 127, no. 1 (2005): 49–58. http://dx.doi.org/10.1115/1.1839582.

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The semiconductor community is developing three-dimensional circuits that integrate logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical systems. These three-dimensional (3D) circuits pose important challenges for thermal management due to the increasing heat load per unit surface area. This paper theoretically studies 3D circuit cooling by means of an integrated microchannel network. Predictions are based on thermal models solving one-dimensional conservation equations for boiling convection along microchannels, and are consistent with past data obtained from straight channels. The model is combined within a thermal resistance network to predict temperature distributions in logic and memory. The calculations indicate that a layer of integrated microchannel cooling can remove heat densities up to 135W/cm2 within a 3D architecture with a maximum circuit temperature of 85°C. The cooling strategy described in this paper will enable 3D circuits to include greater numbers of active levels while exposing external surface area for functional signal transmission.
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Wang, Shaoxi, Yue Yin, Chenxia Hu, and Pouya Rezai. "3D Integrated Circuit Cooling with Microfluidics." Micromachines 9, no. 6 (2018): 287. http://dx.doi.org/10.3390/mi9060287.

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Kim, Bruce, Sukeshwar Kannan, Anurag Gupta, and Naga Sai Evana. "Modeling and Simulation of 3D MEMS Integrated RF Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 002006–27. http://dx.doi.org/10.4071/2012dpc-wp35.

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Today's integrated packaging consists of analog, mixed-signal and RF circuits. These integrated packages are now available in 3-D which makes it extremely difficult to test for defects and their circuit functionalities. This paper provides 3D MEMS integrated packaging which provides self testing and calibrations to overcome process defects and out of spec circuits inside the package making the package self heal itself in case of faults and defects. We have worked on TSV based 3D packaging with MEMS switches to perform self calibrations. We developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated on an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. We used arrays of MEMS switches to perform self testing. We have considered a low noise amplifier as the reference RF circuit which operates between 4 GHz and 6 GHz. The entire validation of the design using test technique and self-calibration of the RF circuit is automated using the calibration algorithm. The paper presents defects in TSV due to mechanical stress and thermal changes.
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Indrusiak, Leandro Soares, and Ricardo Augusto da Luz Reis. "3D integrated circuit layout visualization using VRML." Future Generation Computer Systems 17, no. 5 (2001): 503–11. http://dx.doi.org/10.1016/s0167-739x(00)00036-4.

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Andras Moritz, Csaba. "Architecting 3D integrated circuit fabrics at nanoscale." Research Outreach, no. 108 (July 10, 2019): 122–25. http://dx.doi.org/10.32907/ro-108-122125.

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Behroozpour, Behnam, Phillip A. M. Sandborn, Niels Quack, et al. "Electronic-Photonic Integrated Circuit for 3D Microimaging." IEEE Journal of Solid-State Circuits 52, no. 1 (2017): 161–72. http://dx.doi.org/10.1109/jssc.2016.2621755.

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Li, Mingyu, Jiajun Shi, Mostafizur Rahman, Santosh Khasanvis, Sachin Bhat, and Csaba Andras Moritz. "Skybridge-3D-CMOS: A Fine-Grained 3D CMOS Integrated Circuit Technology." IEEE Transactions on Nanotechnology 16, no. 4 (2017): 639–52. http://dx.doi.org/10.1109/tnano.2017.2700626.

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Petrosyants, Konstantin O., and Nikita I. Ryabov. "Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages." Energies 13, no. 12 (2020): 3054. http://dx.doi.org/10.3390/en13123054.

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The problem of thermal modeling of modern three-dimensional (3D) integrated circuit (IC) systems in packages (SiPs) is discussed. An effective quasi-3D (Q3D) approach of thermal design is proposed taking into account the specific character of 3D IC stacked multilayer constructions. The fully-3D heat transfer equation for global multilayer construction is reduced to the set of coupled two-dimensional (2D) equations for separate construction layers. As a result, computational difficulties, processor time, and RAM volume are significantly reduced, while accuracy can be provided. A software tool, Overheat-3D-IC, was developed on the base of the generalized Q3D package numerical model. For the first time, the global 3D thermal performances across the modern integrated circuit/through-silicon via/ball grid array (IC-TSV-BGA) and multi-chip (MC)-embedded printed circuit board (PCB) packages were simulated. A ten times decrease of central processing unit (CPU) time was achieved as compared with the 3D solutions obtained by commercial universal 3D simulators, while saving the sufficient accuracy. The simulation error of maximal temperature TMAX determination for different types of packages was not more than 10–20%.
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Sabbavarapu, Srinivas, Amit Acharyya, P. Balasubramanian, and C. Ramesh Reddy. "Fast 3D Integrated Circuit Placement Methodology using Merging Technique." Defence Science Journal 69, no. 3 (2019): 217–22. http://dx.doi.org/10.14429/dsj.69.14410.

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In the recent years the advancement in the field of microelectronics integrated circuit (IC) design technologies proved to be a boon for design and development of various advanced systems in-terms of its reduction in form factor, low power, high speed and with increased capacity to incorporate more designs. These systems provide phenomenal advantage for armoured fighting vehicle (AFV) design to develop miniaturised low power, high performance sub-systems. One such emerging high-end technology to be used to develop systems with high capabilities for AFVs is discussed in this paper. Three dimensional IC design is one of the emerging field used to develop high density heterogeneous systems in a reduced form factor. A novel grouping based partitioning and merge based placement (GPMP) methodology for 3D ICs to reduce through silicon vias (TSVs) count and placement time is proposed. Unlike state-of-the-art techniques, the proposed methodology does not suffer from initial overlap of cells during intra-layer placement which reduces the placement time. Connectivity based grouping and partitioning ensures less number of TSVs and merge based placement further reduces intra layer wire-length. The proposed GPMP methodology has been extensively against the IBMPLACE database and performance has been compared with the latest techniques resulting in 12 per cent improvement in wire-length, 13 per cent reduction in TSV and 1.1x improvement in placement time.
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Hubbard, Joshua D., Ruben Acevedo, Kristen M. Edwards, et al. "Fully 3D-printed soft robots with integrated fluidic circuitry." Science Advances 7, no. 29 (2021): eabe5257. http://dx.doi.org/10.1126/sciadv.abe5257.

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The emergence of soft robots has presented new challenges associated with controlling the underlying fluidics of such systems. Here, we introduce a strategy for additively manufacturing unified soft robots comprising fully integrated fluidic circuitry in a single print run via PolyJet three-dimensional (3D) printing. We explore the efficacy of this approach for soft robots designed to leverage novel 3D fluidic circuit elements—e.g., fluidic diodes, “normally closed” transistors, and “normally open” transistors with geometrically tunable pressure-gain functionalities—to operate in response to fluidic analogs of conventional electronic signals, including constant-flow [“direct current (DC)”], “alternating current (AC)”–inspired, and preprogrammed aperiodic (“variable current”) input conditions. By enabling fully integrated soft robotic entities (composed of soft actuators, fluidic circuitry, and body features) to be rapidly disseminated, modified on demand, and 3D-printed in a single run, the presented design and additive manufacturing strategy offers unique promise to catalyze new classes of soft robots.
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Dissertations / Theses on the topic "3D integrated circuit"

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Sekar, Deepak Chandra. "Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26562.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects. This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential. A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
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Contreras, Andres A. "Micronetworking: Reliable Communication on 3D Integrated Circuits." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/728.

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The potential failure in through-silicon vias (TSVs) still poses a challenge in trying to extend the useful life of a 3D integrated circuit (IC). A model is proposed to mitigate the communication problem in 3D integrated circuits caused by the breaks at the TSVs. We provide the details of a low-complexity network that takes advantages of redundant TSVs to make it possible to re-route around breaks and maintain effective communication between layers. Different configurations for the micronetwork are analyzed and discussed. We also present an evaluation of the micronetwork's performance, which turns out to be quite promising, based on several Monte Carlo simulations. Finally, we provide some directions for future research on the subject.
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Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.

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For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.
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Kim, Dae Hyun. "Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43642.

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The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.
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Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.

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Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation<br>Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
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Xu, Yuanzhe, and 徐远哲. "Variational analysis for 3D integrated circuit on-chip structures based on process-variation-aware electromagnetic-semiconductor coupledsimulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47047616.

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Neveu, Florian. "Design and implementation of high frequency 3D DC-DC converter." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0133/document.

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L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche est compatible avec une intégration totale sur silicium, mais limitée en terme de densité de puissance. Le second axe est l’utilisation de convertisseurs à inductances, qui pâtissent d’imposants composants passifs. Une augmentation de la fréquence permet de réduire les valeurs des composants passifs. Cependant une augmentation de la fréquence implique une augmentation des pertes par commutation, ce qui est contrebalancé par l’utilisation d’une technologie de fabrication plus avancée. Ces technologies plus avancées souffrent quant à elles de limitations au niveau de leur tension d’utilisation. Convertir une tension de 3,3V vers une tension de 1,2V apparait donc comme un objectif ambitieux, particulièrement dans le cas où les objectifs de taille minimale et de rendement supérieur à 90 % sont visés. Un assemblage 3D des composants actifs et passifs permet de minimiser la surface du système. Un fonctionnement à haute fréquence est aussi considéré, ce qui permet de réduire les valeurs requises pour les composants passifs. Dans le contexte de l’alimentation « on-chip », la technologie silicium est contrainte par les fonctions numériques. Une technologie 40 nm CMOS de type « bulk » est choisie comme cas d’étude pour une tension d’entrée de 3,3 V. Les transistors 3,3 V présentent une figure de mérite médiocre, les transistors 1,2 V sont donc choisis. Ce choix permet en outre de présenter une meilleure compatibilité avec une future intégration sur puce. Une structure cascode utilisant trois transistors en série est étudiée est confrontée à une structure standard à travers des simulations et mesures. Une fréquence de +100MHz est choisie. Une technologie de capacités en tranchées est sélectionnée, et fabriquée sur une puce séparée qui servira d’interposeur et recevra la puce active et les inductances. Les inductances doivent être aussi fabriquées de manière intégrée afin de limiter leur impact sur la surface du convertisseur. Ce travail fournit un objet contenant un convertisseur de type Buck à une phase, avec la puce active retournée (« flip-chip ») sur l’interposeur capacitif, sur lequel une inductance est rapportée. Le démonstrateur une phase est compatible pour une démonstration à phases couplées. Les configurations standard et cascode sont comparées expérimentalement aux fréquences de 100 MHz et 200 MHz. La conception de la puce active est l’élément central de ce travail, l’interposeur capacitif étant fabriqué par IPDiA et les inductances par Tyndall National Institute. L’assemblage des différents sous-éléments est réalisé via des procédés industriels. Un important ensemble de mesures ont été réalisées, montrant les performances du convertisseur DC-DC délivré, ainsi que ses limitations. Un rendement pic de 91,5 % à la fréquence de 100 MHz a été démontré<br>Ultimate integration of power switch-mode converter relies on two research paths. One path experiments the development of switched-capacitor converters. This approach fits silicon integration but is still limited in term of power density. Inductive DC-DC architectures of converters suffer by the values and size of passive components. This limitation is addressed with an increase in frequency. Increase in switching losses in switches leads to consider advanced technological nodes. Consequently, the capability with respect to input voltage is then limited. Handling 3.3 V input voltage to deliver an output voltage in the range 0.6 V to 1.2 V appears a challenging specification for an inductive buck converter if the smallest footprint is targeted at +90 % efficiency. Smallest footprint is approached through a 3D assembly of passive components to the active silicon die. High switching frequency is also considered to shrink the values of passive components as much as possible. In the context of on-chip power supply, the silicon technology is dictated by the digital functions. Complementary Metal-Oxide- Semiconductor (CMOS) bulk C40 is selected as a study case for 3.3 V input voltage. 3.3 V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) features poor figure of merits and 1.2 V standard core, regular devices are preferred. Moreover future integration as an on-chip power supply is more compatible. A three-MOSFET cascode arrangement is experimented and confronted experimentally to a standard buck arrangement in the same technology. The coupled-phase architecture enables to reduce the switching frequency to half the operating frequency of the passive devices. +100MHz is selected for operation of passive devices. CMOS bulk C40 offers Metal-Oxide-Metal (MOM) and MOS capacitors, in density too low to address the decoupling requirements. Capacitors have to be added externally to the silicon die but in a tight combination. Trench-cap technology is selected and capacitors are fabricated on a separate die that will act as an interposer to receive the silicon die as well as the inductors. The work delivers an object containing a one-phase buck converter with the silicon die flip-chipped on a capacitor interposer where a tiny inductor die is reported. The one-phase demonstrator is suitable for coupled-phase demonstration. Standard and cascode configurations are experimentally compared at 100 MHz and 200 MHz switching frequency. A design methodology is presented to cover a system-to-device approach. The active silicon die is the central design part as the capacitive interposer is fabricated by IPDiA and inductors are provided by Tyndall National Institute. The assembly of the converter sub-parts is achieved using an industrial process. The work details a large set of measurements to show the performances of the delivered DC/DC converters as well as its limitations. A 91.5% peak efficiency at 100MHz switching frequency has been demonstrated
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Doan, Nguyen Anh Vu. "Multi-Objective Optimization and Multi-Criteria Decision Aid Applied to the Design of 3D-Stacked Integrated Circuits." Doctoral thesis, Universite Libre de Bruxelles, 2015. https://dipot.ulb.ac.be/dspace/bitstream/2013/216785/4/thesis.pdf.

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Ces dernières décennies, l'industrie en microélectronique s'est astreinte à suivre la loi de Moore pour améliorer la performance des circuits intégrés (Integrated Circuit, IC). Cependant, il sera sans doute impossible de suivre cette loi dans le futur à cause de limitations physiques apparaissant avec la miniaturisation des transistors en-dessous d'un certain seuil si aucune innovatio n'a lieu. Afin de surmonter ce problème, de nouvelles technologies ont émergées, et parmi elles les circuits 3D (3D-Stacked Integrated Circuit, 3D-SIC) ont été proposés pour maintenir l'évolution de la loi de Moore. Les 3D-SIC peuvent apporter de nombreux avantages dans le design des futurs IC mais au coût d'une complexité de design accrue étant donné leur nature fortement combinatoire, et l'optimisation de plusieurs critères conflictuels. Dans cette thèse, nous présentons une première étude des outils qui pourraient aider dans le design de 3D-SIC, en utilisant l'optimisation multi-objectifs (multiobjective optimization, MOO) et l'aide multicritère à la décision (multi-criteria decision aid, MCDA). Notre étude vise l'une des problématiques principales dans le design de 3D-SIC: le partitionnement avec estimation du floorplanning en tenant compte de plusieurs objectifs. Cette thèse montre que l'utilisation d'un paradigme multicritère peut fournir une analyse pertinente et objective du problème. Cela peut permettre une exploration rapide de l'espace de design et une amélioration des flots de conception actuels étant donné qu'il est possible de fournir des informations qualitatives et quantitatives par rapport à l'espace de design qui ne seraient pas disponibles avec les outils actuels. De même, de par sa flexibilité, la MOO peut tenir compte des multiples degrés de liberté des 3D-SIC, ce qui permet plus de possibilités de design qui ne sont généralement pas prises en compte avec les outils actuels. De plus, les algorithmes développés peuvent montrer des propriétés de robustesse même si le problème est complexe. Enfin, appliquer l'aide multicritère à la décision pourrait permettre aux designers de faire des choix pertinents selon un processus transparent.<br>In the past decades, the microelectronic industry has been following the Moore's law to improve the performance of integrated circuits (IC). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold without innovation. In order to overcome this problem, new technologies have emerged, and among them the 3D-Stacked Integrated Circuits (3D-SIC) have been proposed to keep the Moore's momentum alive. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and the optimization of several conflicting criteria. In this thesis, we present a first study of tools that can help the design of 3D-SICs, using mutiobjective optimization (MOO) and multi-criteria decision aid (MCDA). Our study has targeted one of the main issues in the design of 3D-SICs: the partitioning with floorplanning estimation under multiple objectives. This thesis shows that the use of a multi-criteria paradigm can provide relevant and objective analysis of the problem. This can allow a quick design space exploration and an improvement of the current design flows as it is possible to provide qualitative and quantitative information about a design space, that would not be available with current tools. Also, with its flexibility, MOO can cope with the multiple degrees of freedom of 3D-SICs, which enables more design possibilities that are usually not taken into account with current tools. In addition, the developed algorithms can show robustness properties even if the problem is complex. Finally, applying multi-criteria decision aid would allow designers to make relevant choices in a transparent process.<br>Doctorat en Sciences de l'ingénieur<br>info:eu-repo/semantics/nonPublished
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Fkih, Yassine. "Conception en vue du Test des Circuits Intégrés 3D à base de TSVs." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20063/document.

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Depuis plusieurs années, la complexité des circuits intégrés ne cesse d'augmenter : du SOC (System On Chip) vers le SIP (System In Package), et plus récemment les circuits empilés en 3D : les 3D SIC (Stacked Integrated Circuits) à base de TSVs (Through Silicon Vias) interconnectant verticalement les tiers, ou puces, du système. Les 3D SIC présentent de nombreux avantages en termes de facteur de forme, de performance et de consommation mais demandent aussi de relever de nombreux défis en ce qui concerne leur test, étape nécessaire avant la mise en service de ces systèmes complexes. Dans cette thèse, nous nous attachons à définir les infrastructures de test qui permettront de détecter les éventuels défauts apparaissant lors de la fabrication des TSVs ou des différentes puces du système. Nous proposons une solution de BIST (Built In Self Test) pour le test avant empilement des TSVs. Cette solution est basée sur l'utilisation d'oscillateurs en anneaux dont la fréquence d'oscillation dépend des caractéristiques électriques des TSVs. La solution de test proposée permet non seulement la détection de TSVs fautifs mais aussi de renseigner sur le nombre d'éléments défectueux et leur identification. D'autre part, nous proposons une architecture de test 3D basée sur la nouvelle proposition de norme IEEE P1687. Cette infrastructure permet de donner accès aux composants du système 3D avant et après empilement. Elle permet d'autre part de profiter du recyclage des données de test développées et appliquées avant empilement pour chacun des tiers puis ré-appliqués durant ou après l'empilement. Ces travaux aboutissent finalement à l'ouverture d'une nouvelle problématique liée à l'ordonnancement des tests sous contraintes (puissance consommée, température).Mots-clés : test, circuits 3D, TSV, BIST, oscillateur en anneau, architecture de test 3D, IEEE P1687, test avant empilement, test après empilement<br>For several years, the complexity of integrated circuits continues to increase, from SOC (System On Chip) to SIP (System In Package) , and more recently 3D SICs (Stacked Integrated Circuits) based on TSVs (Through Silicon Vias ) that vertically interconnect stacked circuits in a 3D system. 3D SICs have many advantages in terms of small form factor, high performances and low power consumption but have many challenges regarding their test which is a necessary step before the commissioning of these complex systems. In this thesis we focus on defining the test infrastructure that will detect any occurring defects during the manufacturing process of TSVs or the different sacked chips in the system. We propose a BIST (Built In Self Test) solution for TSVs testing before stacking, this solution is based on the use of ring oscillators which their oscillation frequencies depend on the electrical characteristics of the TSVs. The proposed test solution not only allows the detection of faulty TSVs but also gives information about the number of defective TSVs and their location. On the other hand, we propose a 3D DFT (Design For Test) architecture based on the new proposed test standard IEEE P1687. The proposed test architecture provides test access to the components of the 3D system before and after stacking. Also it allows the re-use of recycled test data developed and applied before stacking to each die in the mid-bond and post-bond test levels. This work lead to the opening of a new problem related to the test scheduling under constraints such as: power consumption, temperature.Keywords: test, 3D circuits, TSV, BIST, ring oscillators, 3D DFT architecture, IEEE P1687, pre-bond test, post-bond test
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Books on the topic "3D integrated circuit"

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Integrated interconnect technologies for 3D nanoelectronic systems. Artech House, 2009.

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Three-dimensional molded interconnect devices (3D-MID): Materials, manufacturing, assembly, and applications for injection molded circuit carriers. Hanser Publishers, 2014.

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Khan, Nauman, and Soha Hassoun. Designing TSVs for 3D Integrated Circuits. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-5508-0.

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Khan, Nauman. Designing TSVs for 3D Integrated Circuits. Springer New York, 2013.

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3D IC stacking technology. McGraw-Hill Professional, 2011.

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Salah, Khaled, Yehea Ismail, and Alaa El-Rouby. Arbitrary Modeling of TSVs for 3D Integrated Circuits. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-07611-9.

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Electrical modeling and design for 3D integration: 3D integrated circuits and packaging signal integrity, power integrity, and EMC. Wiley-IEEE Press, 2011.

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Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2013.

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Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-9542-1.

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Japan) International Workshop on Stress-Induced Phenomena in Microelectronics (12th 2012 Kyoto. Stress Induced Phenomena and Reliability in 3D Microelectronics: Kyoto, Japan, 28-30 May 2012. Edited by Ho P. S. editor. AIP Publishing, 2014.

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Book chapters on the topic "3D integrated circuit"

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Checka, Nisha. "Circuit Architectures for 3D Integration." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_13.

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Burns, James, Brian Aull, Robert Berger, et al. "An SOI-Based 3D Circuit Integration Technology." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_8.

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Takahashi, Hiroshi, Senling Wang, Shuichi Kameyama, et al. "Trends in 3D Integrated Circuit (3D-IC) Testing Technology." In Three-Dimensional Integration of Semiconductors. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-18675-7_8.

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Li, Li. "Three-Dimensional System-in-Package for Application-Specific Integrated Circuit and Three-Dimensional Dynamic Random-Access Memory Integration." In 3D Integration in VLSI Circuits. CRC Press, 2018. http://dx.doi.org/10.1201/9781315200699-2.

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Belleville, Marc. "3D Integration for Digital and Imagers Circuits: Opportunities and Challenges." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17752-1_31.

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Arnaldo, Ignacio, José L. Risco-Martín, José L. Ayala, and J. Ignacio Hidalgo. "Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_2.

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Zanini, Francesco, David Atienza, and Giovanni De Micheli. "Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_34.

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Ebi, Thomas, Holm Rauchfuss, Andreas Herkersdorf, and Jörg Henkel. "Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_12.

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Rahmani, Amir-Mohammad, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen. "Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_28.

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Patti, Robert S. "3D Memory." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_12.

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Conference papers on the topic "3D integrated circuit"

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Ehsan, Md Amimul, Zhen Zhou, and Yang Yi. "Neuromorphic 3D Integrated Circuit." In GLSVLSI '17: Great Lakes Symposium on VLSI 2017. ACM, 2017. http://dx.doi.org/10.1145/3060403.3060470.

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Pathak, Divya, and Ioannis Savidis. "Power supply voltage detection and clamping circuit for 3-D integrated circuits." In 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2014. http://dx.doi.org/10.1109/s3s.2014.7028202.

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Jieliang Lu, Qin Wang, Jing Xie, and Zhigang Mao. "TSVs-aware floorplanning for 3D integrated circuit." In 2013 IEEE 10th International Conference on ASIC (ASICON 2013). IEEE, 2013. http://dx.doi.org/10.1109/asicon.2013.6812068.

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Dai, Yong-sheng, Xiang-zhi Chen, Mao-ya Yang, and Jian-hua Zhu. "Researches of UWB MMIC control circuits and LTCC 3D integrated circuit technology." In 2016 International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2016. http://dx.doi.org/10.1109/icam.2016.7813566.

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Rahman, Mostafizur, Santosh Khasanvis, Jiajun Shi, Mingyu Li, and Csaba Andras Moritz. "Fine-grained 3-D integrated circuit fabric using vertical nanowires." In 2015 International 3D Systems Integration Conference (3DIC). IEEE, 2015. http://dx.doi.org/10.1109/3dic.2015.7334563.

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Chen, Yung-Tin, and Steve Radigan. "Pushing KrF photolithography limit for 3D integrated circuit." In Microlithography 2004, edited by Bruce W. Smith. SPIE, 2004. http://dx.doi.org/10.1117/12.544386.

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Levine, Zachary H., and Steven Grantham. "X-Ray Tomography of Integrated Circuit Interconnects: Past and Future." In ISTFA 2001. ASM International, 2001. http://dx.doi.org/10.31399/asm.cp.istfa2001p0011.

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Abstract A scanning transmission x-ray microscope was used to perform x-ray tomography of integrated circuit interconnects. Reconstructions of test circuits were made with 140 nm 3D resolution in the best case.
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Yuan Xie and Yuchun Ma. "Design space exploration for 3D integrated circuits." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4735042.

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Lau, John H., Ying Ying Lim, Teck Guan Lim, et al. "Design and analysis of 3D stacked optoelectronics on optical printed circuit boards." In Integrated Optoelectronic Devices 2008, edited by Alexei L. Glebov and Ray T. Chen. SPIE, 2008. http://dx.doi.org/10.1117/12.764032.

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Li, Jing, and Hiroshi Miyashita. "Post-placement Thermal Via Planning for 3D Integrated Circuit." In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/apccas.2006.342144.

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Reports on the topic "3D integrated circuit"

1

Chu, D., and D. W. Palmer. 3D packaging for integrated circuit systems. Office of Scientific and Technical Information (OSTI), 1996. http://dx.doi.org/10.2172/420397.

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Shakouri, Ali, Bin Liu, Patrick Abraham, and John E. Bowers. 3D Photonic Integrated Circuits for WDM Applications. Defense Technical Information Center, 1998. http://dx.doi.org/10.21236/ada461796.

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Ahmed, Mohammad. Early Layout Design Exploration in TSV-based 3D Integrated Circuits. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.5509.

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