Academic literature on the topic '3D integrated circuit'
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Journal articles on the topic "3D integrated circuit"
Koo, Jae-Mo, Sungjun Im, Linan Jiang, and Kenneth E. Goodson. "Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures." Journal of Heat Transfer 127, no. 1 (2005): 49–58. http://dx.doi.org/10.1115/1.1839582.
Full textWang, Shaoxi, Yue Yin, Chenxia Hu, and Pouya Rezai. "3D Integrated Circuit Cooling with Microfluidics." Micromachines 9, no. 6 (2018): 287. http://dx.doi.org/10.3390/mi9060287.
Full textKim, Bruce, Sukeshwar Kannan, Anurag Gupta, and Naga Sai Evana. "Modeling and Simulation of 3D MEMS Integrated RF Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 002006–27. http://dx.doi.org/10.4071/2012dpc-wp35.
Full textIndrusiak, Leandro Soares, and Ricardo Augusto da Luz Reis. "3D integrated circuit layout visualization using VRML." Future Generation Computer Systems 17, no. 5 (2001): 503–11. http://dx.doi.org/10.1016/s0167-739x(00)00036-4.
Full textAndras Moritz, Csaba. "Architecting 3D integrated circuit fabrics at nanoscale." Research Outreach, no. 108 (July 10, 2019): 122–25. http://dx.doi.org/10.32907/ro-108-122125.
Full textBehroozpour, Behnam, Phillip A. M. Sandborn, Niels Quack, et al. "Electronic-Photonic Integrated Circuit for 3D Microimaging." IEEE Journal of Solid-State Circuits 52, no. 1 (2017): 161–72. http://dx.doi.org/10.1109/jssc.2016.2621755.
Full textLi, Mingyu, Jiajun Shi, Mostafizur Rahman, Santosh Khasanvis, Sachin Bhat, and Csaba Andras Moritz. "Skybridge-3D-CMOS: A Fine-Grained 3D CMOS Integrated Circuit Technology." IEEE Transactions on Nanotechnology 16, no. 4 (2017): 639–52. http://dx.doi.org/10.1109/tnano.2017.2700626.
Full textPetrosyants, Konstantin O., and Nikita I. Ryabov. "Quasi-3D Thermal Simulation of Integrated Circuit Systems in Packages." Energies 13, no. 12 (2020): 3054. http://dx.doi.org/10.3390/en13123054.
Full textSabbavarapu, Srinivas, Amit Acharyya, P. Balasubramanian, and C. Ramesh Reddy. "Fast 3D Integrated Circuit Placement Methodology using Merging Technique." Defence Science Journal 69, no. 3 (2019): 217–22. http://dx.doi.org/10.14429/dsj.69.14410.
Full textHubbard, Joshua D., Ruben Acevedo, Kristen M. Edwards, et al. "Fully 3D-printed soft robots with integrated fluidic circuitry." Science Advances 7, no. 29 (2021): eabe5257. http://dx.doi.org/10.1126/sciadv.abe5257.
Full textDissertations / Theses on the topic "3D integrated circuit"
Sekar, Deepak Chandra. "Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26562.
Full textCommittee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.
Full textContreras, Andres A. "Micronetworking: Reliable Communication on 3D Integrated Circuits." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/728.
Full textZaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.
Full textKim, Dae Hyun. "Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43642.
Full textKnechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.
Full textDreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
Xu, Yuanzhe, and 徐远哲. "Variational analysis for 3D integrated circuit on-chip structures based on process-variation-aware electromagnetic-semiconductor coupledsimulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47047616.
Full textNeveu, Florian. "Design and implementation of high frequency 3D DC-DC converter." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0133/document.
Full textUltimate integration of power switch-mode converter relies on two research paths. One path experiments the development of switched-capacitor converters. This approach fits silicon integration but is still limited in term of power density. Inductive DC-DC architectures of converters suffer by the values and size of passive components. This limitation is addressed with an increase in frequency. Increase in switching losses in switches leads to consider advanced technological nodes. Consequently, the capability with respect to input voltage is then limited. Handling 3.3 V input voltage to deliver an output voltage in the range 0.6 V to 1.2 V appears a challenging specification for an inductive buck converter if the smallest footprint is targeted at +90 % efficiency. Smallest footprint is approached through a 3D assembly of passive components to the active silicon die. High switching frequency is also considered to shrink the values of passive components as much as possible. In the context of on-chip power supply, the silicon technology is dictated by the digital functions. Complementary Metal-Oxide- Semiconductor (CMOS) bulk C40 is selected as a study case for 3.3 V input voltage. 3.3 V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) features poor figure of merits and 1.2 V standard core, regular devices are preferred. Moreover future integration as an on-chip power supply is more compatible. A three-MOSFET cascode arrangement is experimented and confronted experimentally to a standard buck arrangement in the same technology. The coupled-phase architecture enables to reduce the switching frequency to half the operating frequency of the passive devices. +100MHz is selected for operation of passive devices. CMOS bulk C40 offers Metal-Oxide-Metal (MOM) and MOS capacitors, in density too low to address the decoupling requirements. Capacitors have to be added externally to the silicon die but in a tight combination. Trench-cap technology is selected and capacitors are fabricated on a separate die that will act as an interposer to receive the silicon die as well as the inductors. The work delivers an object containing a one-phase buck converter with the silicon die flip-chipped on a capacitor interposer where a tiny inductor die is reported. The one-phase demonstrator is suitable for coupled-phase demonstration. Standard and cascode configurations are experimentally compared at 100 MHz and 200 MHz switching frequency. A design methodology is presented to cover a system-to-device approach. The active silicon die is the central design part as the capacitive interposer is fabricated by IPDiA and inductors are provided by Tyndall National Institute. The assembly of the converter sub-parts is achieved using an industrial process. The work details a large set of measurements to show the performances of the delivered DC/DC converters as well as its limitations. A 91.5% peak efficiency at 100MHz switching frequency has been demonstrated
Doan, Nguyen Anh Vu. "Multi-Objective Optimization and Multi-Criteria Decision Aid Applied to the Design of 3D-Stacked Integrated Circuits." Doctoral thesis, Universite Libre de Bruxelles, 2015. https://dipot.ulb.ac.be/dspace/bitstream/2013/216785/4/thesis.pdf.
Full textIn the past decades, the microelectronic industry has been following the Moore's law to improve the performance of integrated circuits (IC). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold without innovation. In order to overcome this problem, new technologies have emerged, and among them the 3D-Stacked Integrated Circuits (3D-SIC) have been proposed to keep the Moore's momentum alive. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and the optimization of several conflicting criteria. In this thesis, we present a first study of tools that can help the design of 3D-SICs, using mutiobjective optimization (MOO) and multi-criteria decision aid (MCDA). Our study has targeted one of the main issues in the design of 3D-SICs: the partitioning with floorplanning estimation under multiple objectives. This thesis shows that the use of a multi-criteria paradigm can provide relevant and objective analysis of the problem. This can allow a quick design space exploration and an improvement of the current design flows as it is possible to provide qualitative and quantitative information about a design space, that would not be available with current tools. Also, with its flexibility, MOO can cope with the multiple degrees of freedom of 3D-SICs, which enables more design possibilities that are usually not taken into account with current tools. In addition, the developed algorithms can show robustness properties even if the problem is complex. Finally, applying multi-criteria decision aid would allow designers to make relevant choices in a transparent process.
Doctorat en Sciences de l'ingénieur
info:eu-repo/semantics/nonPublished
Fkih, Yassine. "Conception en vue du Test des Circuits Intégrés 3D à base de TSVs." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20063/document.
Full textFor several years, the complexity of integrated circuits continues to increase, from SOC (System On Chip) to SIP (System In Package) , and more recently 3D SICs (Stacked Integrated Circuits) based on TSVs (Through Silicon Vias ) that vertically interconnect stacked circuits in a 3D system. 3D SICs have many advantages in terms of small form factor, high performances and low power consumption but have many challenges regarding their test which is a necessary step before the commissioning of these complex systems. In this thesis we focus on defining the test infrastructure that will detect any occurring defects during the manufacturing process of TSVs or the different sacked chips in the system. We propose a BIST (Built In Self Test) solution for TSVs testing before stacking, this solution is based on the use of ring oscillators which their oscillation frequencies depend on the electrical characteristics of the TSVs. The proposed test solution not only allows the detection of faulty TSVs but also gives information about the number of defective TSVs and their location. On the other hand, we propose a 3D DFT (Design For Test) architecture based on the new proposed test standard IEEE P1687. The proposed test architecture provides test access to the components of the 3D system before and after stacking. Also it allows the re-use of recycled test data developed and applied before stacking to each die in the mid-bond and post-bond test levels. This work lead to the opening of a new problem related to the test scheduling under constraints such as: power consumption, temperature.Keywords: test, 3D circuits, TSV, BIST, ring oscillators, 3D DFT architecture, IEEE P1687, pre-bond test, post-bond test
Books on the topic "3D integrated circuit"
Integrated interconnect technologies for 3D nanoelectronic systems. Artech House, 2009.
Three-dimensional molded interconnect devices (3D-MID): Materials, manufacturing, assembly, and applications for injection molded circuit carriers. Hanser Publishers, 2014.
Khan, Nauman, and Soha Hassoun. Designing TSVs for 3D Integrated Circuits. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-5508-0.
Full textKhan, Nauman. Designing TSVs for 3D Integrated Circuits. Springer New York, 2013.
3D IC stacking technology. McGraw-Hill Professional, 2011.
Salah, Khaled, Yehea Ismail, and Alaa El-Rouby. Arbitrary Modeling of TSVs for 3D Integrated Circuits. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-07611-9.
Full textElectrical modeling and design for 3D integration: 3D integrated circuits and packaging signal integrity, power integrity, and EMC. Wiley-IEEE Press, 2011.
Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2013.
Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-9542-1.
Full textJapan) International Workshop on Stress-Induced Phenomena in Microelectronics (12th 2012 Kyoto. Stress Induced Phenomena and Reliability in 3D Microelectronics: Kyoto, Japan, 28-30 May 2012. Edited by Ho P. S. editor. AIP Publishing, 2014.
Book chapters on the topic "3D integrated circuit"
Checka, Nisha. "Circuit Architectures for 3D Integration." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_13.
Full textBurns, James, Brian Aull, Robert Berger, et al. "An SOI-Based 3D Circuit Integration Technology." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_8.
Full textTakahashi, Hiroshi, Senling Wang, Shuichi Kameyama, et al. "Trends in 3D Integrated Circuit (3D-IC) Testing Technology." In Three-Dimensional Integration of Semiconductors. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-18675-7_8.
Full textLi, Li. "Three-Dimensional System-in-Package for Application-Specific Integrated Circuit and Three-Dimensional Dynamic Random-Access Memory Integration." In 3D Integration in VLSI Circuits. CRC Press, 2018. http://dx.doi.org/10.1201/9781315200699-2.
Full textBelleville, Marc. "3D Integration for Digital and Imagers Circuits: Opportunities and Challenges." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17752-1_31.
Full textArnaldo, Ignacio, José L. Risco-Martín, José L. Ayala, and J. Ignacio Hidalgo. "Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_2.
Full textZanini, Francesco, David Atienza, and Giovanni De Micheli. "Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_34.
Full textEbi, Thomas, Holm Rauchfuss, Andreas Herkersdorf, and Jörg Henkel. "Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_12.
Full textRahmani, Amir-Mohammad, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen. "Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_28.
Full textPatti, Robert S. "3D Memory." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_12.
Full textConference papers on the topic "3D integrated circuit"
Ehsan, Md Amimul, Zhen Zhou, and Yang Yi. "Neuromorphic 3D Integrated Circuit." In GLSVLSI '17: Great Lakes Symposium on VLSI 2017. ACM, 2017. http://dx.doi.org/10.1145/3060403.3060470.
Full textPathak, Divya, and Ioannis Savidis. "Power supply voltage detection and clamping circuit for 3-D integrated circuits." In 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2014. http://dx.doi.org/10.1109/s3s.2014.7028202.
Full textJieliang Lu, Qin Wang, Jing Xie, and Zhigang Mao. "TSVs-aware floorplanning for 3D integrated circuit." In 2013 IEEE 10th International Conference on ASIC (ASICON 2013). IEEE, 2013. http://dx.doi.org/10.1109/asicon.2013.6812068.
Full textDai, Yong-sheng, Xiang-zhi Chen, Mao-ya Yang, and Jian-hua Zhu. "Researches of UWB MMIC control circuits and LTCC 3D integrated circuit technology." In 2016 International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2016. http://dx.doi.org/10.1109/icam.2016.7813566.
Full textRahman, Mostafizur, Santosh Khasanvis, Jiajun Shi, Mingyu Li, and Csaba Andras Moritz. "Fine-grained 3-D integrated circuit fabric using vertical nanowires." In 2015 International 3D Systems Integration Conference (3DIC). IEEE, 2015. http://dx.doi.org/10.1109/3dic.2015.7334563.
Full textChen, Yung-Tin, and Steve Radigan. "Pushing KrF photolithography limit for 3D integrated circuit." In Microlithography 2004, edited by Bruce W. Smith. SPIE, 2004. http://dx.doi.org/10.1117/12.544386.
Full textLevine, Zachary H., and Steven Grantham. "X-Ray Tomography of Integrated Circuit Interconnects: Past and Future." In ISTFA 2001. ASM International, 2001. http://dx.doi.org/10.31399/asm.cp.istfa2001p0011.
Full textYuan Xie and Yuchun Ma. "Design space exploration for 3D integrated circuits." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4735042.
Full textLau, John H., Ying Ying Lim, Teck Guan Lim, et al. "Design and analysis of 3D stacked optoelectronics on optical printed circuit boards." In Integrated Optoelectronic Devices 2008, edited by Alexei L. Glebov and Ray T. Chen. SPIE, 2008. http://dx.doi.org/10.1117/12.764032.
Full textLi, Jing, and Hiroshi Miyashita. "Post-placement Thermal Via Planning for 3D Integrated Circuit." In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/apccas.2006.342144.
Full textReports on the topic "3D integrated circuit"
Chu, D., and D. W. Palmer. 3D packaging for integrated circuit systems. Office of Scientific and Technical Information (OSTI), 1996. http://dx.doi.org/10.2172/420397.
Full textShakouri, Ali, Bin Liu, Patrick Abraham, and John E. Bowers. 3D Photonic Integrated Circuits for WDM Applications. Defense Technical Information Center, 1998. http://dx.doi.org/10.21236/ada461796.
Full textAhmed, Mohammad. Early Layout Design Exploration in TSV-based 3D Integrated Circuits. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.5509.
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