Relevant bibliographies by topics / 3D integrated circuits

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic '3D integrated circuits'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 June 2025

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Journal articles on the topic "3D integrated circuits"

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Koo, Jae-Mo, Sungjun Im, Linan Jiang, and Kenneth E. Goodson. "Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures." Journal of Heat Transfer 127, no. 1 (2005): 49–58. http://dx.doi.org/10.1115/1.1839582.

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The semiconductor community is developing three-dimensional circuits that integrate logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical systems. These three-dimensional (3D) circuits pose important challenges for thermal management due to the increasing heat load per unit surface area. This paper theoretically studies 3D circuit cooling by means of an integrated microchannel network. Predictions are based on thermal models solving one-dimensional conservation equations for boiling convection along microchannels, and are consistent with past data obtained from straight channels. The model is combined within a thermal resistance network to predict temperature distributions in logic and memory. The calculations indicate that a layer of integrated microchannel cooling can remove heat densities up to 135W/cm2 within a 3D architecture with a maximum circuit temperature of 85°C. The cooling strategy described in this paper will enable 3D circuits to include greater numbers of active levels while exposing external surface area for functional signal transmission.
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Pletea, Ionica-Marcela. "Methodology and backend flow optimization for 3D." Journal of Engineering Science 31, no. 2 (2024): 39–47. https://doi.org/10.52326/jes.utm.2024.31(2).04.

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The article deals with the complexity of the workflow used when integrated circuits are implemented using 2D electronic design automation (EDA) tools and adapting the workflow for 3D integrated circuits. If some issues are not identified promptly in the workflow, the working time to produce an integrated circuit is increased. By analyzing and refining workflow, identifying bottlenecks and early problems in a design, the optimization process will ensure an error-minimized trajectory from synthesis to final design prepared for manufacturing. Considering all the details at every stage of the working flow will help the backend designer to solve problems faster and save time. It was created detailed scripts for automatization of the process at every stage including floorplan, power plan, placement, clock tree synthesis, routing and all physical and logical analysis. The workflow was optimized using loops at all levels, extracting important information at every level and improving the process of working. Moreover, optimization techniques contribute significantly to precision and quality in design implementation. This working flow can be used to implement 3D integrated circuits with automated 2D tools from Synopsis.
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Li, Chengxuan. "A review of physical heat dissipation methods for 3D integrated technology." Applied and Computational Engineering 89, no. 1 (2024): 43–47. http://dx.doi.org/10.54254/2755-2721/89/20241052.

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Three-dimensional integrated circuits have higher integration than two-dimensional integrated circuits, and can obtain higher performance and lower power consumption in a certain space. In order to fulfill higher efficiency, thermal management becomes particularly important in 3D integration technology. However, the traditional heat dissipation method cannot satisfy the heat dissipation needs of three-dimensional integrated circuits, which require better heat dissipation methods to be developed. This paper introduces the realization of three-dimensional integrated circuit using silicon via (TSV) technology, which allows the chip to be vertically stacked to transmit information. This paper summarizes the research methods and findings of three-dimensional integrated circuit heat dissipation in recent years, including thermal through silicon via (TTSV) and microchannel cooling. It also emphasizes the advantages and disadvantages of both mehods, and the challenges faced in current research via an overview. The future research trend for both heat dissipation methods mainly consists of combining special algorithms to achieve thermal-electrical codesign and thermal management of three-dimensional integrated circuits.
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Băjenescu, Titu-Marius I. "3D MICROPACKAGING OF INTEGRATED CIRCUITS." Journal of Engineering Science XXVII (1) (March 15, 2020): 28–35. https://doi.org/10.5281/zenodo.3713360.

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A major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also, reliability concerns will be extremely important: electromigration and stress-migration. This paper presents some actual problems and reliability challenges in 3D IC packaging technology. It shows how different architectures have evolved to meet the specific needs of different markets: Multi Chip Module (MCP); Multipackage module (MPM); Embedded SIP modules; SIP package-on-package (PoP) modules; EMIB (Embedded Multi-die Interconnect Bridge); Silicon-based SIP-Module; 3D-TSV stacked module; SIP variants with combinations of wideband and flip-chip interconnects. Causes of blockages and failure mechanisms, as well as problems with predictive reliability, which will need to be developed in the coming years, are analysed.
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Kim, Bruce, Sukeshwar Kannan, Anurag Gupta, and Naga Sai Evana. "Modeling and Simulation of 3D MEMS Integrated RF Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 002006–27. http://dx.doi.org/10.4071/2012dpc-wp35.

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Today's integrated packaging consists of analog, mixed-signal and RF circuits. These integrated packages are now available in 3-D which makes it extremely difficult to test for defects and their circuit functionalities. This paper provides 3D MEMS integrated packaging which provides self testing and calibrations to overcome process defects and out of spec circuits inside the package making the package self heal itself in case of faults and defects. We have worked on TSV based 3D packaging with MEMS switches to perform self calibrations. We developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated on an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. We used arrays of MEMS switches to perform self testing. We have considered a low noise amplifier as the reference RF circuit which operates between 4 GHz and 6 GHz. The entire validation of the design using test technique and self-calibration of the RF circuit is automated using the calibration algorithm. The paper presents defects in TSV due to mechanical stress and thermal changes.
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Pletea, Ionica-Marcela. "METHODOLOGY AND BACKEND FLOW OPTIMIZATION FOR 3D." JOURNAL OF ENGINEERING SCIENCE 31, no. 2 (2024): 39–47. http://dx.doi.org/10.52326/jes.utm.2024.31(2).04.

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The article deals with the complexity of the workflow used when integrated circuits are implemented using 2D electronic design automation (EDA) tools and adapting the workflow for 3D integrated circuits. If some issues are not identified promptly in the workflow, the working time to produce an integrated circuit is increased. By analyzing and refining workflow, identifying bottlenecks and early problems in a design, the optimization process will ensure an error-minimized trajectory from synthesis to final design prepared for manufacturing. Considering all the details at every stage of the working flow will help the backend designer to solve problems faster and save time. It was created detailed scripts for automatization of the process at every stage including floorplan, power plan, placement, clock tree synthesis, routing and all physical and logical analysis. The workflow was optimized using loops at all levels, extracting important information at every level and improving the process of working. Moreover, optimization techniques contribute significantly to precision and quality in design implementation. This working flow can be used to implement 3D integrated circuits with automated 2D tools from Synopsis.
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Lee, Hsien-Hsin S., and Krishnendu Chakrabarty. "Test Challenges for 3D Integrated Circuits." IEEE Design & Test of Computers 26, no. 5 (2009): 26–35. http://dx.doi.org/10.1109/mdt.2009.125.

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Xiang, Chao, Warren Jin, Osama Terra, et al. "3D integration enables ultralow-noise isolator-free lasers in silicon photonics." Nature 620, no. 7972 (2023): 78–85. http://dx.doi.org/10.1038/s41586-023-06251-w.

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AbstractPhotonic integrated circuits are widely used in applications such as telecommunications and data-centre interconnects1–5. However, in optical systems such as microwave synthesizers6, optical gyroscopes7 and atomic clocks8, photonic integrated circuits are still considered inferior solutions despite their advantages in size, weight, power consumption and cost. Such high-precision and highly coherent applications favour ultralow-noise laser sources to be integrated with other photonic components in a compact and robustly aligned format—that is, on a single chip—for photonic integrated circuits to replace bulk optics and fibres. There are two major issues preventing the realization of such envisioned photonic integrated circuits: the high phase noise of semiconductor lasers and the difficulty of integrating optical isolators directly on-chip. Here we challenge this convention by leveraging three-dimensional integration that results in ultralow-noise lasers with isolator-free operation for silicon photonics. Through multiple monolithic and heterogeneous processing sequences, direct on-chip integration of III–V gain medium and ultralow-loss silicon nitride waveguides with optical loss around 0.5 decibels per metre are demonstrated. Consequently, the demonstrated photonic integrated circuit enters a regime that gives rise to ultralow-noise lasers and microwave synthesizers without the need for optical isolators, owing to the ultrahigh-quality-factor cavity. Such photonic integrated circuits also offer superior scalability for complex functionalities and volume production, as well as improved stability and reliability over time. The three-dimensional integration on ultralow-loss photonic integrated circuits thus marks a critical step towards complex systems and networks on silicon.
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Herraiz, Darío, Angel Belenguer, Marcos Fernandez, Santiago Cogollos, Héctor Esteban, and Vicente E. Boria. "Simple and Easily Connectable Transition from Empty Substrate-Integrated Waveguide to a 3D Printed Rectangular Waveguide." Applied Sciences 13, no. 21 (2023): 11698. http://dx.doi.org/10.3390/app132111698.

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3D printing is one of the most promising manufacturing methods in the most developed technological fields, including microwave hardware fabrication. On the other hand, the well-known manufacturing methods of planar substrate integrated circuits allow high-quality prototypes to be made at low cost and with mass production capabilities. The combination of both manufacturing methods, 2D or 2.5D (substrate integrated circuits) and 3D (3D printed structures), will allow us to take advantage of the main strengths of each technology and minimise disadvantages. In this article, for the first time, a transition structure between the Empty Substrate-Integrated Waveguide (ESIW) technology—a planar waveguide integrated on a printed circuit board—and a standard rectangular waveguide manufactured by 3D printing is proposed. This transition will make it possible to combine planar circuits with 3D structures, thus taking advantage of the benefits of both types of technologies. The fabricated prototype presents low losses (0.6 dB for the transmission coefficient and 15 dB for reflection coefficient), good electrical response (very flat), and simultaneously good mechanical stability and robustness to manufacturing and assembly errors. The proposed design for this transition piece is easily realisable for a wide range of affordable 3D printers. Repeatability is guaranteed and the proposed transition allows us to combine different SIC structures to 3D printed circuits. Hence, this transition will enable advancements in the fabrication of microwave devices, particularly with regard to satellite communications.
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Hu, Han. "Navigating The Integrated Circuit Industry: Definitions, Evolution, Innovations, And Challenges." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 226–31. http://dx.doi.org/10.54097/fb9z0110.

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Now, the integrated circuit (IC) industry is experiencing rapid growth, and some of its associated technologies play vital roles in our everyday lives. This paper aims to provide comprehensive insights into the entire IC industry by elaborating on various aspects. First and foremost, it elucidates the definition, development history, and current status of integrated circuits (ICs). Subsequently, it delves into intricate details regarding three state-of-the-art technologies linked to ICs, all of which are conveyed with their full names for clarity: Integrated Circuits in Silicon Germanium (SiGe) Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) for Millimeter-Wave and Terahertz Bioanalyzers, 3D Packaging for Heterogeneous Integration, and, once again, 3D Packaging for Heterogeneous Integration. To conclude, this paper provides an in-depth exploration of the present challenges faced by the integrated circuit industry and the prospective hurdles that could impact the industry's future trajectory. By reading this paper, you can swiftly gain a comprehensive understanding of integrated circuits, covering aspects such as their definition, historical evolution, current status, cutting-edge technologies, and the prevailing challenges that demand attention.
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Dissertations / Theses on the topic "3D integrated circuits"

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Contreras, Andres A. "Micronetworking: Reliable Communication on 3D Integrated Circuits." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/728.

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The potential failure in through-silicon vias (TSVs) still poses a challenge in trying to extend the useful life of a 3D integrated circuit (IC). A model is proposed to mitigate the communication problem in 3D integrated circuits caused by the breaks at the TSVs. We provide the details of a low-complexity network that takes advantages of redundant TSVs to make it possible to re-route around breaks and maintain effective communication between layers. Different configurations for the micronetwork are analyzed and discussed. We also present an evaluation of the micronetwork's performance, which turns out to be quite promising, based on several Monte Carlo simulations. Finally, we provide some directions for future research on the subject.
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Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.

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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects. This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential. A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
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Sekar, Deepak Chandra. "Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26562.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Mineo, Christopher Alexander. "Clock Tree Insertion and Verification for 3D Integrated Circuits." NCSU, 2005. http://www.lib.ncsu.edu/theses/available/etd-09072005-193841/.

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The use of three dimensional chip fabrication technologies has emerged as a solution to the difficulties involved with the continued scaling of bulk silicon devices. While the technology exists, it is undervalued and underutilized largely due to the design and verification challenges a complex 3D design presents. This work presents a clock tree insertion and timing verification methodology for three dimensional integrated circuits (3DIC). It has been designed in the context of and incorporated into the 3DIC design methodology also developed within our research group. The 3DIC verification methodology serves as an efficient means to perform all setup and hold timing checks harnessing the power of existing commercial chip design and verification tools. A novel approach is presented in which the multi-die design is temporarily transformed to appear as a traditional 2D design to the commercial tools for verification purposes. Various parasitic extraction algorithms are examined, and we present a method for performing accurate 3D parasitic extraction for timing purposes. We offer theoretical insight into the optimization of a 3D clock tree for power savings and coupling-induced delay minimization. A practical example of the 3DIC design and verification flow is detailed through the explanation of our research group?s test chip, a nearly 140,000 cell 3D fast Fourier transform chip currently awaiting fabrication at MIT?s Lincoln Labs.
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Lewis, Dean Leon. "Design for pre-bond testability in 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45756.

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In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.
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Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.

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Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation<br>Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
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Athikulwongse, Krit. "Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45783.

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The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.
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Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.

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For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.
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Alam, Syed Mohiul 1975. "ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8953.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (p. 107-112).<br>Recent developments in semiconductor processing technology has enabled the fabrication of a single integrated circuit (IC) with multiple device-interconnect layers or wafers stacked on each other. This approach is commonly referred to as the 3D integration of ICs. Although there has been significant research on the impact of 3D integration on chip size, interconnect delay, and overall system performance, the reliability issues in the 3D interconnect arrays are largely unknown. In this research, a novel Reliability Computer Aided Design (RCAD) tool ERNI-3D has been developed for reliability analysis of interconnects in a 3D IC. Using this tool, circuit designers can get interactive feedback on the reliability of their circuits associated with electromigration, 3D bonding, and joule heating. Based on a joint probability distribution, a full-chip reliability model combines all reliability figures from different components to give a useful number for the designers' reference. This initial version of ERNI-3D treats 3D circuits with two wafers or device-interconnect layers in the stack. However, the data-structures and algorithms in the tool are generic enough to make it compatible with 3D circuits with more than two device-interconnect layers, and to allow incorporation of more sophisticated reliability models in the future. Since 3D integration technology is not yet widespread, and no CAD tool supports IC layouts for such a technology, a novel layout methodology has been implemented in 3DMagic by extending MAGIC, a widely used layout editor in academia. Apart from the CAD tool work, this research has also led to the development of, and interesting experiments with, some 3D circuits for testing ERNI-3D. The test circuits investigated are a 3D 8-bit adder and an FPGA.<br>by Syed Mohiul Alam.<br>S.M.
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Pourbakhsh, Seyed Alireza. "Dummy TSV-Based Timing Optimization for 3D On-Chip Memory." Thesis, North Dakota State University, 2016. https://hdl.handle.net/10365/29093.

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Design and fabrication of three-dimensional (3D) ICs is one the newest and hottest trends in semiconductor manufacturing industry. In 3D ICs, multiple 2D silicon dies are stacked vertically, and through silicon vias (TSVs) are used to transfer power and signals between different dies. The electrical characteristic of TSVs can be modeled with equivalent circuits consisted of passive elements. In this thesis, we use “dummy” TSVs as electrical delay units in 3D SRAMs. Our results prove that dummy TSVs based delay units are as effective as conventional delay cells in performance, increase the operational frequency of SRAM up to 110%, reduce the usage of silicon area up to 88%, induce negligible power overhead, and improve robustness against voltage supply variation and fluctuation.
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Books on the topic "3D integrated circuits"

1

Khan, Nauman, and Soha Hassoun. Designing TSVs for 3D Integrated Circuits. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-5508-0.

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Khan, Nauman. Designing TSVs for 3D Integrated Circuits. Springer New York, 2013.

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Yi, Yasha. From 2D to 3D Photonic Integrated Circuits. Springer Nature Switzerland, 2026. https://doi.org/10.1007/978-3-031-91508-6.

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Salah, Khaled, Yehea Ismail, and Alaa El-Rouby. Arbitrary Modeling of TSVs for 3D Integrated Circuits. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-07611-9.

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E, Garrou Philip, Bower Christopher Andrew, and Ramm Peter, eds. Handbook of 3D integration: Technology and applications of 3D integrated circuits. Wiley-VCH, 2008.

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Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-9542-1.

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Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. Springer New York, 2013.

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Japan) International Workshop on Stress-Induced Phenomena in Microelectronics (12th 2012 Kyoto. Stress Induced Phenomena and Reliability in 3D Microelectronics: Kyoto, Japan, 28-30 May 2012. Edited by Ho P. S. editor. AIP Publishing, 2014.

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Hoi-Jun, Yoo, ed. Mobile graphics 3D SoC: From algorithm to chip. John Wiley, 2010.

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Sithu, Kyaw Aung, ed. Irrlicht 1.7 realtime 3D engine: Beginner's guide : create complete 2D and 3D applications with this cross-platform, high performance engine. Packt Publishing, 2011.

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Book chapters on the topic "3D integrated circuits"

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Patti, Robert S. "3D Memory." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_12.

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Petti, Christopher, S. Brad Herner, and Andrew Walker. "Monolithic 3D Integrated Circuits." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_2.

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Young, Albert M., and Steven J. Koester. "3D Process Technology Considerations." In Integrated Circuits and Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0784-4_2.

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Cong, Jason, and Yuchun Ma. "Thermal-Aware 3D Floorplan." In Integrated Circuits and Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0784-4_4.

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Cong, Jason, and Guojie Luo. "Thermal-Aware 3D Placement." In Integrated Circuits and Systems. Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-0784-4_5.

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Henker, Ronny, Guido Belfiore, Laszlo Szilagyi, and Frank Ellinger. "Integrated Circuits for 3D Photonic Transceivers." In 3D Stacked Chips. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-20481-9_16.

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Checka, Nisha. "Circuit Architectures for 3D Integration." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_13.

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Lin, Sheng-Chih, and Kaustav Banerjee. "Thermal Challenges of 3D ICs." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_14.

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Tan, Chuan Seng, Ronald J. Gutmann, and L. Rafael Reif. "Overview of Wafer-Level 3D ICs." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_1.

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Lu, Jian-Qiang, Timothy S. Cale, and Ronald J. Gutmann. "3D Integration Based upon Dielectric Adhesive Bonding." In Integrated Circuits and Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76534-1_10.

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Conference papers on the topic "3D integrated circuits"

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Lyu, J., M. Malakoutian, D. Rich, et al. "Diamond 3D Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits." In 2024 IEEE International Electron Devices Meeting (IEDM). IEEE, 2024. https://doi.org/10.1109/iedm50854.2024.10873424.

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Datta, Suman, E. Sarkar, K. Aabrar, et al. "Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits." In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2024. http://dx.doi.org/10.1109/vlsitechnologyandcir46783.2024.10631324.

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Ling, Yi-Chun, Shun-Hung Lee, Ahmed Mortuza Saleque, Yichi Zhang, and S. J. Ben Yoo. "3D Electronic Photonic Integrated Circuits (3D EPICs): Co-Design and Co-Integration for Optimal Performance at Scale." In CLEO: Applications and Technology. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_at.2024.jth3k.1.

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We discuss the impact of the 3D photonic integrated circuits (PICs), review enabling technologies including optical through-silicon-vias, and cover co-integration and co-design of 3D Electronic-Photonic-Integrated-Circuits (3D EPICs).
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Zidane, Hajar, Christopher Pouzou, Jordan Corsi, et al. "Substrate Integrated Waveguide in 3D Integrated Technology for D-Band Applications." In 2024 19th European Microwave Integrated Circuits Conference (EuMIC). IEEE, 2024. http://dx.doi.org/10.23919/eumic61603.2024.10732684.

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Weigel, Madeleine, Martin Kresse, Crispin Zawadzki, et al. "3D photonic integrated interposer enabling connectivity between multicore fibers and photonic integrated circuits." In Integrated Optics: Devices, Materials, and Technologies XXIX, edited by Sonia M. García-Blanco and Pavel Cheben. SPIE, 2025. https://doi.org/10.1117/12.3043661.

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Yoo, S. J. Ben. "Best-of-both-worlds computing in 3D-electronic-photonic-integrated-circuits (3D EPICs)." In Photonic Computing: From Materials and Devices to Systems and Applications, edited by Xingjie Ni and Wenshan Cai. SPIE, 2024. http://dx.doi.org/10.1117/12.3027325.

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Patti, Robert. "3D integrated circuits." In the International Conference. ACM Press, 2012. http://dx.doi.org/10.1145/2429384.2429439.

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Wong, Simon, Abbas El-Gamal, Peter Griffin, Yoshio Nishi, Fabian Pease, and James Plummer. "Monolithic 3D Integrated Circuits." In 2007 International Symposium VLSI Technology, Systems and Applications (VLSI-TSA). IEEE, 2007. http://dx.doi.org/10.1109/vtsa.2007.378923.

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Patti, Robert. "Advances in 3D integrated circuits." In the 2011 international symposium. ACM Press, 2011. http://dx.doi.org/10.1145/1960397.1960416.

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Melikyan, V. Sh, and A. G. Harutyunyan. "3D integrated circuits multifactor placement." In 2017 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2017. http://dx.doi.org/10.1109/ewdts.2017.8110082.

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Reports on the topic "3D integrated circuits"

1

Shakouri, Ali, Bin Liu, Patrick Abraham, and John E. Bowers. 3D Photonic Integrated Circuits for WDM Applications. Defense Technical Information Center, 1998. http://dx.doi.org/10.21236/ada461796.

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Ahmed, Mohammad. Early Layout Design Exploration in TSV-based 3D Integrated Circuits. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.5509.

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Chu, D., and D. W. Palmer. 3D packaging for integrated circuit systems. Office of Scientific and Technical Information (OSTI), 1996. http://dx.doi.org/10.2172/420397.

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Tsang, Harvey, Jian Yu, and Nikhil Murty. Designing a 3D Printable Arduino Integrated Circuit for Acceleration Sensing on Smart Munitions: Part I. Breadboarding. DEVCOM Army Research Laboratory, 2021. http://dx.doi.org/10.21236/ad1152804.

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