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1
Contreras, Andres A. "Micronetworking: Reliable Communication on 3D Integrated Circuits." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/728.
Full textAbstract:
The potential failure in through-silicon vias (TSVs) still poses a challenge in trying to extend the useful life of a 3D integrated circuit (IC). A model is proposed to mitigate the communication problem in 3D integrated circuits caused by the breaks at the TSVs. We provide the details of a low-complexity network that takes advantages of redundant TSVs to make it possible to re-route around breaks and maintain effective communication between layers. Different configurations for the micronetwork are analyzed and discussed. We also present an evaluation of the micronetwork's performance, which turns out to be quite promising, based on several Monte Carlo simulations. Finally, we provide some directions for future research on the subject.
2
Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.
Full textAbstract:
Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage.
The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function.
The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance.
Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects.
This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential.
A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
3
Sekar, Deepak Chandra. "Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26562.
Full textAbstract:
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.
4
Mineo, Christopher Alexander. "Clock Tree Insertion and Verification for 3D Integrated Circuits." NCSU, 2005. http://www.lib.ncsu.edu/theses/available/etd-09072005-193841/.
Full textAbstract:
The use of three dimensional chip fabrication technologies has emerged as a solution to the difficulties involved with the continued scaling of bulk silicon devices. While the technology exists, it is undervalued and underutilized largely due to the design and verification challenges a complex 3D design presents. This work presents a clock tree insertion and timing verification methodology for three dimensional integrated circuits (3DIC). It has been designed in the context of and incorporated into the 3DIC design methodology also developed within our research group. The 3DIC verification methodology serves as an efficient means to perform all setup and hold timing checks harnessing the power of existing commercial chip design and verification tools. A novel approach is presented in which the multi-die design is temporarily transformed to appear as a traditional 2D design to the commercial tools for verification purposes. Various parasitic extraction algorithms are examined, and we present a method for performing accurate 3D parasitic extraction for timing purposes. We offer theoretical insight into the optimization of a 3D clock tree for power savings and coupling-induced delay minimization. A practical example of the 3DIC design and verification flow is detailed through the explanation of our research group?s test chip, a nearly 140,000 cell 3D fast Fourier transform chip currently awaiting fabrication at MIT?s Lincoln Labs.
5
Lewis, Dean Leon. "Design for pre-bond testability in 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45756.
Full textAbstract:
In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.
6
Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.
Full textAbstract:
Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation<br>Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
7
Athikulwongse, Krit. "Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45783.
Full textAbstract:
The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored.
In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts.
In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied.
In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively.
In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.
8
Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.
Full textAbstract:
For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.
9
Alam, Syed Mohiul 1975. "ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8953.
Full textAbstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (p. 107-112).<br>Recent developments in semiconductor processing technology has enabled the fabrication of a single integrated circuit (IC) with multiple device-interconnect layers or wafers stacked on each other. This approach is commonly referred to as the 3D integration of ICs. Although there has been significant research on the impact of 3D integration on chip size, interconnect delay, and overall system performance, the reliability issues in the 3D interconnect arrays are largely unknown. In this research, a novel Reliability Computer Aided Design (RCAD) tool ERNI-3D has been developed for reliability analysis of interconnects in a 3D IC. Using this tool, circuit designers can get interactive feedback on the reliability of their circuits associated with electromigration, 3D bonding, and joule heating. Based on a joint probability distribution, a full-chip reliability model combines all reliability figures from different components to give a useful number for the designers' reference. This initial version of ERNI-3D treats 3D circuits with two wafers or device-interconnect layers in the stack. However, the data-structures and algorithms in the tool are generic enough to make it compatible with 3D circuits with more than two device-interconnect layers, and to allow incorporation of more sophisticated reliability models in the future. Since 3D integration technology is not yet widespread, and no CAD tool supports IC layouts for such a technology, a novel layout methodology has been implemented in 3DMagic by extending MAGIC, a widely used layout editor in academia. Apart from the CAD tool work, this research has also led to the development of, and interesting experiments with, some 3D circuits for testing ERNI-3D. The test circuits investigated are a 3D 8-bit adder and an FPGA.<br>by Syed Mohiul Alam.<br>S.M.
10
Pourbakhsh, Seyed Alireza. "Dummy TSV-Based Timing Optimization for 3D On-Chip Memory." Thesis, North Dakota State University, 2016. https://hdl.handle.net/10365/29093.
Full textAbstract:
Design and fabrication of three-dimensional (3D) ICs is one the newest and hottest trends in semiconductor manufacturing industry. In 3D ICs, multiple 2D silicon dies are stacked vertically, and through silicon vias (TSVs) are used to transfer power and signals between different dies. The electrical characteristic of TSVs can be modeled with equivalent circuits consisted of passive elements. In this thesis, we use “dummy” TSVs as electrical delay units in 3D SRAMs. Our results prove that dummy TSVs based delay units are as effective as conventional delay cells in performance, increase the operational frequency of SRAM up to 110%, reduce the usage of silicon area up to 88%, induce negligible power overhead, and improve robustness against voltage supply variation and fluctuation.
11
Jung, Moongon. "Low power and reliable design methodologies for 3D ICs." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51824.
Full textAbstract:
The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC designs. Through-silicon-via (TSV), a vertical interconnect element between dies, is the key enabling technology in 3D ICs. This new design element provides unprecedented design freedom as well as challenges. To maximize benefits and overcome challenges in TSV-based 3D ICs, new analysis methodologies and optimization techniques should be developed. In this dissertation, first, the robustness of 3D power delivery network is assessed under different power/ground TSV placement schemes and TSV RC variations. Next, thermo-mechanical stress and reliability problems are examined in full-chip/stack scale using the principle of linear superposition of stress tensors. Finally, physical design methods for low power 3D designs are explored to enhance the 3D power benefit over the 2D counterpart.
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Minz, Jacob Rajkumar. "Physical Design Automation for System-on-Packages and 3D-Integrated Circuits." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14012.
Full textAbstract:
The focus of this research was to develop interconnect-centric
physical design tools for 3D technologies.
A new routing model for the SOP structure was developed which
incorporated the 3D structure and formalized the resource structure
that facilitated the development of the global routing tool.
The challenge of this
work was to intelligently convert the 3D SOP routing problem into a set
of 2D problems which could be solved efficiently.
On the lines of MCM, the global routing problem
was divided into a number of phases namely, coarse pin distribution,
net distribution, detailed pin distribution, topology generation, layer
assignment, channel assignment and local routing. The novelty in this
paradigm is due to the feed-through vias needed by the nets which traverse
through multiple placement layers. To gain further improvements in
performance, optical
routing was proposed and a cost analysis study was done. The areas for
the placement of waveguides were efficiently determined, which reduced
delays and maximized utilization.
The global router developed was integrated into a simulated-annealing based
floorplanner to investigate trade-offs of various objectives. Since power-supply
noise suppression is of paramount importance in SOP, a model was developed
for the SOP power-supply network. Decap allocation, and
insertion were also integrated into the framework. The challenges
in this work were to integrate computationally intensive analysis tools with
a floorplanning that works to its best efficency provided the evaluation of
the cost functions are rapid. Trajectory-based approaches were used to sample
representative data points for congestion analysis and interpolate the
the congestion metric during the optimization schedule. Efficient
algorithms were also proposed for 3D clock routing, which acheived
equal skews under uniform and worst thermal profiles. Other
objectives such as wirelength, through-vias, and
power were also handled.
13
Nagarajan, Raghavan. "Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45389.
Full textAbstract:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008.<br>Includes bibliographical references (p. 84-87).<br>Wafer bonding is a key process and enabling technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power dissipation, along with an improved form factor and portability. One of the most recent novel and promising wafer bonding approaches to realizing 3DIC is Low Temperature Thermocompression (LTTC) bonding using copper (Cu) as the bonding interface material. This thesis investigates the LTTC bonding approach in terms of its technological implications in contrast to other conventional bonding approaches. The various technological aspects pertaining to LTTC are comprehensively explored and analyzed. In addition to this, the commercialization potential for this technology is also studied and the economic viability of this process in production is critically evaluated using suitable cost models. Based on the technological and economic outlook, the potential for commercialization of LTTC is gauged.<br>by Raghavan Nagarajan.<br>M.Eng.
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Kim, Dae Hyun. "Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43642.
Full textAbstract:
The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs.
The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength.
The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance.
The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness.
The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated.
The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.
15
Kim, Chul. "3D-SoftChip: A novel 3D vertically integrated adaptive computing system [thesis]." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2005. https://ro.ecu.edu.au/theses/656.
Full textAbstract:
At present, as we enter the nano and giga-scaled integrated-circuit era, there are many system design challenges which must be overcome to resolve problems in current systems. The incredibly increased nonrecurring engineering (NRE) cost, abruptly shortened Time-to- Market (ITA) period and ever widening design productive gaps are good examples illustrating the problems in current systems. To cope with these problems, the concept of an Adaptive Computing System is becoming a critical technology for next generation computing systems. The other big problem is an explosion in the interconnection wire requirements in standard planar technology resulting from the very high data-bandwidth requirements demanded for real-time communications and multimedia signal processing. The concept of 3D-vertical integration of 2D planar chips becomes an attractive solution to combat the ever increasing interconnect wire requirements. As a result, this research proposes the concept of a novel 3D integrated adaptive computing system, which we term 3D-ACSoC. The architecture and advanced system design methodology of the proposed 3D-SoftChip as a forthcoming giga-scaled integrated circuit computing system has been introduced, along with high-level system modeling and functional verification in the early design stage using SystemC.
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Helou, Jirar Nicolas. "Fully differential CTIA cds for a 32x16 ROIC for 3D ladar imaging systems." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 74 p, 2007. http://proquest.umi.com/pqdweb?did=1338919441&sid=7&Fmt=2&clientId=8331&RQT=309&VName=PQD.
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Healy, Michael Benjamin. "Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures." Thesis, Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10562.
Full textAbstract:
The main objective of this thesis is to develop a physical design tool that is capable of being used by microarchitects to evaluate the impact of their design decisions on the physical design aspects of future microprocessor development. For deep submicron technology wire delay will scale increasingly badly compared to gate delay and so will become a major bottleneck to performance improvement. Three dimensional integrated circuits (3D ICs) offer a new method of dealing with non-linear wire latency by allowing shorter interconnects that act within their linear region. Thermal considerations in 3D ICs will be more important than traditional designs however, so this problem must also be addressed.
This thesis presents a microarchitectural floorplanning tool that will help computer architects to attack the wire delay problem early in the design stages of higher performance microprocessors by including consideration of design for 3D ICs. Consideration of the new problems that occur due to the move to 3D and inherent difficulties with deep submicron design is included. Experiments demonstrate that this tool can generate microprocessor floorplans that include many objectives and continue to enhance performance into the next generation of high performance design.
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Sart, Clément. "Numerical and Experimental Investigations on Mechanical Stress in 3D Stacked Integrated Circuits for Imaging Applications." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAI084.
Full textAbstract:
Ces dernières années, un certain nombre de barrières physiques ou économiques ont fait leur apparition dans la course pour la miniaturisation et l’amélioration des performances des circuits intégrés. Pour dépasser ces limites, de nouvelles architectures sont continûment développées. En particulier, on observe un tournant dans l’industrie de la microélectronique vers les stratégies d’intégration 3D, comme une alternative à la réduction des dimensions des transistors MOS. Cette approche innovante consiste à combiner en un seul et même module des puces de technologies ou fonctionnalités diverses. Une stratégie possible pour réaliser ces systèmes hétérogènes est d’empiler verticalement les puces les unes sur les autres plutôt que de les juxtaposer dans le plan, permettant des gains considérables en terme de compacité et de polyvalence des circuits. Ceci vaut en particulier pour les capteurs d’image, pour lesquels l’exploitation de la dimension verticale rend possible l’incorporation de fonctionnalités supplémentaires, notamment pour le traitement d’image. Parmi les nombreuses méthodes existantes pour réaliser des interconnexions verticales directes entre les puces empilées, le collage « hybride » cuivre/oxyde est une approche prometteuse permettant de réaliser simultanément la connexion mécanique et électrique, avec un pas d’interconnexion submicronique car limité principalement par la précision d’alignement atteignable entre les plots de collage métalliques au moment de leur mise en contact.Un enjeu majeur pour ce type d’architecture innovante est la tenue mécanique des éléments de connexion électrique. Cette thèse vise à examiner la robustesse mécanique d’un capteur d’image reporté sur un circuit logique de technologie plus avancée par empilement 3D, dans le but de prévenir un certain nombre de problèmes potentiels causés par les contraintes thermomécaniques s’accumulant pendant sa fabrication. Dans ce travail de thèse, les contraintes mécaniques générées dans le capteur d’image empilé pendant l’élaboration du circuit et son encapsulation dans un boîtier à puce sont examinées, et les interactions entre les différents composants du système analysées. L’intégrité mécanique de plusieurs structures clés est étudiée, notamment : (i) les plots d’interconnexion à l’interface de collage « hybride » entre la puce imageur et la puce logique, (ii) les plots d’assemblage filaire faisant le lien entre le capteur d’image empilé et le substrat du boîtier, ainsi que (iii) les composants électroniques dans la zone active du substrat silicium du capteur d’image, à travers l’évaluation in-situ des contraintes mécaniques induites par les procédés de fabrication grâce à des capteurs de contraintes piézorésistifs à base de silicium dopé. Pour ce faire, une approche combinant caractérisations expérimentales et analyses numériques a été adoptée : les mesures morphologiques, mécaniques et électriques effectuées sont systématiquement corrélées et étendues à l’aide de simulations par la méthode des éléments finis, permettant de garantir la bonne intégration des produits d’imagerie du point de vue thermomécanique<br>In recent years, a number of physical and economical barriers have emerged in the race for miniaturization and speed of integrated circuits. To circumvent these issues, new processes and architectures are continuously developed. In particular, a progressive shift towards 3D integration strategies is currently observed in the semiconductor industry as an alternative path to further transistor downscaling. This innovative approach consists in combining chips of different technologies or different functionalities into a single module. A possible strategy to realize such heterogeneous systems is to stack chips on top of each other instead of tiling them on the plane, enabling considerable benefits in terms of compactness and versatility, but also increased performance. This is especially true for image sensor chips, for which vertical stacking allows the incorporation of additional functionalities such as advanced image signal processing. Among various methods to achieve direct vertical interconnections between stacked chips, a promising method is Cu/SiO2 hybrid bonding, enabling simultaneous mechanical and electrical connection with a submicron interconnection pitch mostly limited by photolithography resolution and alignment accuracy.The mechanical integrity of the different electrical connection elements for such a 3D integrated imager-on-logic device is of critical importance. The aim of this thesis is to investigate the mechanical robustness of this relatively new architecture in semiconductor manufacturing during its fabrication, aiming to address a number of possible issues from a thermomechanical perspective. In this work, thermomechanical stresses building up in the image sensor during chip processing and assembly onto a package are investigated, and the interactions between the different system components analyzed. The mechanical integrity of several key structures is studied, namely (i) interconnection pads at the hybrid bonding interface between the imager/logic chips, (ii) bondpad structures below the wires connecting the imager to the package substrate, and (iii) semiconductor devices in the image sensor, through in-situ evaluation of process-induced mechanical stresses using doped Si piezoresistive stress sensors. To do so, for each item a combined numerical and experimental approach was adopted, using morphological, mechanical and electrical characterizations, then correlated or extended by thermomechanical finite element analyses, allowing to secure product integration from a thermomechanical perspective
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Sawicki, Sandro. "Particionamento de células e pads de I/O em circuitos VLSI 3D." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/26502.
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A etapa de particionamento em circuitos VLSI 3D é fundamental na distribuição de células e blocos para as camadas do circuito, além de auxiliar na redução da complexidade dos posicionadores. Estes, quando o particionamento é bem realizado, permitem que se atinjam soluções com menor comprimento total de fios, o que reduz a dissipação de potência e aumenta o desempenho dos circuitos. Atualmente, os algoritmos utilizados para resolver o problema de particionamento em circuitos 3D são adaptações daqueles aplicados em circuitos planares. Ou seja, o circuito é particionado como se fosse um hipergrafo tradicional, e as células são assinaladas diretamente para as partições, com o objetivo de reduzir somente as conexões que cruzam as partes. Contudo essa solução é simplista e faz com que o algoritmo não perceba a criação de conexões longas, o que aumenta o número de vias do circuito e, consequentemente, sua área. É importante compreender que o valor dos recursos usados é um múltiplo da distância vertical das camadas. Na verdade, considerando-se que o caminho de uma camada para outra adjacente atravessa todos os níveis de metal, é evidente que qualquer ligação vertical superior à adjacente pode ser proporcionalmente mais custosa para o roteamento, sem mencionar o atraso provocado e o quanto da área ativa é ocupada. Em vista disso, este trabalho apresenta um conjunto de algoritmos desenvolvidos para reduzir o número de vias em circuitos VLSI 3D. A otimização é obtida pelo uso de duas estratégias distintas: a análise prévia da estrutura interna do circuito e a redução do número de conexões verticais não-adjacentes. Os algoritmos propostos, além de reduzir o número de vias-3D, adaptam a lógica dos circuitos 2D para os 3D mantendo o balanceamento de área e dos pinos de I/O entre as diferentes camadas. Os resultados experimentais mostram que essas técnicas reduzem o número total de vias-3D em 19%, 18%, 12% e 16% em duas, três, quatro e cinco tiers, respectivamente, comparados com os resultados das abordagens atuais.<br>A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allow interconnection of stacked 2D circuits. However, 3D-vias can impose significant obstacles and constraints to the 3D placement problem. Most of the existing placement and partitioning algorithms completely ignore this fact, but they do optimize the number of vias using a min-cut partitioning applied to a generic graph partitioning problem. This work proposes a new approach for I/O pads and cells partitioning addressing 3D-vias reduction and its impact on the 3D circuit design. The approach presents two distinct strategies: the first one is based on circuit structure analyses and the second one reducing the number of connections between nonadjacent tiers. The strategies outperformed a state-of-the-art hypergraph partitioner, hMetis and other approaches by providing a reduction of the number of 3D-vias 19%, 17%, 12% and 16% using two, three, four and five tiers.
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King, Calvin R. Jr. "Thermal management of three-dimensional integrated circuits using inter-layer liquid cooling." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44759.
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Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack.
This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min.
The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².
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Doan, Nguyen Anh Vu. "Multi-Objective Optimization and Multi-Criteria Decision Aid Applied to the Design of 3D-Stacked Integrated Circuits." Doctoral thesis, Universite Libre de Bruxelles, 2015. https://dipot.ulb.ac.be/dspace/bitstream/2013/216785/4/thesis.pdf.
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Ces dernières décennies, l'industrie en microélectronique s'est astreinte à suivre la loi de Moore pour améliorer la performance des circuits intégrés (Integrated Circuit, IC). Cependant, il sera sans doute impossible de suivre cette loi dans le futur à cause de limitations physiques apparaissant avec la miniaturisation des transistors en-dessous d'un certain seuil si aucune innovatio n'a lieu. Afin de surmonter ce problème, de nouvelles technologies ont émergées, et parmi elles les circuits 3D (3D-Stacked Integrated Circuit, 3D-SIC) ont été proposés pour maintenir l'évolution de la loi de Moore. Les 3D-SIC peuvent apporter de nombreux avantages dans le design des futurs IC mais au coût d'une complexité de design accrue étant donné leur nature fortement combinatoire, et l'optimisation de plusieurs critères conflictuels. Dans cette thèse, nous présentons une première étude des outils qui pourraient aider dans le design de 3D-SIC, en utilisant l'optimisation multi-objectifs (multiobjective optimization, MOO) et l'aide multicritère à la décision (multi-criteria decision aid, MCDA). Notre étude vise l'une des problématiques principales dans le design de 3D-SIC: le partitionnement avec estimation du floorplanning en tenant compte de plusieurs objectifs. Cette thèse montre que l'utilisation d'un paradigme multicritère peut fournir une analyse pertinente et objective du problème. Cela peut permettre une exploration rapide de l'espace de design et une amélioration des flots de conception actuels étant donné qu'il est possible de fournir des informations qualitatives et quantitatives par rapport à l'espace de design qui ne seraient pas disponibles avec les outils actuels. De même, de par sa flexibilité, la MOO peut tenir compte des multiples degrés de liberté des 3D-SIC, ce qui permet plus de possibilités de design qui ne sont généralement pas prises en compte avec les outils actuels. De plus, les algorithmes développés peuvent montrer des propriétés de robustesse même si le problème est complexe. Enfin, appliquer l'aide multicritère à la décision pourrait permettre aux designers de faire des choix pertinents selon un processus transparent.<br>In the past decades, the microelectronic industry has been following the Moore's law to improve the performance of integrated circuits (IC). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold without innovation. In order to overcome this problem, new technologies have emerged, and among them the 3D-Stacked Integrated Circuits (3D-SIC) have been proposed to keep the Moore's momentum alive. 3D-SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and the optimization of several conflicting criteria. In this thesis, we present a first study of tools that can help the design of 3D-SICs, using mutiobjective optimization (MOO) and multi-criteria decision aid (MCDA). Our study has targeted one of the main issues in the design of 3D-SICs: the partitioning with floorplanning estimation under multiple objectives. This thesis shows that the use of a multi-criteria paradigm can provide relevant and objective analysis of the problem. This can allow a quick design space exploration and an improvement of the current design flows as it is possible to provide qualitative and quantitative information about a design space, that would not be available with current tools. Also, with its flexibility, MOO can cope with the multiple degrees of freedom of 3D-SICs, which enables more design possibilities that are usually not taken into account with current tools. In addition, the developed algorithms can show robustness properties even if the problem is complex. Finally, applying multi-criteria decision aid would allow designers to make relevant choices in a transparent process.<br>Doctorat en Sciences de l'ingénieur<br>info:eu-repo/semantics/nonPublished
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Tsui, Yat Kit. "Design and fabrication of a flip-chip-on-chip multi-chip module with 3D packaging structure and through-silicon-via for underfill dispensing /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?MECH%202004%20TSUI.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 116-127). Also available in electronic version. Access restricted to campus users.
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Yeleswarapu, Krishnamurthy. "TCAD simulation framework for the study of TSV-device interaction." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51785.
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With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area respectively. These concerns have led to an effort to find a solution that would reduce interconnect delay and leakage, while also reducing the area they occupy in a chip, so that either the chip area could be reduced, or more functionality could be incorporated within a certain area. 3D integration, i.e., stacking of various sub-systems of a chip on top of each other, enables chip-makers to achieve higher packaging efficiencies, thereby reducing system cost, while also reducing delay (and thus increasing the available bandwidth). Through Silicon Vias (TSVs) have emerged as the key interconnect technology for 3D ICs, as they enable significant reduction in delay and leakage compared to wire-bonded dies, while also occupying less area in a package. They also enable stacking of sub-systems which differ in functionality, and stacking of multiple dies. Also, unlike wire-bond, dies need not be bandwidth limited by the number of wire bonds that can be made between two levels in a stack. While TSVs offer many advantages, one of the concerns when implementing a 3D system using TSVs is the mechanisms of interaction between a TSV and a device in its vicinity. Another concern is with regards to the interaction between the TSV and its surrounding material. The purpose of this thesis is to develop a TCAD framework for process and device co-simulation of a TSV transistor system to study the various mechanisms of interaction between them, as well as between the TSV and substrate. The utility of this tool has been demonstrated by studying two mechanisms of interaction, the effect of TSV-induced stress, and the effect of TSV-device electrical coupling, on the electrical performance of bulk NMOS and PMOS transistors. The results from 3D TCAD simulations suggest that designers can scale the keep out zone (KOZ) around TSVs more aggressively, allowing for more efficient utilization of silicon area, without a drastic performance penalty.
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Xu, Yuanzhe, and 徐远哲. "Variational analysis for 3D integrated circuit on-chip structures based on process-variation-aware electromagnetic-semiconductor coupledsimulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47047616.
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Fkih, Yassine. "Conception en vue du Test des Circuits Intégrés 3D à base de TSVs." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20063/document.
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Depuis plusieurs années, la complexité des circuits intégrés ne cesse d'augmenter : du SOC (System On Chip) vers le SIP (System In Package), et plus récemment les circuits empilés en 3D : les 3D SIC (Stacked Integrated Circuits) à base de TSVs (Through Silicon Vias) interconnectant verticalement les tiers, ou puces, du système. Les 3D SIC présentent de nombreux avantages en termes de facteur de forme, de performance et de consommation mais demandent aussi de relever de nombreux défis en ce qui concerne leur test, étape nécessaire avant la mise en service de ces systèmes complexes. Dans cette thèse, nous nous attachons à définir les infrastructures de test qui permettront de détecter les éventuels défauts apparaissant lors de la fabrication des TSVs ou des différentes puces du système. Nous proposons une solution de BIST (Built In Self Test) pour le test avant empilement des TSVs. Cette solution est basée sur l'utilisation d'oscillateurs en anneaux dont la fréquence d'oscillation dépend des caractéristiques électriques des TSVs. La solution de test proposée permet non seulement la détection de TSVs fautifs mais aussi de renseigner sur le nombre d'éléments défectueux et leur identification. D'autre part, nous proposons une architecture de test 3D basée sur la nouvelle proposition de norme IEEE P1687. Cette infrastructure permet de donner accès aux composants du système 3D avant et après empilement. Elle permet d'autre part de profiter du recyclage des données de test développées et appliquées avant empilement pour chacun des tiers puis ré-appliqués durant ou après l'empilement. Ces travaux aboutissent finalement à l'ouverture d'une nouvelle problématique liée à l'ordonnancement des tests sous contraintes (puissance consommée, température).Mots-clés : test, circuits 3D, TSV, BIST, oscillateur en anneau, architecture de test 3D, IEEE P1687, test avant empilement, test après empilement<br>For several years, the complexity of integrated circuits continues to increase, from SOC (System On Chip) to SIP (System In Package) , and more recently 3D SICs (Stacked Integrated Circuits) based on TSVs (Through Silicon Vias ) that vertically interconnect stacked circuits in a 3D system. 3D SICs have many advantages in terms of small form factor, high performances and low power consumption but have many challenges regarding their test which is a necessary step before the commissioning of these complex systems. In this thesis we focus on defining the test infrastructure that will detect any occurring defects during the manufacturing process of TSVs or the different sacked chips in the system. We propose a BIST (Built In Self Test) solution for TSVs testing before stacking, this solution is based on the use of ring oscillators which their oscillation frequencies depend on the electrical characteristics of the TSVs. The proposed test solution not only allows the detection of faulty TSVs but also gives information about the number of defective TSVs and their location. On the other hand, we propose a 3D DFT (Design For Test) architecture based on the new proposed test standard IEEE P1687. The proposed test architecture provides test access to the components of the 3D system before and after stacking. Also it allows the re-use of recycled test data developed and applied before stacking to each die in the mid-bond and post-bond test levels. This work lead to the opening of a new problem related to the test scheduling under constraints such as: power consumption, temperature.Keywords: test, 3D circuits, TSV, BIST, ring oscillators, 3D DFT architecture, IEEE P1687, pre-bond test, post-bond test
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Healy, Michael Benjamin. "Physical design for performance and thermal and power-supply reliability in modern 2D and 3D microarchitectures." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37093.
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The main objective of this research is to examine the performance, power noise, and thermal trade-offs in modern traditional (2D) and three-dimensionally-integrated (3D) architectures and to present design automation tools and physical design methodologies that enable higher reliability while maintaining microarchitectural performance for these systems. Five main research topics that support this goal are included. The first topic focuses on thermal reliability. The second, third, and fourth, topics examine power-supply noise. The final topic presents a set of physical design and analysis methodologies used to produce a 3D design that was sent for fabrication in March of 2010.
The first section of this dissertation details a microarchitectural floorplanning algorithm that enables the user to choose and adjust the trade-off between microarchitectural performance and general operating temperature in both 2D and 3D systems, which is a major determinant of overall reliability and chip lifetime. Simulation results demonstrate that the algorithm performs as expected and successfully provides the user with the desired trade-off. The first section also presents a thermal-aware microarchitectural floorplanning algorithm designed to help reduce the operating temperature of the cores in the unique environment present within multi-core processors. Heat-coupling between neighboring cores is considered during the optimization process to provide floorplans that result in lower maximum temperature.
The second section explores power-supply noise in processors caused by fine-grained clock-gating and describes a floorplanning algorithm created to work with an active noise-canceling clock-gating controller. Simulation results show that combining these two techniques results in lower power-supply noise with minimal processor performance impact. The third section turns to future 3D systems with a large number of stacked active layers (many-tier systems) and examines power-supply delivery challenges in these systems. Parasitic resistance, capacitance, and inductance are calculated for the 3D vias, and the results of scaling various parameters in the power-supply-network design are presented. Several techniques for reducing power-supply-network noise in these many-tier systems are explored. The fourth section describes a layout-level analysis of a novel power distribution through-silicon-via topology and it's effect on IR-drop and dynamic noise. Simulations show that both types of power-supply noise can be reduced by more than 20\% in systems with non-uniform per-tier power dissipation when using the proposed topology.
The final section explains the physical design and analysis techniques used to produce the layouts for 3D-MAPS, a 64-core 3D-stacked memory-on-processor system targeted at demonstration of large memory bandwidth using 3D connections. The 3D-aware physical design flow utilizing non-3D-aware commercial tools is detailed, along with the techniques and add-ons that were developed to enable this process.
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Lee, Young-Joon. "CAD methodologies for low power and reliable 3D ICs." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47635.
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The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects.
The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages.
The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality.
The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead.
The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.
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Liu, Xi. "Experimental and theoretical assessment of Through-Silicon Vias for 3D integrated microelectronic packages." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50249.
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With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermomechanical reliability is still in infancy. This work explores the thermomechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with free-standing wafers, this work examines failure mechanisms such as Si and SiO₂ cohesive cracking as well as SiO₂/Cu interfacial cracking. Such cohesive crack propagation and interfacial crack propagation are studied using fracture mechanics finite-element modeling, and the energy available for crack propagation is determined through crack extension using the proposed centered finite-difference approach (CFDA). In parallel to the simulations, silicon wafers with TSVs are designed and fabricated and subjected to thermal shock test. Cross-sectional SEM failure analysis is carried out to study cohesive and interfacial crack initiation and propagation under thermal excursions. In addition, local micro-strain fields under thermal excursions are mapped through synchrotron X-ray diffraction. To understand the 3D to 2D strain measurement data projection process, a new data interpretation method based on beam intensity averaging is proposed and validated with measurements. Building upon the work on free-standing wafers, this research studies the package assembly issues and failure mechanisms in multi-die stacks. Comprehensive design-of-simulations study is carried out to assess the effect of various material and geometry parameters on the reliability of 3D microelectronic packages. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermomechanical reliability of TSVs used in future 3D microelectronic packages.
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Knechtel, Johann [Verfasser], Jens [Akademischer Betreuer] Lienig, and Günter [Akademischer Betreuer] Elst. "Interconnect Planning for Physical Design of 3D Integrated Circuits / Johann Knechtel. Gutachter: Jens Lienig ; Günter Elst. Betreuer: Jens Lienig." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://d-nb.info/1068446714/34.
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Sane, Hemant. "Power supply noise analysis for 3D ICs using through-silicon-vias." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33875.
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3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy stage. Power supply noise analysis is one of the critical aspects of a design. Hence, the area of noise analysis for 3D designs is a key area for future development. The following research presents a new parasitic RLC modeling technique for 3D chips containing TSVs as well as a novel optimization algorithm for power-ground network of a 3D chip with the aim of minimizing noise in the network. The following work also looks into an existing commercial IR drop analysis tool and presents a way to modify it with the aim of handling 3D designs containing TSVs.
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Ma, Yue. "Modèles compacts électro-thermiques du premier ordre et considération de bruit pour les circuits 3D." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI042/document.
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L'intégration tridimensionnels (3D) ont été couronnés de succès dans les dispositifs traditionnels pour augmenter la densité logique et réduire les distances de mouvement des données. Il résout les limites fondamentales de la mise à l'échelle, par ex. retard croissant dans les interconnexions, les coûts de développement et la variabilité. La plupart des périphériques de mémoire livrés aujourd'hui comportent une forme d'empilage de puce. Mais en raison des limites de dissipation de puissance des circuits intégrés, la fréquence de fonctionnement du MPU d'aujourd'hui a été limitée à quelques GHz. Le but de la thèse est de fournir une méthode de conception globale pour le circuit intégré 3D dans le domaine électrique, thermique, électrothermique et aussi le bruit. À cette fin, la question de recherche est la suivante: Comment réaliser la conception 3D IC, comment gérer VLS 3D IC et comment résoudre les problèmes thermiques dans le CI 3D. Dans ce contexte, les méthodes de simulation pour le substrat et également la connectivité relative (TSV, RDL, Micro strip et circuits intégrés dans le substrat) sont proposées. Afin de satisfaire la demande de recherche, un 3D-TLE et une impédance de substrat sont programmés dans Matlab, qui peut automatiquement extraire de tous les contacts; impédance, de forme arbitraire et de matière arbitraire. L'extracteur est compatible à 100% avec le simulateur de cœur SPICE et vérifié avec les résultats de mesure et les résultats de simulation FEM. Et comme pour une démo, une fréquence de 26 GHz et un filtre RF de bande passante 2GHz sont proposés dans ce travail. Un autre simulateur électrothermique est également programmé et vérifié avec ADS. En tant que solution à la dissipation thermique locale, le caloduc plat est proposé comme composant potentiel. Le modèle caloduc est vérifié avec une simulation FEM. La méthode d'analyse du bruit des substrats et les méthodes de calcul de électriques et thermo-mécanique KOZ sont également présentées<br>Three Dimensional (3D) Integration and Packaging has been successful in mainstream devices to increase logic density and to reduce data movement distances. It solves the fundamental limits of scaling e.g. increasing delay in interconnections, development costs and variability. Most memory devices shipped today have some form of chip-stacking involved. But because of the power dissipation limits of ICs, today’s MPU’s operating frequency has been limited to a few GHz. The aim of the thesis is to provide a global design method for the 3D integrated circuit in electrical, thermal, electro-thermal and also noise field. To this end, the research question is as follows: How to realize the 3D IC design, how to manage VLS 3D IC and how to solve the thermal issues in the 3D IC. In this context, the simulation methods for substrate and also relative connectivity (TSV, RDL, Micro strip and circuits embedded into the substrate) are proposed. In order to satisfy the research demand, a 3D-TLE and a substrate impedance are programmed in Matlab, which can automatically extract from any contacts; impedance, of arbitrary shape and arbitrary material. The extractor is 100% compatible with SPICE core simulator, and verified with measurement results and FEM simulation results. And as for a demo, a 26 GHz frequency and 2GHz bandwidth RF filter is propose in this work. Another electro-thermal simulator is also programmed and verified with ADS. As a solution to the local heat dissipation, flat heat pipe (FHP) is proposed as a prospective component. The heat-pipe model is verified with FEM simulation. The substrates noise analysis method and electrical and thermos-mechanical keep-out-of-zone (KOZ) calculation methods are also presented
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David, Romain. "Study and design of integrated laser diode driver for 3D-depth sensing applications." Thesis, Lyon, 2021. http://www.theses.fr/2021LYSE1033.
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Les nouveaux capteurs d’image 3D sont des éléments clés pour exploiter pleinement les applications émergentes dans les domaines de l'imagerie 3D et de la vision par ordinateur telles que la reconnaissance faciale, la capture de mouvement, la détection de présence ou encore la réalité augmentée. Ces capteurs reposent essentiellement sur une technique de mesure de distance. Parmi celles-ci, la mesure indirecte du temps de vol des photons présente l’avantage d’une mise en œuvre simple, fiable et économique appropriée aux applications mobiles grâce au fonctionnement conjugué d’un capteur d’image et d’une diode laser. Le principe consiste à calculer une distance en mesurant le déphasage entre un signal laser infrarouge modulé et le signal optique renvoyé après réflexion sur un objet de la scène. Des impulsions laser avec un rapport cyclique proche de 50\% sont généralement utilisées comme signal laser en modulant le courant à travers une diode laser. Le travail de thèse se focalise sur l'étude et la conception d'un circuit intégré de pilotage de diode laser qui soit à la fois compact, efficace et peu cher, pour des applications d'imagerie 3D utilisées dans les téléphones portables. La nouveauté ici concerne l'intégration du pilote entier (hormis la diode laser et quelques composants passifs) sur une seule puce tout en respectant les contraintes des applications mobiles (faibles tensions d'alimentation, forte intégration). Un autre défi important concerne les pics de tension se produisant pendant les transitoires rapides dus aux inductances parasites. Enfin, un fort rendement électrique s’avère indispensable dans le but de prolonger l’autonomie de la batterie et minimiser l’auto-échauffement. A des fins de comparaison, deux topologies de pilotage différentes, mettant en oeuvre un convertisseur DC/DC associé à un élément de commutation connecté soit en série soit en parallèle de la diode laser, ont été retenues comme base pour concevoir le pilote de diode laser. Deux prototypes ont été réalisés en utilisant une technologie CMOS 130nm de STMicroelectronics, qui sont capables de fournir des impulsions de courant jusqu'à 3A avec une largeur d'impulsion de 2,5ns à une fréquence maximale de 200MHz sous une tension d'alimentation de 3,6V. Dans ces conditions, ils délivrent une puissance électrique de sortie moyenne de 4,5W à la diode laser avec un rendement électrique d'environ 60%<br>Three-dimensional (3D) image sensors are key enablers for unlocking emerging applications in consumer electronics such as facial recognition, presence detection, gesture control or Augmented Reality (AR). These sensors mostly rely on range measuring techniques such as structured-light or Time-of-Flight (ToF) principles. The indirect Time-of-Flight (iToF) principle offers the advantage of a simple, reliable and low cost solution for mobile applications by using a laser transmitter and an image sensor. Its operating principle is to calculate a distance by measuring the phase shift between a modulated infrared laser signal and the optical signal received by the sensor after reflection on an object from the scene. Laser pulses with a duty cycle close to 50\% are usually sent through the scene by modulating the current through a semiconductor laser diode. The thesis is focused on the study and design of a compact, cost-effective and efficient integrated Laser Diode Driver (LDD) for 3D-depth sensing applications used in mobile phones. The novelty here concerns the integration of the whole driver (except laser diode and some passive components) on a single chip while accommodating mobile phone constraints (low supply voltages, high integration). Another important requirement concerns the high voltage spikes occurring during fast transients due to stray inductance. Finally, a high efficiency and low losses in the chip are critical for saving the battery lifetime and minimizing the self-heating. For comparison purposes, two different driving topologies, implementing a DC/DC converter connecting a switching element either in series or in parallel with a laser diode, have been retained as basis for designing the laser diode driver. Two IC prototypes have been realized using a 130nm CMOS technology from STMicroelectronics. Both drivers are able to generate current pulses up to 3A with a 2.5ns pulse width at a maximum 200MHz frequency under a 3.6V supply voltage. Under theses conditions, they provide an average output electrical power of 4.5W to the laser diode with an electrical efficiency of around 60%
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Xie, Jianyong. "Electrical-thermal modeling and simulation for three-dimensional integrated systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50307.
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The continuous miniaturization of electronic systems using the three-dimensional (3D) integration technique has brought in new challenges for the computer-aided design and modeling of 3D integrated circuits (ICs) and systems. The major challenges for the modeling and analysis of 3D integrated systems mainly stem from four aspects: (a) the interaction between the electrical and thermal domains in an integrated system, (b) the increasing modeling complexity arising from 3D systems requires the development of multiscale techniques for the modeling and analysis of DC voltage drop, thermal gradients, and electromagnetic behaviors, (c) efficient modeling of microfluidic cooling, and (d) the demand of performing fast thermal simulation with varying design parameters. Addressing these challenges for the electrical/thermal modeling and analysis of 3D systems necessitates the development of novel numerical modeling methods.
This dissertation mainly focuses on developing efficient electrical and thermal numerical modeling and co-simulation methods for 3D integrated systems. The developed numerical methods can be classified into three categories. The first category aims to investigate the interaction between electrical and thermal characteristics for power delivery networks (PDNs) in steady state and the thermal effect on characteristics of through-silicon via (TSV) arrays at high frequencies. The steady-state electrical-thermal interaction for PDNs is addressed by developing a voltage drop-thermal co-simulation method while the thermal effect on TSV characteristics is studied by proposing a thermal-electrical analysis approach for TSV arrays.
The second category of numerical methods focuses on developing multiscale modeling approaches for the voltage drop and thermal analysis. A multiscale modeling method based on the finite-element non-conformal domain decomposition technique has been developed for the voltage drop and thermal analysis of 3D systems. The proposed method allows the modeling of a 3D multiscale system using independent mesh grids in sub-domains. As a result, the system unknowns can be greatly reduced. In addition, to improve the simulation efficiency, the cascadic multigrid solving approach has been adopted for the voltage drop-thermal co-simulation with a large number of unknowns.
The focus of the last category is to develop fast thermal simulation methods using compact models and model order reduction (MOR). To overcome the computational cost using the computational fluid dynamics simulation, a finite-volume compact thermal model has been developed for the microchannel-based fluidic cooling. This compact thermal model enables the fast thermal simulation of 3D ICs with a large number of microchannels for early-stage design. In addition, a system-level thermal modeling method using domain decomposition and model order reduction is developed for both the steady-state and transient thermal analysis. The proposed approach can efficiently support thermal modeling with varying design parameters without using parameterized MOR techniques.
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Puttaswamy, Kiran. "Designing high-performance microprocessors in 3-dimensional integration technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19759.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Loh, Gabriel H.; Committee Co-Chair: Lee, Hsien-Hsin S.; Committee Member: Lim, Sung Kyu; Committee Member: Prvulovic, Milos; Committee Member: Yalamanchili, Sudhakar; Committee Member: Yoder, Douglas.
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Brocard, Mélanie. "Caractérisation et analyse du couplage substrat entre le TSV et les transistors MOS dans les circuits intégrés 3D." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00954178.
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Ces dernières années ont vu l'émergence d'un nouveaux concept dans le domaine de la microélectronique pour répondre aux besoins grandissant en termes de performances et taille des puces et trouver une alternative au loi de Moore et de More than Moore qui atteignent leur limites. Il s'agit de l'intégration tridimensionnelle des circuits intégrés. Cette innovation de rupture repose sur l'empilement de puces aux fonctionnalités différentes et la transmission des signaux au travers des substrats de silicium via des TSV (via traversant le silicium). Très prometteurs en termes de bande passante et de puissance consommée devant les circuits 2D, les circuits intégrés 3D permettent aussi d'avoir des facteurs de forme plus agressifs. Des points clés par rapport aux applications en vogue sur le marché (téléphonie, appareils numériques) Un prototype nommé Wide I/O DRAM réalisé à ST et au Leti a démontré ses performances face à une puce classique POP (Package on Package), avec une bande passante multipliée par huit et une consommation divisée par deux. Cependant, l'intégration de plus en plus poussée, combinée à la montée en fréquence des circuits, soulève les problèmes des diaphonies entre les interconnexions TSV et les circuits intégrés, qui se manifestent par des perturbations dans le substrat. Ces TSV doivent pouvoir véhiculer des signaux agressifs sans perturber le fonctionnement de blocs logiques ou analogiques situés à proximité, sensibles aux perturbations substrat. Cette thèse a pour objectif d'évaluer ces niveaux de diaphonies sur une large gamme de fréquence (jusqu'à 40 GHz) entre le TSV et les transistors et d'apporter des solutions potentielles pour les réduire. Elle repose sur de la conception de structure de test 3D, leur caractérisation, la modélisation des mécanismes de couplage, et des simulations.
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Fernando, Pradeep R. "Genetic algorithm based two-dimensional and three-dimensional floorplanning for VLSI ASICs." [Tampa, Fla] : University of South Florida, 2006. http://purl.fcla.edu/usf/dc/et/SFE0001549.
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Natu, Nitish Umesh. "Design and prototyping of temperature resilient clock distribution networks." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51812.
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Clock Distribution Networks play a vital role in performance and reliability of a system. However, temperature gradients observed in 3D ICs hamper the functionality of CDNs in terms of varying skew and propagation delay. This thesis presents two compensation techniques, Adaptive Voltage and Controllable Delay, to overcome these problems. The compensation methods are validated using a FPGA-based test vehicle. Modification in traditional buffer design are also presented and the performance as well as the area and power overhead of both the implementations is compared.
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Sun, Fengyuan. "Analyse et caractérisation des couplages substrat et de la connectique dans les circuits 3D : Vers des modèles compacts." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0073/document.
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L’intégration 3D est la solution technologique la plus prometteuse pour suivre le niveau d’intégration dictée par la loi de Moore (cf. more than Moore, versus more Moore). Elle entraine des travaux de recherche importants depuis une douzaine d’années. Elle permet de superposer différents circuits et composants dans un seul boitier. Son principal avantage est de permettre une association de technologies hétérogènes et très spécialisées pour la constitution d’un système complet, tout en préservant un très haut niveau de performance grâce à des connexions très courtes entre ces différents circuits. L’objectif de ce travail est de fournir des modélisations cohérentes de via traversant, ou/et de contacts dans le substrat, avec plusieurs degrés de finesse/précision, pour permettre au concepteur de haut niveau de gérer et surtout d’optimiser le partitionnement entre les différentes strates. Cette modélisation passe par le développement de plusieurs vues à différents niveaux d’abstraction: du modèle physique au modèle « haut niveau ». Elle devait permettre de répondre à différentes questions rencontrées dans le processus de conception :- le modèle physique de via basé sur une simulation électromagnétique 2D ou 3D (solveur « éléments finis ») est utilisé pour optimiser l’architecture du via (matériaux, dimensions etc.) Il permet de déterminer les performances électriques des via, notamment en haute fréquence. Les simulations électromagnétiques permettent également de quantifier le couplage entre via adjacents. - le modèle compact analytique de via et de leur couplage, basé sur une description de type ligne de transmission ou noyaux de Green, est utilisé pour les simulations au niveau bloc, ainsi que des simulations de type Spice. Les modèles analytiques sont souvent validés par rapport à des mesures et/ou des modèles physiques<br>The 3D integration is the most promising technological solution to track the level of integration dictated by Moore's Law (see more than Moore, Moore versus more). It leads to important research for a dozen years. It can superimpose different circuits and components in one box. Its main advantage is to allow a combination of heterogeneous and highly specialized technologies for the establishment of a complete system, while maintaining a high level of performance with very short connections between the different circuits. The objective of this work is to provide consistent modeling via crossing, and / or contacts in the substrate, with various degrees of finesse / precision to allow the high-level designer to manage and especially to optimize the partitioning between the different strata. This modelization involves the development of multiple views at different levels of abstraction: the physical model to "high level" model. This would allow to address various issues faced in the design process: - The physical model using an electromagnetic simulation based on 2D or 3D ( finite element solver ) is used to optimize the via (materials, dimensions etc..) It determines the electrical performance of the via, including high frequency. Electromagnetic simulations also quantify the coupling between adjacent via. - The analytical compact of via their coupling model, based on a description of transmission line or Green cores is used for the simulations at the block level and Spice type simulations. Analytical models are often validated against measurements and / or physical models
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Visan, Silviu. "Simulation électromagnétique 3D basée sur la méthode des différences finies dans le domaine temporel : application à l'étude de structures planaires utilisées dans les circuits intégrés monolithiques microondes et millimétriques." Grenoble INPG, 1994. http://www.theses.fr/1994INPG0014.
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Ce travail de these a permis la mise au point et l'implementation d'une methode de simulation electromagnetique tridimensionnelle basee sur les differences finies dans le domaine temporel (fdtd - finite difference time domain). Le logiciel qui a ete realise sert a caracteriser des structures planaires, notamment celles utilisees dans les circuits integres monolithiques microondes (mmic - microwave monolithic integrated circuits). Le chapitre 1 presente le contexte de l'etude. Dans le chapitre 2 nous presentons en detail la methode qui est a la base de nos simulations. Il resulte qu'elle presente des avantages importants: tres bonne generalite, caracterisation large bande d'une structure apres une seule simulation, possibilite de prendre en compte a la fois des structures fermees et des structures ouvertes. Dans le chapitre 3, la methode a ete validee par l'etude d'une cavite resonante a 30 ghz, d'une ligne microruban uniforme, et d'un trou metallise sur une ligne microruban. Dans le chapitre 4, une etude complete a ete effectuee sur les structures coplanaires utilisees dans les mmic. Nous avons etudie des lignes uniformes, des discontinuites uniaxiales (court- circuit, circuit ouvert, gap, saut de largeur) et des discontinuites multiaxiales (coude angle droit, te, avec ou sans ponts a air). Une etude comparative a ete realisee entre deux solutions possibles pour la suppression du mode fentes couplees dans les mmic: le pont a air et les trous metallises. Le chapitre 5 presente l'etude des interconnexions entre des modules mmic et des modules hybrides. On a ainsi presente les variations des parametres s de l'interconnexion en fonction des parametres technologiques de celle-ci. Dans le chapitre 6, la simulation d'une antenne planaire a donne des resultats tout a fait conformes aux mesures experimentales. Les conclusions de ce travail sont presentees dans le chapitre 7
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Schulz, Stefan E. "AMC 2015 – Advanced Metallization Conference." Universitätsverlag der Technischen Universität Chemnitz, 2016. https://monarch.qucosa.de/id/qucosa%3A20503.
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Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry.
Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of:
- Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials)
- Highly-scaled local and global interconnects
- Beyond Cu interconnect
- Novel metallization schemes and advanced dielectrics
- Interconnect and device reliability
- Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM)
- 3D and packaging (monolithic 3D, TSV, EMI)
- Novel and emerging interconnects
Executive Committee:
Sang Hoon Ahn (Samsung Electronics Co., Ltd.)
Paul R. Besser (Lam Research)
Robert S. Blewer (Blewer Scientific Consultants, LLC)
Daniel Edelstein (IBM)
John Ekerdt (The University of Texas at Austin)
Greg Herdt (Micron)
Chris Hobbs (Sematech)
Francesca Iacopi (Griffith University)
Chia-Hong Jan (Intel Corporation)
Rajiv Joshi (IBM)
Heinrich Koerner (Infineon Technologies)
Mehul Naik (Applied Materials Inc.)
Fabrice Nemouchi (CEA LETI MINATEC)
Takayuki Ohba (Tokyo Institute of Technology)
Noel Russell (TEL Technology Center, America)
Stefan E. Schulz (Chemnitz University of Technology)
Yosi Shacham-Diamand (Tel-Aviv University)
Roey Shaviv (Applied Materials Inc.)
Zsolt Tokei (IMEC)
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Pic, Axel. "Numerical and experimental investigations of self-heating phenomena in 3D Hybrid Bonding imaging technologies." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI054.
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Dans cette thèse, les phénomènes d’auto-échauffement ont été étudié pour guider la conception de circuits intégrés 3D de nouvelle génération. Grâce à des études expérimentales et numériques, la dissipation thermique dans des imageurs 3D par collage hybride a été analysée et l’impact de l’augmentation de température résultante a été évalué. Premièrement, afin de développer des modèles précis, les propriétés thermiques des matériaux utilisés dans les circuits intégrés ont dû être déterminées. Différents films minces diélectriques impliquant des oxydes, des nitrures et des composés low-k ont été étudiés. Pour ce faire, la microscopie thermique à sonde locale (SThM) et la méthode électrothermique 3ω, sensibles à la conductivité thermique effective faible et élevée, ont été mises en œuvre. Dans un deuxième temps, des modèles éléments finis de circuits intégrés 3D ont été développés. Une méthode numérique nécessitant homogénéisations et approches multi-échelles a été proposée pour surmonter des grands rapports de forme inhérents à la microélectronique. La procédure numérique a été validée en comparant les calculs et les mesures expérimentales effectuées par SThM, la thermométrie résistive et la microscopie infrarouge sur une puce de test par collage hybride simplifiée. Il a été montré que la dissipation de chaleur est principalement limitée par la conductance du puit thermique ainsi que les pertes par l'air. Enfin, des études numériques et expérimentales ont été réalisées sur des imageurs 3D par collage hybride fonctionnels. Le champ de température a été mesuré par SThM et comparé aux calculs par éléments finis à la surface de la matrice. Les résultats numériques ont montré que la température de la surface des pixels est égale à celle du Front-End-Of-Line de l’imageur. L'influence de l'échauffement sur les performances optiques de l'imageur a été déduite de cette analyse. Cette étude a permis également d'évaluer les différentes méthodes numériques et expérimentales pour la caractérisation de la dissipation de chaleur en microélectronique<br>In this PhD thesis, self-heating phenomena are studied for guiding the design of next-generation 3D Integrated Circuits (ICs). By means of experimental and numerical investigations, associated heat dissipation in 3D Hybrid Bonding imagers is analyzed and the impact of the resulting temperature rise is evaluated. First, in order to develop accurate models, the thermal properties of materials used in ICs are to be determined. Different dielectric thin films involving oxides, nitrides, and low-k compounds are investigated. To do so, Scanning Thermal Microscopy (SThM) and the 3ω electrothermal method, sensitive to low and large effective thermal conductivity, are implemented. In a second step, finiteelement models of 3D ICs are developed. A numerical method involving homogenization and a multiscale approach is proposed to overcome the large aspect ratios inherent in microelectronics. The numerical procedure is validated by comparing calculations and experimental measurements performed with SThM, resistive thermometry and infrared microscopy on a simplified Hybrid Bonding test chip. It is shown that heat dissipation is mainly limited by the heat sink conductance and the losses through air. Finally, numerical and experimental studies are performed on fully-functional 3D Hybrid Bonding imagers. The temperature field is measured with SThM and compared with finite-element computations at the die surface. The numerical results show that the temperature of the pixel surface is equal to that of the imager Front-End-Of-Line. The influence of the temperature rise on the optical performance of the imager is deduced from the analysis. The study also allows assessing the various numerical and experimental methods for characterizing heat dissipation in microelectronics
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Neveu, Florian. "Design and implementation of high frequency 3D DC-DC converter." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0133/document.
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L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche est compatible avec une intégration totale sur silicium, mais limitée en terme de densité de puissance. Le second axe est l’utilisation de convertisseurs à inductances, qui pâtissent d’imposants composants passifs. Une augmentation de la fréquence permet de réduire les valeurs des composants passifs. Cependant une augmentation de la fréquence implique une augmentation des pertes par commutation, ce qui est contrebalancé par l’utilisation d’une technologie de fabrication plus avancée. Ces technologies plus avancées souffrent quant à elles de limitations au niveau de leur tension d’utilisation. Convertir une tension de 3,3V vers une tension de 1,2V apparait donc comme un objectif ambitieux, particulièrement dans le cas où les objectifs de taille minimale et de rendement supérieur à 90 % sont visés. Un assemblage 3D des composants actifs et passifs permet de minimiser la surface du système. Un fonctionnement à haute fréquence est aussi considéré, ce qui permet de réduire les valeurs requises pour les composants passifs. Dans le contexte de l’alimentation « on-chip », la technologie silicium est contrainte par les fonctions numériques. Une technologie 40 nm CMOS de type « bulk » est choisie comme cas d’étude pour une tension d’entrée de 3,3 V. Les transistors 3,3 V présentent une figure de mérite médiocre, les transistors 1,2 V sont donc choisis. Ce choix permet en outre de présenter une meilleure compatibilité avec une future intégration sur puce. Une structure cascode utilisant trois transistors en série est étudiée est confrontée à une structure standard à travers des simulations et mesures. Une fréquence de +100MHz est choisie. Une technologie de capacités en tranchées est sélectionnée, et fabriquée sur une puce séparée qui servira d’interposeur et recevra la puce active et les inductances. Les inductances doivent être aussi fabriquées de manière intégrée afin de limiter leur impact sur la surface du convertisseur. Ce travail fournit un objet contenant un convertisseur de type Buck à une phase, avec la puce active retournée (« flip-chip ») sur l’interposeur capacitif, sur lequel une inductance est rapportée. Le démonstrateur une phase est compatible pour une démonstration à phases couplées. Les configurations standard et cascode sont comparées expérimentalement aux fréquences de 100 MHz et 200 MHz. La conception de la puce active est l’élément central de ce travail, l’interposeur capacitif étant fabriqué par IPDiA et les inductances par Tyndall National Institute. L’assemblage des différents sous-éléments est réalisé via des procédés industriels. Un important ensemble de mesures ont été réalisées, montrant les performances du convertisseur DC-DC délivré, ainsi que ses limitations. Un rendement pic de 91,5 % à la fréquence de 100 MHz a été démontré<br>Ultimate integration of power switch-mode converter relies on two research paths. One path experiments the development of switched-capacitor converters. This approach fits silicon integration but is still limited in term of power density. Inductive DC-DC architectures of converters suffer by the values and size of passive components. This limitation is addressed with an increase in frequency. Increase in switching losses in switches leads to consider advanced technological nodes. Consequently, the capability with respect to input voltage is then limited. Handling 3.3 V input voltage to deliver an output voltage in the range 0.6 V to 1.2 V appears a challenging specification for an inductive buck converter if the smallest footprint is targeted at +90 % efficiency. Smallest footprint is approached through a 3D assembly of passive components to the active silicon die. High switching frequency is also considered to shrink the values of passive components as much as possible. In the context of on-chip power supply, the silicon technology is dictated by the digital functions. Complementary Metal-Oxide- Semiconductor (CMOS) bulk C40 is selected as a study case for 3.3 V input voltage. 3.3 V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) features poor figure of merits and 1.2 V standard core, regular devices are preferred. Moreover future integration as an on-chip power supply is more compatible. A three-MOSFET cascode arrangement is experimented and confronted experimentally to a standard buck arrangement in the same technology. The coupled-phase architecture enables to reduce the switching frequency to half the operating frequency of the passive devices. +100MHz is selected for operation of passive devices. CMOS bulk C40 offers Metal-Oxide-Metal (MOM) and MOS capacitors, in density too low to address the decoupling requirements. Capacitors have to be added externally to the silicon die but in a tight combination. Trench-cap technology is selected and capacitors are fabricated on a separate die that will act as an interposer to receive the silicon die as well as the inductors. The work delivers an object containing a one-phase buck converter with the silicon die flip-chipped on a capacitor interposer where a tiny inductor die is reported. The one-phase demonstrator is suitable for coupled-phase demonstration. Standard and cascode configurations are experimentally compared at 100 MHz and 200 MHz switching frequency. A design methodology is presented to cover a system-to-device approach. The active silicon die is the central design part as the capacitive interposer is fabricated by IPDiA and inductors are provided by Tyndall National Institute. The assembly of the converter sub-parts is achieved using an industrial process. The work details a large set of measurements to show the performances of the delivered DC/DC converters as well as its limitations. A 91.5% peak efficiency at 100MHz switching frequency has been demonstrated
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MUKHERJEE, MADHUBANTI. "ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784.
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Buttrick, Michael T. "Testable Clock Distributions for 3d Integrated Circuits." 2011. https://scholarworks.umass.edu/theses/587.
Full textAbstract:
The 3D integration of dies promises to address the problem of increased die size caused by the slowing of scaling. By partitioning a design among two or more dies and stacking them vertically, the average interconnect length is greatly decreased and thus power is reduced. Also, since smaller dies will have a higher yield, 3D integration will reduce manufacturing costs. However, this increase in yield can only be seen if manufactured dies can be tested before they are stacked. If not, the overall yield for the die stack will be worse than that of the single, larger die.
One of the largest issues with prebond die testing is that, to save power, a single die may not have a complete clock distribution network until bonding. This thesis addresses the problem of prebond die testability by ensuring the clock distribution network on a single die will operate with low skew during testing and at a reduced power consumption during operation as compared to a full clock network. The development of a Delay Lock Loop is detailed and used to synchronize disconnected clock networks on a prebond die. This succeeds in providing a test clock network that operates with a skew that is sufficiently close to the target postbond skew.
Additionally, a scheme to increase interdie bandwidth by multiplexing Through-Silicon Vias (TSVs) by the system clock is presented. This technique allows for great increase in the number of effective signal TSVs while imposing a negligible area overhead causing no performance degradation.
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Lin, Cheng-Hong, and 林政宏. "Simulation Flow and Circuit Analysis of NBTI Effects on 3D Integrated Circuits." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/77356348719628362326.
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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>With CMOS technology scaled into 65nm and 45nm node, the NBTI (negative bias temperature instability) effect has become a major reliability problem in modern circuit systems. In order to predict the threshold voltage shift and circuit performance degradation caused by NBTI, several analytical models have been proposed, and these models are functions of numerous condition parameters. To predict threshold voltage shift, NBTI can be calculated using the analytic model. However, the circuit performance degradation cannot be estimated using the analytic model alone, but through circuit simulations, such as SPICE. In this thesis, we predict ΔVth using predictive models proposed by other papers and utilize NBTI sub-circuit model for PMOS to calculate circuit performance degradation using HSPICE. The 3DIC (three-dimensional integral circuits) has features of high transistor density and vertically stacked dies, so it has the advantage such as enhancing circuit performance and reducing cost. However, 3DIC has the potential problem of high power density, which might cause difficulty in heat conduction and thus high chip temperature. As the NBTI effect is very sensitive to local temperature, protecting Critical Gates (CGs) can thus effectively reduce the impact of NBTI. In this work, we introduce two new concepts to 3DIC design and implementation. Firstly, we propose that in 3DIC, the CGs should be placed on low temperature dies in order to mitigate NBTI effect. Then we create a floorplan of 3D quad-core four chip system based on this concept and compare to other common floorplans. We use Hotspot to simulate steady state temperature. Finally, we propose an NBTI-aware 3DIC implement flow, which can be used to implement 3DIC layout that has less impacts from NBTI.
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Deutsch, Sergej. "Test and Debug Solutions for 3D-Stacked Integrated Circuits." Diss., 2015. http://hdl.handle.net/10161/10450.
Full textAbstract:
<p>Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.</p><p>Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.</p><p>Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.</p><p>Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.</p><p>In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.</p><p>Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. In addition, the proposed on-chip debug circuitry can identify erroneous segments of observed data by using compact signatures that are stored in the DRAM a priori. Only failing intervals are off-loaded from a temporary trace buffer into DRAM, allowing for a more efficient use of the memory, resulting in a larger observation window.</p><p>In summary, this dissertation provides solutions to several challenges related to 3D test and debug that need to be addressed before volume manufacturing of 3D ICs can be viable.</p><br>Dissertation
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"ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits." 2001. http://hdl.handle.net/1721.1/4112.
Full textAbstract:
by Syed Mohiul Alam.<br>Supervised by Donald E. Troxel and Carl V. Thompson.<br>Also issued as Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (p. 107-112).
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O'Sullivan, Conor. "Test Chip Design for Process Variation Characterization in 3D Integrated Circuits." Thesis, 2013. http://hdl.handle.net/10012/7888.
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A test chip design is presented for the characterization of process variations and Through
Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de-
signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries
process through CMC microsystems. The test chip takes advantage of the architecture
of 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a device
array density of 40.94 m2 per device. The design also has a high spatial resolution and
measurement delity compared to similar 2D variation characterization test structures.
Background leakage subtraction and radial ltering are two techniques that are ap-
plied to the chip's measurements to reduce its error further for subthreshold device current
measurements and stress-induced mobility measurements, respectively. Experimental mea-
surements are be taken from the chip using a custom PCB measurement setup once the
chip has returned from fabrication.
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Falkenstern, Paul Xie Yuan Das Chita R. "Electronic design automation challenges in three dimensional integrated circuits (3D ICs)." 2008. http://etda.libraries.psu.edu/theses/approved/WorldWideIndex/ETD-3421/index.html.
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Ugland, Ryan A. "Using IEEE 1500 for wafer testing of TSV Based 3D integrated circuits." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4471.
Full textAbstract:
The potential end of Moore's law has caused the semiconductor industry to investigate 3D integrated circuits as a way to continue to increase transistor density. Solutions must be put in place to allow each 3D IC die layer to be tested thoroughly on its own at wafer level to unsure adequate yield on assembled 3D devices. This paper details the testability of a 3D implementation of the Open Cores or1200 architecture. IEEE 1500 is used to signi cantly improve wafer level testability of the 3D IC die layers while maintaining a low test pin count requirement.<br>text