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Journal articles on the topic '3D integrated circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 June 2025

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Koo, Jae-Mo, Sungjun Im, Linan Jiang, and Kenneth E. Goodson. "Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures." Journal of Heat Transfer 127, no. 1 (2005): 49–58. http://dx.doi.org/10.1115/1.1839582.

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The semiconductor community is developing three-dimensional circuits that integrate logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical systems. These three-dimensional (3D) circuits pose important challenges for thermal management due to the increasing heat load per unit surface area. This paper theoretically studies 3D circuit cooling by means of an integrated microchannel network. Predictions are based on thermal models solving one-dimensional conservation equations for boiling convection along microchannels, and are consistent with past data obtained from straight channels. The model is combined within a thermal resistance network to predict temperature distributions in logic and memory. The calculations indicate that a layer of integrated microchannel cooling can remove heat densities up to 135W/cm2 within a 3D architecture with a maximum circuit temperature of 85°C. The cooling strategy described in this paper will enable 3D circuits to include greater numbers of active levels while exposing external surface area for functional signal transmission.

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Pletea, Ionica-Marcela. "Methodology and backend flow optimization for 3D." Journal of Engineering Science 31, no. 2 (2024): 39–47. https://doi.org/10.52326/jes.utm.2024.31(2).04.

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The article deals with the complexity of the workflow used when integrated circuits are implemented using 2D electronic design automation (EDA) tools and adapting the workflow for 3D integrated circuits. If some issues are not identified promptly in the workflow, the working time to produce an integrated circuit is increased. By analyzing and refining workflow, identifying bottlenecks and early problems in a design, the optimization process will ensure an error-minimized trajectory from synthesis to final design prepared for manufacturing. Considering all the details at every stage of the working flow will help the backend designer to solve problems faster and save time. It was created detailed scripts for automatization of the process at every stage including floorplan, power plan, placement, clock tree synthesis, routing and all physical and logical analysis. The workflow was optimized using loops at all levels, extracting important information at every level and improving the process of working. Moreover, optimization techniques contribute significantly to precision and quality in design implementation. This working flow can be used to implement 3D integrated circuits with automated 2D tools from Synopsis.

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Li, Chengxuan. "A review of physical heat dissipation methods for 3D integrated technology." Applied and Computational Engineering 89, no. 1 (2024): 43–47. http://dx.doi.org/10.54254/2755-2721/89/20241052.

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Three-dimensional integrated circuits have higher integration than two-dimensional integrated circuits, and can obtain higher performance and lower power consumption in a certain space. In order to fulfill higher efficiency, thermal management becomes particularly important in 3D integration technology. However, the traditional heat dissipation method cannot satisfy the heat dissipation needs of three-dimensional integrated circuits, which require better heat dissipation methods to be developed. This paper introduces the realization of three-dimensional integrated circuit using silicon via (TSV) technology, which allows the chip to be vertically stacked to transmit information. This paper summarizes the research methods and findings of three-dimensional integrated circuit heat dissipation in recent years, including thermal through silicon via (TTSV) and microchannel cooling. It also emphasizes the advantages and disadvantages of both mehods, and the challenges faced in current research via an overview. The future research trend for both heat dissipation methods mainly consists of combining special algorithms to achieve thermal-electrical codesign and thermal management of three-dimensional integrated circuits.

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Băjenescu, Titu-Marius I. "3D MICROPACKAGING OF INTEGRATED CIRCUITS." Journal of Engineering Science XXVII (1) (March 15, 2020): 28–35. https://doi.org/10.5281/zenodo.3713360.

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A major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also, reliability concerns will be extremely important: electromigration and stress-migration. This paper presents some actual problems and reliability challenges in 3D IC packaging technology. It shows how different architectures have evolved to meet the specific needs of different markets: Multi Chip Module (MCP); Multipackage module (MPM); Embedded SIP modules; SIP package-on-package (PoP) modules; EMIB (Embedded Multi-die Interconnect Bridge); Silicon-based SIP-Module; 3D-TSV stacked module; SIP variants with combinations of wideband and flip-chip interconnects. Causes of blockages and failure mechanisms, as well as problems with predictive reliability, which will need to be developed in the coming years, are analysed.

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Kim, Bruce, Sukeshwar Kannan, Anurag Gupta, and Naga Sai Evana. "Modeling and Simulation of 3D MEMS Integrated RF Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 002006–27. http://dx.doi.org/10.4071/2012dpc-wp35.

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Today's integrated packaging consists of analog, mixed-signal and RF circuits. These integrated packages are now available in 3-D which makes it extremely difficult to test for defects and their circuit functionalities. This paper provides 3D MEMS integrated packaging which provides self testing and calibrations to overcome process defects and out of spec circuits inside the package making the package self heal itself in case of faults and defects. We have worked on TSV based 3D packaging with MEMS switches to perform self calibrations. We developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated on an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. We used arrays of MEMS switches to perform self testing. We have considered a low noise amplifier as the reference RF circuit which operates between 4 GHz and 6 GHz. The entire validation of the design using test technique and self-calibration of the RF circuit is automated using the calibration algorithm. The paper presents defects in TSV due to mechanical stress and thermal changes.

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Pletea, Ionica-Marcela. "METHODOLOGY AND BACKEND FLOW OPTIMIZATION FOR 3D." JOURNAL OF ENGINEERING SCIENCE 31, no. 2 (2024): 39–47. http://dx.doi.org/10.52326/jes.utm.2024.31(2).04.

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Lee, Hsien-Hsin S., and Krishnendu Chakrabarty. "Test Challenges for 3D Integrated Circuits." IEEE Design & Test of Computers 26, no. 5 (2009): 26–35. http://dx.doi.org/10.1109/mdt.2009.125.

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Xiang, Chao, Warren Jin, Osama Terra, et al. "3D integration enables ultralow-noise isolator-free lasers in silicon photonics." Nature 620, no. 7972 (2023): 78–85. http://dx.doi.org/10.1038/s41586-023-06251-w.

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AbstractPhotonic integrated circuits are widely used in applications such as telecommunications and data-centre interconnects1–5. However, in optical systems such as microwave synthesizers6, optical gyroscopes7 and atomic clocks8, photonic integrated circuits are still considered inferior solutions despite their advantages in size, weight, power consumption and cost. Such high-precision and highly coherent applications favour ultralow-noise laser sources to be integrated with other photonic components in a compact and robustly aligned format—that is, on a single chip—for photonic integrated circuits to replace bulk optics and fibres. There are two major issues preventing the realization of such envisioned photonic integrated circuits: the high phase noise of semiconductor lasers and the difficulty of integrating optical isolators directly on-chip. Here we challenge this convention by leveraging three-dimensional integration that results in ultralow-noise lasers with isolator-free operation for silicon photonics. Through multiple monolithic and heterogeneous processing sequences, direct on-chip integration of III–V gain medium and ultralow-loss silicon nitride waveguides with optical loss around 0.5 decibels per metre are demonstrated. Consequently, the demonstrated photonic integrated circuit enters a regime that gives rise to ultralow-noise lasers and microwave synthesizers without the need for optical isolators, owing to the ultrahigh-quality-factor cavity. Such photonic integrated circuits also offer superior scalability for complex functionalities and volume production, as well as improved stability and reliability over time. The three-dimensional integration on ultralow-loss photonic integrated circuits thus marks a critical step towards complex systems and networks on silicon.

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Herraiz, Darío, Angel Belenguer, Marcos Fernandez, Santiago Cogollos, Héctor Esteban, and Vicente E. Boria. "Simple and Easily Connectable Transition from Empty Substrate-Integrated Waveguide to a 3D Printed Rectangular Waveguide." Applied Sciences 13, no. 21 (2023): 11698. http://dx.doi.org/10.3390/app132111698.

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3D printing is one of the most promising manufacturing methods in the most developed technological fields, including microwave hardware fabrication. On the other hand, the well-known manufacturing methods of planar substrate integrated circuits allow high-quality prototypes to be made at low cost and with mass production capabilities. The combination of both manufacturing methods, 2D or 2.5D (substrate integrated circuits) and 3D (3D printed structures), will allow us to take advantage of the main strengths of each technology and minimise disadvantages. In this article, for the first time, a transition structure between the Empty Substrate-Integrated Waveguide (ESIW) technology—a planar waveguide integrated on a printed circuit board—and a standard rectangular waveguide manufactured by 3D printing is proposed. This transition will make it possible to combine planar circuits with 3D structures, thus taking advantage of the benefits of both types of technologies. The fabricated prototype presents low losses (0.6 dB for the transmission coefficient and 15 dB for reflection coefficient), good electrical response (very flat), and simultaneously good mechanical stability and robustness to manufacturing and assembly errors. The proposed design for this transition piece is easily realisable for a wide range of affordable 3D printers. Repeatability is guaranteed and the proposed transition allows us to combine different SIC structures to 3D printed circuits. Hence, this transition will enable advancements in the fabrication of microwave devices, particularly with regard to satellite communications.

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Hu, Han. "Navigating The Integrated Circuit Industry: Definitions, Evolution, Innovations, And Challenges." Highlights in Science, Engineering and Technology 81 (January 26, 2024): 226–31. http://dx.doi.org/10.54097/fb9z0110.

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Now, the integrated circuit (IC) industry is experiencing rapid growth, and some of its associated technologies play vital roles in our everyday lives. This paper aims to provide comprehensive insights into the entire IC industry by elaborating on various aspects. First and foremost, it elucidates the definition, development history, and current status of integrated circuits (ICs). Subsequently, it delves into intricate details regarding three state-of-the-art technologies linked to ICs, all of which are conveyed with their full names for clarity: Integrated Circuits in Silicon Germanium (SiGe) Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) for Millimeter-Wave and Terahertz Bioanalyzers, 3D Packaging for Heterogeneous Integration, and, once again, 3D Packaging for Heterogeneous Integration. To conclude, this paper provides an in-depth exploration of the present challenges faced by the integrated circuit industry and the prospective hurdles that could impact the industry's future trajectory. By reading this paper, you can swiftly gain a comprehensive understanding of integrated circuits, covering aspects such as their definition, historical evolution, current status, cutting-edge technologies, and the prevailing challenges that demand attention.

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Ababei, C., Yan Feng, B. Goplen, et al. "Placement and Routing in 3D Integrated Circuits." IEEE Design and Test of Computers 22, no. 6 (2005): 520–31. http://dx.doi.org/10.1109/mdt.2005.150.

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Contreras, A. A., T. K. Moon, A. Dasu, and J. H. Gunther. "Micronetworking: reliable communication on 3D integrated circuits." Electronics Letters 46, no. 4 (2010): 291. http://dx.doi.org/10.1049/el.2010.2193.

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Park, Manseok, Sungdong Kim, and Sarah Eunkyung Kim. "TSV Liquid Cooling System for 3D Integrated Circuits." Journal of the Microelectronics and Packaging Society 20, no. 3 (2013): 1–6. http://dx.doi.org/10.6117/kmeps.2013.20.3.001.

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Namoune, A., R. Taleb, N. Mansour, M. R. Benzidane, and A. Boukortt. "Integrated through-silicon-via-based inductor design in buck converter for improved efficiency." Electrical Engineering & Electromechanics, no. 6 (October 21, 2023): 54–57. http://dx.doi.org/10.20998/2074-272x.2023.6.09.

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Introduction. Through-silicon-via (TSV) is one of the most important components of 3D integrated circuits. Similar to two-dimensional circuits, the performance evaluation of 3D circuits depends on both the quality factor and inductance. Therefore, accurate TSV-inductor modeling is required for the design and analysis of 3D integrated circuits. Aim. This work proposes the equivalent circuit model of the TSV-inductor to derive the relations that determine both the quality factor and the inductance by Y-parameters. Methods. The model developed was simulated using MATLAB software, and it was used to evaluate the effect of redistribution lines width, TSV radius, and the number of turns on inductance and quality factor. Additionally, a comparative study was presented between TSV-based inductors and conventional inductors (i.e., spiral and racetrack inductors). Results. These studies show that replacing conventional inductors with TSV-inductors improved the quality factor by 64 % compared to a spiral inductor and 60 % compared to a racetrack inductor. Furthermore, the area of the TSV-inductor was reduced up to 1.2 mm². Using a PSIM simulator, the application of an integrated TSV-inductor in a buck converter was studied, and the simulation gave very good results in 3D integration compared to 2D integration. Moreover, the simulation results demonstrated that using a TSV-inductor in a buck converter could increase its efficiency by up to 15 % and 6 % compared to spiral and racetrack inductors, respectively.

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Piechulek, Niklas, Lei Xu, Jan Fröhlich, Patrick Bründl, and Jörg Franke. "Miniaturization Potential of Additive-Manufactured 3D Mechatronic Integrated Device Components Produced by Stereolithography." Micromachines 16, no. 1 (2024): 16. https://doi.org/10.3390/mi16010016.

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Three-dimensional Mechatronic Integrated Devices (3D-MIDs) combine mechanical and electrical functions, enabling significant component miniaturization and enhanced functionality. However, their application in high-temperature environments remains limited due to material challenges. Existing research highlights the thermal stability of ceramic substrates; yet, their reliability under high-stress and complex mechanical loading conditions remains a challenge. In this study, 3D-MID components were fabricated using stereolithography (SLA) 3D-printing technology, and the feasibility of circuit miniaturization on high-temperature-resistant resin substrates was explored. Additionally, the influence of laser parameters on resistance values was analyzed using the Response Surface Methodology (RSM). The results demonstrate that SLA 3D-printing achieves substrates with low surface roughness, enabling the precise formation of fine features. Electric circuits are successfully formed on substrates printed with resin mixed with Laser Direct Structuring (LDS) additives, following laser structuring and metallization processes, with a minimum conductor spacing of 150 µm. Furthermore, through the integration of through-holes (vias) and the use of smaller package chips, such as Ball Grid Array (BGA) and Quad Flat No-lead (QFN), the circuits achieve further miniaturization and establish reliable electrical connections via soldering. Taken together, our results demonstrate that thermoset plastics serve as substrates for 3D-MID components, broadening the application scope of 3D-MID technology and providing a framework for circuit miniaturization on SLA-printed substrates.

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Su, Shiyuan, Zhongqi Shi, and Yile Wang. "Modeling Of 3D Integrated Circuits, Heat Transfer Solutions and Application." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 415–20. http://dx.doi.org/10.54097/hset.v71i.14620.

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As transistor sizes approach the quantum limit, the cost of further shrinking them becomes prohibitively high. To overcome this limitation and surpass Moore's Law, 3D (Integrated Circuits) IC technology has emerged. However, while 3D ICs offer advantages like high integration, they also present challenges related to thermal management. This paper introduces and discusses partial differential equations and modeling methods for heat transfer in 3D ICs. It explores solutions to address thermal conduction problems and analyzes the potential application areas and prospects of 3D ICs. By utilizing different modeling methods, we can optimize the heat transfer problem during the design stage. To enhance the thermal conduction of 3D ICs, this study proposes the use of copper thermal conductive materials, graphene thermal conductive layers, and phase-change material cooling. As technology advances and costs decrease, 3D ICs are expected to find broader applications in high-performance computing, artificial intelligence, the Internet of Things, and other fields. Despite its numerous advantages, 3D integrated circuit technology still faces challenges such as cost, heat, and silicon vias. To address these issues, further technological innovations and updates to Computer Aided Design (CAD) tools are necessary. Overall, this study holds significant social and scientific importance as it promotes the development of 3D IC technology, improves electronic device performance, and advances scientific research.

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Niranjana, Gurushankar. "Verification Challenge in 3D Integrated Circuits (IC) Design." INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH AND CREATIVE TECHNOLOGY 6, no. 1 (2020): 1–6. https://doi.org/10.5281/zenodo.14383858.

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Three-dimensional integrated circuits (3D ICs) have emerged as a promising solution to overcome the limitations of traditional 2D ICs, offering improved performance, reduced power consumption, and increased functionality. However, the increased complexity introduced by stacking multiple dies vertically presents significant challenges for verification. Traditional verification methodologies are inadequate for 3D ICs due to the intricate interactions between stacked dies, including thermal effects, through-silicon vias (TSVs), and inter-die signaling. We delve into the complexities of verifying these interactions, focusing on the need for accurate modeling and simulation techniques. Furthermore, we discuss the challenges posed by increased design complexity and the need for efficient debugging and validation strategies. New approaches, such as formal verification, advanced simulation, and 3D-specific DFT strategies are needed. This paper provides a comprehensive overview of 3D IC verification challenges to guide future research and development.

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Rao, Xixin, Huizhong Liu, Sai Wang, Jianhao Song, Cheng Jin, and Chengdi Xiao. "Thermal modeling and analysis of three-dimensional integrated circuits with irregular structure." Thermal Science, no. 00 (2023): 61. http://dx.doi.org/10.2298/tsci220805061r.

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Considering the manufacturing and packaging process, three-dimensional integrated circuits design often requires irregular chip structures. Three-dimensional integrated circuits with irregular structures can facilitate differentiated chip design and reduce manufacturing costs. Highly complex through-silicon vias have not been considered in past thermal modeling and analysis of irregularly structured three-dimensional integrated circuits. Thus, a detailed model of a three-layer irregularly structured 3D integrated circuit with through-silicon vias and microbumps is developed, and an analytical method based on the thermal resistance network model is proposed to extract the equivalent thermal conductivity of through-silicon vias and microbumps, the accuracy of which is verified by a 3D finite element simulation method. The results show that the maximum temperature and temperature gradient obtained by the equivalent model simulations agree well with the detailed model results, proving the validity of the equivalent model. To save the computational cost, the effects of heat source area, power setting and through-silicon vias structure parameters on the maximum temperature are studied by numerical simulation method based on the equivalent model. Heat source area equal to the overlap between chip layers, high power chips close to the heat sink, and reducing through-silicon vias pitch can better reduce the maximum temperature. The results provide a reference value for thermal design and optimization of three-dimensional integrated circuits with irregular structures.

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Zhu, Yizhan. "Thermal Management of TSV Array in 3D Integrated Circuits Based on the Super-Element Method." Applied and Computational Engineering 141, no. 1 (2025): 131–38. https://doi.org/10.54254/2755-2721/2025.21790.

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As Moores Law approaches its physical limits, three-dimensional integrated circuits (3D ICs) utilizing Through- Silicon Vias (TSVs) are gradually replacing traditional two-dimensional integrated circuits (2D ICs). However, the highly integrated circuits also introduce more significant thermal issues. In this paper, an optimization method for the positions of multiple heat sources in the TSV array is proposed to minimize the temperature and temperature gradient within the model. This study employs super-element methods for thermal simulations, leverages the superposition principle to reduce the computational cost, and utilizes Simulated Annealing (SA) for position optimization. Experimental results show that the time required for the super-element method to compute the simulation model is approximately 26.4% of that required by FEM. Furthermore, after optimization, the maximum temperature rise, average temperature rise, and temperature gradient of the TSV array are reduced by 4.58%, 0.64%, and 3.78%, respectively, significantly mitigating the thermal effects on the circuit.

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Kapoor, Dipesh, Cher Ming Tan, and Vivek Sangwan. "Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits." Applied Sciences 10, no. 3 (2020): 748. http://dx.doi.org/10.3390/app10030748.

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Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

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Bakir, MuhannadS, Gang Huang, Deepak Sekar, and Calvin King. "3D Integrated Circuits: Liquid Cooling and Power Delivery." IETE Technical Review 26, no. 6 (2009): 407. http://dx.doi.org/10.4103/0256-4602.57826.

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Xiang, Chao, and John E. Bowers. "Building 3D integrated circuits with electronics and photonics." Nature Electronics 7, no. 6 (2024): 422–24. http://dx.doi.org/10.1038/s41928-024-01187-z.

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Gouker, Pascale M., Brian Tyrrell, Richard D'Onofrio, et al. "Radiation Effects in 3D Integrated SOI SRAM Circuits." IEEE Transactions on Nuclear Science 58, no. 6 (2011): 2845–54. http://dx.doi.org/10.1109/tns.2011.2172463.

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Liu, Yunfei, Yuxuan Zhu, Lu Chang, Congwei Liao, Lei Lu, and Shengdong Zhang. "P‐6.13: 3D Stacked Hybrid TFT Integrated Circuits for 1100 PPI AMOLED Display." SID Symposium Digest of Technical Papers 55, S1 (2024): 1030–33. http://dx.doi.org/10.1002/sdtp.17268.

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This paper studies high‐resolution AMOLED displays pixel and driving circuits using 3D stacking LTPS and oxide hybrid TFT integration technology systematically. It is demonstrated the OLED display resolution reaches 1167 PPI when the minimum line width/line spacing is reduced to 1 μm/0.5 μm. In addition, peripheral row and column drive circuits for the high display resolution were also illustrated. Good dynamic performance of the designed driving circuits was obtained thanks to the 3D TFTs.

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Kumar, Malagonda Siva, and Jayavelu Mohanraj. "Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 3 (2024): 2500. http://dx.doi.org/10.11591/ijece.v14i3.pp2500-2507.

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As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement from wave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies.

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Craton, Michael, Mohd Ifwat Mohd Ghazali, Brian Wright, Kyoung Youl Park, Premjeet Chahal, and John Papapolymerou. "3D Printed Integrated Microfluidic Cooling for High Power RF Applications." International Symposium on Microelectronics 2017, no. 1 (2017): 000675–80. http://dx.doi.org/10.4071/isom-2017-poster6_098.

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Abstract This paper presents the design and fabrication of microfluidic channel integration in a plastic substrate using 3D printing. The microfluidic channels are integrated along with a copper plate which the coolant is in direct contact with. To demonstrate the design, a diode intended for switched power supplies is integrated onto the copper plate and its performance characterized. 3D printing or additive manufacturing (AM) allows for fast prototyping of such package designs and can be readily adopted in the fabrication of RF circuits. This paper, to the best of our knowledge, for the first time will demonstrate a 3D printed integrated microfluidic channel for the cooling of electronic circuits. Details of design, fabrication and characterization are presented.

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Dhananjay, Krithika, Prachi Shukla, Vasilis F. Pavlidis, Ayse Coskun, and Emre Salman. "Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 3 (2021): 837–43. http://dx.doi.org/10.1109/tcsii.2021.3051250.

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Gong, Xiao, Kaizhen Han, Chen Sun, et al. "Beol-Compatible Ingazno-Based Devices for 3D Integrated Circuits." ECS Meeting Abstracts MA2022-02, no. 32 (2022): 1186. http://dx.doi.org/10.1149/ma2022-02321186mtgabs.

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Due to its attractive materials and electrical properties, indium-gallium-zinc-oxide (IGZO) has been extensively researched in many emerging technologies, especially for three-dimensional (3D) monolithic integration and back-end-of-line (BEOL) compatible applications [1]. On the pathway toward the realization of high-performance 3D monolithic integrated chips (ICs), a wide range of building blocks with different functionalities are required. 3D monolithic ICs also demand optimization in device performance and circuit architecture design. In this paper, we discuss our recent research development in IGZO-based techniques at both device and circuit levels. This includes nanowire structure for IGZO-based transistors, as well as the BEOL-compatible ferroelectric ternary content-addressable memory (TCAM) and embedded dynamic random-access-memory (eDRAM) for compute-in-memory (CiM) using IGZO-based transistors. A novel digital etch technique for amorphous IGZO (α-IGZO) material as well as the formation of α-IGZO nanowires were realized, enabling high performance α-IGZO nanowire field-effect transistors (NWFETs) with ultra-scaled nanowire width (W NW) [2]. The scanning electron microscopy (SEM) images of α-IGZO nanowire before and after the digital etch show that the nanowire structure as well as W NW reduction after digital etch can be clearly observed. The smallest α-IGZO nanowire after digital etch has a W NW of ~20 nm. By leveraging the ultra-scaled nanowire structure, the NWFET with the smallest W NW achieves decent subthreshold swing of 80 mV/decade as well as high peak extrinsic transconductance (G m,ext) of 612 μS/μm at a drain to source voltage (V DS) = 2 V (456 μS/μm at V DS = 1 V). As compared with previous works in literature, our IGZO NWFET achieves one of the highest peak G m among all IGZO-based FETs. α-IGZO ferroelectric FETs (Fe-FETs) with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure were further realized based on the α-IGZO transistor process modules. The smallest L CH is as small as 40 nm. The cross-sectional transmission electron microscopy (TEM) image of the device shows sharp interface. The α-IGZO Fe-FETs achieve a large memory window of 2.9 V, high endurance of 108 cycles, high conductance ratio, and small cycle-to-cycle variation. By leveraging the low temperature processed α-IGZO Fe-FETs with good electrical characteristics, a BEOL-compatible ferroelectric TCAM circuit with 2 Fe-FETs connected in parallel was realized [3], showing an extremely large sensing margin. In addition, such α-IGZO Fe-FET TCAM reduces the transistor number from 16 to 2 as compared to traditional SRAM-based TCAM. Smaller cell size and higher energy efficiency can also be obtained. IGZO transistors can play an important role in in-memory computing as well. SEM image of the eDRAM CiM cell shows utilization of IGZO transistors. The smallest device has L CH of 45 nm [4]. The IGZO transistor-based eDRAM CiM with differential cell structure achieves low leakage current, low variation, low charge loss sensitivity, and the control-friendly charge-domain computing without DC power. By evaluating the key figure-of-merits, including precision, power efficiency, computing density, retention time, and robustness, it can be concluded that our IGZO transistor-based eDRAM CiM is promising for low-power and scalable compute-in-eDRAM design. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114). References: [1] K. Normura et al., Nature, 432 (7016), 488-492, 2004. [2] K. Han et al., VLSI, 2021, p. T10-1. [3] C. Sun et al., VLSI, 2021, p. T7-4. [4] J. Liu et al., IEDM, 2021, p. 462.

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Tavakkoli, Fatemeh, Siavash Ebrahimi, Shujuan Wang, and Kambiz Vafai. "Analysis of critical thermal issues in 3D integrated circuits." International Journal of Heat and Mass Transfer 97 (June 2016): 337–52. http://dx.doi.org/10.1016/j.ijheatmasstransfer.2016.02.010.

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Kolymagin, D. A., A. I. Prokhodtsov, D. A. Chubich, et al. "3D Microstructures for Introducing Radiation into Photonic Integrated Circuits." Bulletin of the Russian Academy of Sciences: Physics 88, no. 12 (2024): 2016–21. https://doi.org/10.1134/s1062873824708626.

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Bachnak, Nouhad. "MEMS Packaging with 3D-MID Technology." International Symposium on Microelectronics 2011, no. 1 (2011): 000484–90. http://dx.doi.org/10.4071/isom-2011-wa1-paper6.

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3D-MID (three dimensional molded interconnect devices) technology (which is already broadly used for 3D-MID mobile phone antennas) is also used for MEMS packaging and sensors applications. 3D-MID allows miniaturization by the integration of mechanical and electronic functions in one part. The 3D electronic circuit is integrated into a 3D plastic casing or carrier, making it possible to achieve much more compact construction and much greater function density. More and more applications involving electrical and electro-optical circuits are made using 3D-MID technology. Typical 3D-MID applications are: Sensor packaging, LED packaging, security casings, RFIDs and Antennas. The main areas of application are in the automotive, medical, industrial technology and telecommunications sectors.

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Malagonda, Siva Kumar, and Mohanraj Jayavelu. "Electrical signal interference minimization using appropriate core material for 3D integrate circuit at high frequency applications." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 3 (2024): 2500–2507. https://doi.org/10.11591/ijece.v14i3.pp2500-2507.

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As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement fromwave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies.

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Jeon, Sangmin, Hyunseok Kwak, and Woojoo Lee. "A Study of Advancing Ultralow-Power 3D Integrated Circuits with TEI-LP Technology and AI-Enhanced PID Autotuning." Mathematics 12, no. 4 (2024): 543. http://dx.doi.org/10.3390/math12040543.

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The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations.

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Ostling, Mikael, and Per-Erik Hellstrom. "(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1511. http://dx.doi.org/10.1149/ma2023-02301511mtgabs.

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In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects. By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors. In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers. A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistors Fully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices. 3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type. 3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.

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Chen, Boyi. "Application of Photolithography in Integrated Circuits." Applied and Computational Engineering 126, no. 1 (2025): 33–38. https://doi.org/10.54254/2755-2721/2025.20005.

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Integrated circuit (IC) manufacturing relies heavily on lithography, which drives device size reduction and performance improvement through precise pattern transfer. As the performance requirements of electronic devices continue to increase, lithography faces major challenges in terms of precision and efficiency. Currently, deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography technologies are mainstream, while technologies such as electron beam lithography (EBL) and directed self-assembly (DSA) are applied in specific high-precision fields. This paper reviews the current development status of lithography technology and analyzes its application in CMOS technology, 3D NAND flash memory, and high-performance computing components. The study also explores the main challenges facing photolithography, including technical bottlenecks, rising costs, and environmental impacts. In order to address these issues, the study emphasizes the importance of technological innovation and material improvement, especially in the development of new photoresists and mask materials and the promotion of environmentally friendly lithography technology. Therefore, it can be found that continued advances in lithography are essential to meet the changing needs of the semiconductor industry.

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Kim, Woojo, Jimin Kwon, and Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors." Journal of Flexible and Printed Electronics 2, no. 2 (2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.

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Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.

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Li, Mingli, Na Gong, Jinhui Wang, and Zhibin Lin. "Phase Change Material for Thermal Management in 3D Integrated Circuits Packaging." International Symposium on Microelectronics 2015, no. 1 (2015): 000649–53. http://dx.doi.org/10.4071/isom-2015-tha44.

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Effective thermal control and management in three-dimensional electronic packaging are desirable to ensure the heat generated in integrated circuits can be dissipated. Conventional base materials in electronics from substrate to protective layers, due to low coefficient of thermal conductivity, cannot help to cool down the circuits, while such elevated temperature could highly impact the performance of the chips. In this study, phase change material (PCM) is selected for potential applications in thermal management of electronic packaging due to its isothermal nature and high thermal storage capability. PCM based composite is developed through the impregnation technology using highly porous expanded graphite. Heat transfer test results reveal that the PCM based composite displays superior heat storage capacity, while maintaining the favorable feature of thermal and chemical stabilization for electronic applications. Toward the end, the concept of implementation of PCM based composite is proposed in thermal control of 3D integrated circuits. It is expected the proposed composite will improve heat dissipation, and ultimately enhance the performance of the chips.

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Chakrabarty, Krishnendu, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, and Fangming Ye. "Test and Design-for-Testability Solutions for 3D Integrated Circuits." IPSJ Transactions on System LSI Design Methodology 7 (2014): 56–73. http://dx.doi.org/10.2197/ipsjtsldm.7.56.

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Annuar, Syahira, Reza Mahmoodian, Mohd Hamdi, and King-Ning Tu. "Intermetallic compounds in 3D integrated circuits technology: a brief review." Science and Technology of Advanced Materials 18, no. 1 (2017): 693–703. http://dx.doi.org/10.1080/14686996.2017.1364975.

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Zhang, Yu, Anirban Samanta, Kuanping Shang, and S. J. Ben Yoo. "Scalable 3D Silicon Photonic Electronic Integrated Circuits and Their Applications." IEEE Journal of Selected Topics in Quantum Electronics 26, no. 2 (2020): 1–10. http://dx.doi.org/10.1109/jstqe.2020.2975656.

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Thomas, R., J. Li, Sam Ladak, D. Barrow, and P. M. Smowton. "In situ fabricated 3D micro-lenses for photonic integrated circuits." Optics Express 26, no. 10 (2018): 13436. http://dx.doi.org/10.1364/oe.26.013436.

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Sithi Shameem Fathima, S. M. H., and M. Chinnarani. "An efficient encoding technique for 3D integrated switching circuits activities." Materials Today: Proceedings 33 (2020): 4280–84. http://dx.doi.org/10.1016/j.matpr.2020.07.401.

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Zhao, Mingrui, Rajesh Balachandran, Zach Patterson, et al. "Contactless bottom-up electrodeposition of nickel for 3D integrated circuits." RSC Advances 5, no. 56 (2015): 45291–99. http://dx.doi.org/10.1039/c5ra03683f.

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Electrochemical oxidation of silicon by water generates electrons and subsequent chemical etching of silicon dioxide by fluoride based species regenerates the surface. The electrons are conducted through bulk silicon and accepted by nickel ions.

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Doan, N. A. V., D. Milojevic, F. Robert, and Y. De Smet. "A MOO-based Methodology for Designing 3D Stacked Integrated Circuits." Journal of Multi-Criteria Decision Analysis 21, no. 1-2 (2013): 43–63. http://dx.doi.org/10.1002/mcda.1497.

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Kutscher, Alexander, Paula Kalenczuk, Mohammed Shahadha, et al. "Fabrication of Chemofluidic Integrated Circuits by Multi-Material Printing." Micromachines 14, no. 3 (2023): 699. http://dx.doi.org/10.3390/mi14030699.

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Photolithographic patterning of components and integrated circuits based on active polymers for microfluidics is challenging and not always efficient on a laboratory scale using the traditional mask-based fabrication procedures. Here, we present an alternative manufacturing process based on multi-material 3D printing that can be used to print various active polymers in microfluidic structures that act as microvalves on large-area substrates efficiently in terms of processing time and consumption of active materials with a single machine. Based on the examples of two chemofluidic valve types, hydrogel-based closing valves and PEG-based opening valves, the respective printing procedures, essential influencing variables and special features are discussed, and the components are characterized with regard to their properties and tolerances. The functionality of the concept is demonstrated by a specific chemofluidic chip which automates an analysis procedure typical of clinical chemistry and laboratory medicine. Multi-material 3D printing allows active-material devices to be produced on chip substrates with tolerances comparable to photolithography but is faster and very flexible for small quantities of up to about 50 chips.

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Fehmi Chatmen, Mohamed, Adel Baganne, and Rached Tourki. "New design of Network on Chip Based on Virtual Routers." Indonesian Journal of Electrical Engineering and Computer Science 2, no. 1 (2016): 115. http://dx.doi.org/10.11591/ijeecs.v2.i1.pp115-131.

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<p>Network is considered the most convenient way to communicate between different IP integrated into the same chip. Studies have been developed to propose networks with improved performance in terms of latency, power consumption, throughput and quality of service. Most of these networks have been designed based on the 2-dimensional network structure. Recently, with the introduction of the new structure of 3D integrated circuits (3D IC), new works have used this type of circuit to design 3 dimensions on-chip networks. The advantage brought by this new structure is to reduce the average number of hops crossed from the source to the destination, which improves the throughput and the average latency of the network.</p>

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M.Siva, Kumar, S.Neelima, P.Dilleep, T.Avinash, G.Vandana, and C.Raju. "Improved Heat dissipation in Three-Dimensional Integrate Circuits." Journal of Optoelectronics and Communication 6, no. 1 (2024): 28–35. https://doi.org/10.5281/zenodo.10851498.

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<em>This study investigates the impact of incorporating fins onto Thermal Through Silicon Vias (TTSV) and integrating heat spreaders into traditional Three-Dimensional Integrated Circuit (3D IC) structures on heat management. Through simulations conducted using COMSOL Multiphysics, we explore various aspects such as thermal cooling and its influence on potential distribution across the IC under different conditions. We consider three architectures: (1) 3D IC structure without fins and spreaders, (2) TTSV with graphene fins and spreaders, and (3) TTSV with Carbon Nanotube (CNT) fins and spreaders. Our findings reveal that CNT demonstrates superior thermal cooling capabilities compared to Graphene, with a significant difference exceeding 100 K. Additionally, incorporating finned structures with heat spreaders provides an additional cooling advantage of over 400 K. However, from a signal integrity perspective, graphene with fin structures outperforms other configurations. In conclusion, the proposed 3D IC structures offer efficient improvements in thermal management.</em>

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Rohilla, Rajesh. "Optimisation for 3D Integrated Circuits using Continuously Improving Evolutionary Strategy Machine Learning Techniques." INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 05 (2025): 1–9. https://doi.org/10.55041/ijsrem48758.

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Abstract Three-Dimensional Integrated Circuits (3D ICs) are a revolutionary advancement in semiconductor technology, allowing vertical stacking of multiple active device layers to overcome the scaling challenges faced by conventional Two-Dimensional Integrated Circuits (2D ICs). While 3D ICs harness incredible advantages in terms of increased integration density, shorter interconnect length, and increased performance, they also present daunting challenges—primarily, the strong coupling between thermal and timing constraints. These challenges demand strong, multi-objective optimization techniques that can manage 3D ICs' highly non-convex and multi-modal design space. In this paper, we introduce a novel optimization framework based on the Covariance Matrix Adaptation Evolution Strategy (CMA-ES) integrated with a physics-based electro-thermal-timing simulation framework. By comparing CMA-ES with Bayesian optimization, we prove that CMA-ES produces superior convergence, robustness, and solution quality, especially under noisy and high-dimensional objective conditions. Our results evidence spectacular improvements in key figures of merit such as peak temperature, thermal gradients, clock skew, and overall simulation efficiency.

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Soref, Richard. "Reconfigurable Integrated Optoelectronics." Advances in OptoElectronics 2011 (May 4, 2011): 1–15. http://dx.doi.org/10.1155/2011/627802.

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Integrated optics today is based upon chips of Si and InP. The future of this chip industry is probably contained in the thrust towards optoelectronic integrated circuits (OEICs) and photonic integrated circuits (PICs) manufactured in a high-volume foundry. We believe that reconfigurable OEICs and PICs, known as ROEICs and RPICs, constitute the ultimate embodiment of integrated photonics. This paper shows that any ROEIC-on-a-chip can be decomposed into photonic modules, some of them fixed and some of them changeable in function. Reconfiguration is provided by electrical control signals to the electro-optical building blocks. We illustrate these modules in detail and discuss 3D ROEIC chips for the highest-performance signal processing. We present examples of our module theory for RPIC optical lattice filters already constructed, and we propose new ROEICs for directed optical logic, large-scale matrix switching, and 2D beamsteering of a phased-array microwave antenna. In general, large-scale-integrated ROEICs will enable significant applications in computing, quantum computing, communications, learning, imaging, telepresence, sensing, RF/microwave photonics, information storage, cryptography, and data mining.

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Huang, Shou-Yi, and Shih-Hsu Huang. "Memory Grouping for the Built-In Self-Test of Three-Dimensional Integrated Circuits." Electronics 13, no. 18 (2024): 3759. http://dx.doi.org/10.3390/electronics13183759.

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As the complexity of circuit design continues to grow, the development of three-dimensional (3D) integrated circuit (IC) technology has become increasingly vital. While 3D ICs offer faster signal transmission speeds and lower power consumption compared with traditional two-dimensional (2D) ICs, they also pose greater challenges in manufacturing and testing. In memory testing, traditional 2D ICs require only a single testing stage, whereas 3D ICs involve both prebond and postbond testing stages, complicating the memory grouping process. Most existing memory grouping algorithms focus on testing 2D ICs. While one study addressed the memory grouping problem for 3D IC testing, it did not consider the impact of test scheduling. In contrast, our approach incorporates test scheduling into the memory grouping process, resulting in a reduction in BIST area overhead. Experimental results demonstrate that our method reduces built-in self-test circuit area overhead by an average of 10.28% compared with those in the existing literature.

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