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Journal articles on the topic '3D molded interconnect devices'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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Polzinger, Bernhard, Vladimir Matic, Laura Liedtke, et al. "Printing of Functional Structures on Molded 3D Devices." Advanced Materials Research 1038 (September 2014): 37–42. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.37.

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This paper summarizes the results on inkjet printing and characterization of functional structures on molded 2D and 3D devices. Different injection molded thermoplastics, a transfer molded thermoset and polyimide foil as substrate materials were used. Conductive structures were obtained by inkjet printing of a commercial available silver nanoparticle ink. The use of printable acrylic based ink enabled the fabrication of conductor crossovers or multilayers. Results on inkjet printed temperature sensitive structures and an inkjet printed intrusion sensor device as well as an inkjet printed electrical interconnect on a transfer molded package will be presented.

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Cui, Liangyu, Chengjuan Yang, Yanling Tian, and Dawei Zhang. "Development and Application of Molded Interconnect Devices." International Journal of Robotics Applications and Technologies 2, no. 1 (2014): 1–18. http://dx.doi.org/10.4018/ijrat.2014010101.

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With the improvements of electromechanical systems' automation and intelligence, contradiction between the high integration, high performance and miniaturization, low cost has become the principal reason restricting the development of electromechanical system. The emergence of molded interconnection device (MID) technology provides a new way to resolve this contradiction. Integration of the mechanical and electrical functions in electromechanical system onto the same polymer molded base structure, replacement of the tradition printed circuit board (PCB), design and processing of 3D circuit system on polymer molded base structure surface distinguishes MID technology from others. MID technology can not only save space occupied by the electromechanical system and improve the system integration, but also can simplify the assembly process and lower the cost. In this study, present research and future development of MID technology were introduced first. Then the main technical problems involved in MID processing including the design method of MID, materials technology, equipment technology, surface mounted devices (SMD) assembly technique, and so on were analyzed systematically. Finally, using the ultrasonic micro embossing technology, a manufacturing method of polymer circuit board, radio frequency identification (RFID) antenna, microelectrode arrays, and some other polymer foil MID was proposed. Based on the in-depth analysis of polymer foil MID's characteristics, polymer foil MID are expected to have a broad application in the field of microfluidic chip.

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Zhuo, Yong. "Integration of 3D-Routing for the Design of Molded Interconnect Devices." Advanced Materials Research 139-141 (October 2010): 1109–12. http://dx.doi.org/10.4028/www.scientific.net/amr.139-141.1109.

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One of the fundamental innovations in the field of mechatronics is the direct material integration of mechanical and electronic functions using Molded Interconnect Devices (MID technology). Unlike conventional circuit boards, they are not limited to two dimensions but offer the possibility to arbitrarily lay printed circuit traces on the surfaces of the 3D carrier, traditional 2D routing function in EDA cannot be directly applied in MID design. In this paper, two new 3D automatic routing methods are introduced. One method is based on a grid graph and extends Hadlock’s minimum detour algorithm; the other is gridless and combines the A*-algorithm and an extension of Hightower’s algorithm. The related 3D routing functions, which are not supported by conventional MCAD und ECAD systems, are integrated in the design system MIDCAD. With these 3D routing functions, MIDCAD enables a more effective product design based on the MID technology.

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Zhuo, Yong, Juan Peng, and Yan Jun Wu. "Design and Simulation of Molded Interconnect Devices with Two Shot Molding." Advanced Materials Research 295-297 (July 2011): 1651–55. http://dx.doi.org/10.4028/www.scientific.net/amr.295-297.1651.

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Three Dimensional Molded Interconnect Devices (3D-MID) has enormous potential for rationalization in both manufacturing process and the freedom to design of mechatronic products. Two shot molding is one of the most important and commonly used methods among the various MID manufacturing processes. Currently, there is a lack of effective design and simulation tools that can be used for MID with two shot molding. In this paper, an integrated product model using feature technology, some MID-specific design functions, and one special interface based on the API of Moldflow Plastics Insight (MPI) and the COM-Technology are presented. These developed product model, functions and interface increase the efficiency of the MID design process, and the design and simulation integrated environment also towards the rational and optimal design of MID products with two shot molding.

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Siengchin, Suchart, Supakit Chuaping, and Thomas Mann. "Glass Fiber/Polyphthalamide Composites for 3D-Molded Interconnect Devices Application: Structure and Properties." Polymer-Plastics Technology and Engineering 55, no. 15 (2016): 1613–22. http://dx.doi.org/10.1080/03602559.2016.1163599.

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Schmidt, Marc-Peter, Aleksandr Oseev, Christian Engel, Andreas Brose, Bertram Schmidt, and Sören Hirsch. "Flexible free-standing SU-8 microfluidic impedance spectroscopy sensor for 3-D molded interconnect devices application." Journal of Sensors and Sensor Systems 5, no. 1 (2016): 55–61. http://dx.doi.org/10.5194/jsss-5-55-2016.

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Abstract. The current contribution reports about the fabrication technology for the development of novel microfluidic impedance spectroscopy sensors that are directly attachable on 3-D molded interconnect devices (3D-MID) that provides an opportunity to create reduced-scale sensor devices for 3-D applications. Advantages of the MID technology in particular for an automotive industry application were recently discussed (Moser and Krause, 2006). An ability to integrate electrical and fluidic parts into the 3D-MID platform brings a sensor device to a new level of the miniaturization. The demonstrated sensor is made of a flexible polymer material featuring a system of electrodes that are structured on and embedded in the SU-8 polymer. The sensor chips can be directly soldered on the MID due to the electroless plated contact pads. A flip chip process based on the opposite electrode design and the implementation of all fluidic and electrical connections at one side of the sensors can be used to assemble the sensor to a three-dimensional substrate. The developed microfluidic sensor demonstrated a predictable impedance spectrum behavior and a sufficient sensitivity to the concentration of ethanol in deionized water. To the best of our knowledge, there is no report regarding such sensor fabrication technology.

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Wu, Yan Jun, Yong Zhuo, Juan Peng, Xuan Wu, and Xin Zhao. "Kinematic Analysis and Simulation of MID Laser Direct Structuring Equipment." Advanced Materials Research 590 (November 2012): 236–41. http://dx.doi.org/10.4028/www.scientific.net/amr.590.236.

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Molded Interconnect Devices (MID) is an innovative technology in the field of mechatronics which abandons the conventional circuit boards and integrates the mechanical and electronic functions directly on the 3D injection molded thermoplastics. The Laser Direct Structuring (LDS) is the most efficient and advanced technology for the manufacrure of MID. In this paper, LDS technology and equipment have been introduced. Then through kinematic modeling analysis of the LDS equipment, getting the forward and inverse solution of laser focus position in the 3D space. And the LDS equipment processing path has been planned based on the kinematic analysis. Finally the simulation system of LDS has been developed based on Open CASCADE in order to inprove the processing efficiency and quality of MID.

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Bachnak, Nouhad. "MEMS Packaging with 3D-MID Technology." International Symposium on Microelectronics 2011, no. 1 (2011): 000484–90. http://dx.doi.org/10.4071/isom-2011-wa1-paper6.

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3D-MID (three dimensional molded interconnect devices) technology (which is already broadly used for 3D-MID mobile phone antennas) is also used for MEMS packaging and sensors applications. 3D-MID allows miniaturization by the integration of mechanical and electronic functions in one part. The 3D electronic circuit is integrated into a 3D plastic casing or carrier, making it possible to achieve much more compact construction and much greater function density. More and more applications involving electrical and electro-optical circuits are made using 3D-MID technology. Typical 3D-MID applications are: Sensor packaging, LED packaging, security casings, RFIDs and Antennas. The main areas of application are in the automotive, medical, industrial technology and telecommunications sectors.

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Zhuo, Yong, Yan Jun Wu, and Juan Peng. "Design and Simulation of 3D Layout for MID Based on Open CASCADE." Advanced Materials Research 479-481 (February 2012): 1978–81. http://dx.doi.org/10.4028/www.scientific.net/amr.479-481.1978.

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Molded Interconnect Devices (MID) is an innovative technology which abandoned the conventional board and integrates the mechanical and electronic functions directly on materials. Due to the complex process, the existing MCAD and ECAD do not meet the requirements of MID, so an MID prototype system for design and simulation of 3D layout based on Open CASCADE has been developed in this paper. Through studying on the algorithm of 3D automatic routing, realized the functions of placement of 3D electronic components and 3D automatic routing. Also, simulation for 3D laser direct structuring and placement of electronic components with a six-axis robot has come true after studying manufacturing process of MID.

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Zeitler, Jochen, Bernhard Götze, Christian Fischer, and Jörg Franke. "Novel Approach for the Implementation of 3D-MID Compatible Routing Functionalities into Computer-Aided Design Tools." Advanced Materials Research 1038 (September 2014): 11–17. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.11.

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Molded Interconnect Devices can be considered as attractive option for the integration of electronic functions into mechanical systems. While development methods and procedures reached high standards, CAD tools still drag behind. This paper focusses the necessary software structure for implementing of automated routing algorithms or other MID specific extensions into CAD tools. An innovative three-layer model will be introduced and explained in detail. This paper also describes a method for mapping electrical components on unfolded surfaces for the further implementation of the automated routing algorithms.

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Goth, Christian, Thomas Kuhn, Gerald Gion, and Jörg Franke. "Hot Pin Pull Method – New Test Procedure for the Adhesion Measurement for 3D-MID." Advanced Materials Research 1038 (September 2014): 115–20. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.115.

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The adhesion test of metallic structures on MID (Molded Interconnect Devices) parts is an unsolved issue. So far no method really works reliably. The test methods which are conventionally used are the pull-off test and the shear-test. Both show large standard deviation and the reproducibility is not assured. Nordson DAGE has introduced the new micro-material testing system 4000Plus. This device enables a new test method for the determination of the adhesion strength of MID structures using the hot pin pull (hot bump pull) method. Copper pins (tinned or untinned) are heated up with a user defined temperature profile, soldered to a metallized structure on the MID and then removed vertically upward, while the force is recorded. In this contribution investigations with this new test method are presented.

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Yan, Hengfeng, Jimin Chen, and Jinyan Zhao. "3D-MID manufacturing via laser direct structuring with nanosecond laser pulses." Journal of Polymer Engineering 36, no. 9 (2016): 957–62. http://dx.doi.org/10.1515/polyeng-2015-0367.

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Abstract 3D molded interconnect device (3D-MID) is a kind of injection-molded thermoplastic part with integrated electronic circuit traces. Currently, it is a hotspot of the electronic and telecommunication equipment industry. Laser direct structuring (LDS) is the main approach to fabricate 3D-MID. Laser scans and activates the surface of thermoplastic parts. After plating, the activated area is coated with copper. In this study, a model was built to describe the mechanisms of interaction between a substrate and laser. The nanosecond laser was applied in the LDS process to manufacture 3D circuit on 3D-MID. With the aid of variable laser pulse width, the model was confirmed by a series of experiments including investigations of roughness, surface structure and energy spectrum. Finally, critical factors affecting the LDS process were found out. They are effective guides for many LDS applications.

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Marcori, Franco, M. Antonipieri, I. di Vora, S. Padovani, and I. Riolino. "Study of MID Technologies for Automotive Lighting and Light Signaling Devices." Advanced Materials Research 1038 (September 2014): 97–103. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.97.

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The production of Molded Interconnect Devices (MIDs) may be achieved through different processes. In this work Centro Ricerche Plast-optica (CRP) has chosen to evaluate, implement and assess Laser Direct Structuring (LDS) and In Mold Labeling (IML) technologies for the production of MIDs. Both alternative methods have been analyzed starting with a 2D component, mainly used for implementation and optimization of the process, and finally a more complex 3D component, that has been designed and produced. The first phase of the activity regards the production of several conductor patterns on planar substrates dedicated to evaluate properties as conductors resistance, adhesion, SMD components solderability, wire bondability of bare LED dice etc. In the case of IML, a flexible circuit has been over-molded during the production of the component by injection molding process: planar parts have been tested also in terms of adhesion of flexible circuit to the injected polymer. The second phase of the activity concerns the production of 3D circuits. Both technologies have been implemented in order to select to materials, process conditions and parameters, design rules and to verify the reliability in the automotive severe conditions. Exploitation of technologies have been performed on an automotive rear lamp. A prototype has been produced in LDS technology and allowed to define the conditions that make economically affordable this solution. Differently, the IML technology allowed to produce a completely new device by embedding a planar electronic circuits into the plastic material.

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Cheval, K., J. Coulm, S. Gout, et al. "Progress in the Manufacturing of Molded Interconnected Devices by 3D Microcontact Printing." Advanced Materials Research 1038 (September 2014): 57–60. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.57.

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The aim of this paper is to report on the use of Microcontact Printing (μCP) for the manufacturing of 3D Molded Interconnects Devices. Two different approaches are reported. A first one is based on the total metallization of the polymer, μCP of the 3D pattern followed by the wet etching of the non-protected areas of the part (the so-called indirect process). A second approach is based on the combination of radio-frequency (RF) plasma treatment, μCP of a pattern of catalysts on the polymer and metallization by electroless deposition (the so-called direct process). This second process allows metallization of bare polymer parts (free of catalytic species in the bulk) with conductive 3D networks ready for the assembly of SMD devices. Examples of MID devices made with both approaches are reported. Key points like thickness (up to 12-15 μm), conductivity and adhesion of the metallic network are also reviewed. Printing on slope surfaces is demonstrated. Advantages and drawbacks of both processes are discussed.

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Chou, Min Chieh, Tune Hune Kao, Meng Chi Huang, Wen Hua Zhang, Wei Yu Li, and Tzi Huei Lai. "Novel Laser Induced Metallization for Three Dimensional Molded Interconnect Device Applications by Spray Method." Advanced Materials Research 1038 (September 2014): 69–73. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.69.

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A novel laser induced metallization (LIM) is developed for 3 dimensional molded interconnect devices (3D-MIDs). A special laser-activable solution is firstly sprayed on top of the substrate, followed by laser direct structuring (LDS) and the electroless plating. The metal patterns can be transferred from the CAD data on almost any complex surface. Compared to the direct LDS, our spray method has smaller linewidth (30 μm) and much more flexibility on the substrate choosing. For example, the substrate can be plastic, glass, or ceramic. In addition, the laser-activable solution on top of the substrate also plays a role of the insulator. As a result, the multilayer patterns can be made by simply repeating the spray method on the same surface. Moreover, since this method is capable of making patterns layer-by-layer, the capacitors and inductances can be direct integrated with the circuit design. In this report, a 2G/3G/4G (all-in-one) antenna is tested by using our spray method. The return loss reaches the 3:1 VSWR standard, and the radiation efficiency is larger than 60% within the operation frequency.

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Leneke, T., and S. Hirsch. "A Multilayer Process for 3D-Molded-Interconnect-Devices to Enable the Assembly of Area-Array Based Package Types." Transactions of The Japan Institute of Electronics Packaging 2, no. 1 (2009): 104–8. http://dx.doi.org/10.5104/jiepeng.2.104.

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Bachy, Bassim, Robert Süß-Wolf, Li Wang, et al. "Novel Ceramic-Based Material for the Applications of Molded Interconnect Devices (3D-MID) Based on Laser Direct Structuring." Advanced Engineering Materials 20, no. 7 (2018): 1700824. http://dx.doi.org/10.1002/adem.201700824.

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Amend, P., C. Pscherer, T. Rechtenwald, T. Frick, and M. Schmidt. "A fast and flexible method for manufacturing 3D molded interconnect devices by the use of a rapid prototyping technology." Physics Procedia 5 (2010): 561–72. http://dx.doi.org/10.1016/j.phpro.2010.08.084.

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Chen, Scott, Simon Wang, Coltrane Lee, and John Hunt. "Low Cost Chip Last Fanout Package using Coreless Substrate." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 000272–300. http://dx.doi.org/10.4071/2015dpc-ta24.

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Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices. Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.

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Usmani, Sadaf, Emily Rose Aurand, Manuela Medelin, et al. "3D meshes of carbon nanotubes guide functional reconnection of segregated spinal explants." Science Advances 2, no. 7 (2016): e1600087. http://dx.doi.org/10.1126/sciadv.1600087.

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In modern neuroscience, significant progress in developing structural scaffolds integrated with the brain is provided by the increasing use of nanomaterials. We show that a multiwalled carbon nanotube self-standing framework, consisting of a three-dimensional (3D) mesh of interconnected, conductive, pure carbon nanotubes, can guide the formation of neural webs in vitro where the spontaneous regrowth of neurite bundles is molded into a dense random net. This morphology of the fiber regrowth shaped by the 3D structure supports the successful reconnection of segregated spinal cord segments. We further observed in vivo the adaptability of these 3D devices in a healthy physiological environment. Our study shows that 3D artificial scaffolds may drive local rewiring in vitro and hold great potential for the development of future in vivo interfaces.

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Chen, Scott, Simon Wang, Coltrane Lee, Adren Hsieh, John Hunt, and William Chen. "Chip Last Fan Out as an Alternative to Chip First." International Symposium on Microelectronics 2015, no. 1 (2015): 000245–50. http://dx.doi.org/10.4071/isom-2015-wa33.

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Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, and they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), and system in package (SIP) being widely used in these smart phones & mobile devices.. Fan out WLCSP (FOWLP) has great potential to be the next new package for the smart phone mobility application. Two factors have driven fan out WLCSP (FOWLP) package technology in the last few years. The first is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solder ball interconnects. The second and potentially more important factor relates to the demand of the market for more functions. Not all silicon functionality benefits from these advanced nodes, and merely adds to the cost of the die. This has driven the designers to partitioning of desired functionality into multiple die, which in turn requires effective interconnection of these separate die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). Up to date FOWLP used chip first processing, in which the bare die was molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a new alternative to chip first FOWLP, an alternative which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package has been in production in ASE for over a year, and uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented. We have designated this package structure “Fan Out Chip Last Package (FOCLP)” For higher end applications we will show the ability to use a high density substrate process for use in more demanding chip last fan out packages

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Hörber, Johannes, Christian Goth, and Jörg Franke. "Aerosol-Jet Printing for Functionalization of Prototyping Materials for Electronic Applications." International Symposium on Microelectronics 2012, no. 1 (2012): 000741–48. http://dx.doi.org/10.4071/isom-2012-wa65.

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To meet the growing demand for adapted 3D electronic devices, e. g. for customized electronic components as well as for Molded Interconnect Devices in small batches, 3D aerosol-jet printing combined with widely-used rapid prototyping methods like stereolithography and powder bed based printing is investigated. Compared to other printing methods for fine pitch structures, the innovative contact- and maskless aerosol-jetting is advantageous for structuring of spatial substrates. This is due to the large viscosity range of processible inks, a flexible stand-off between substrate and nozzle as well as the focal length of the aerosol beam. Focus of the printing tests on stereolithography materials presented in the paper is the suitability of the nanoparticle silver inks (solvent: water and ethylene glycol, respectively) for additive manufacturing of conductor tracks concerning adhesiveness, conductivity and wettability, which can be improved by plasma treatment. Furthermore, test specimens were assembled by mounting of electronic components using isotropic conductive adhesive. Long term reliability tests of these specimens (thermal cycling at −40 °C/+125 °C; temperature humidity test 85 °C/85 % r. h.) were performed in respect of conductivity of circuit tracks and quality of the adhesive joints. Compared to stereolithography materials aerosol-jet printing on powder bed materials requires adapted processing for functionalization. Due to the rough and porous surface and the low thermal stability of the PMMA powder materials, selective sintering of silver tracks by light was examined as well as printing on PU infiltrated surfaces. Despite of reduced contour definition, good conductivity was achieved.

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Pabo, Eric F., Garrett Oakes, Ron Miller, et al. "Enabling Wafer Level Processes for CIS Manufacturing." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 002393–413. http://dx.doi.org/10.4071/2010dpc-tha36.

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CMOS (Complimentary Metal Oxide Semiconductor) Image Sensors have become ubiquitous, appearing in cars, cell phones, toys and many other devices used in every day life. The primary reason for this increasing presence of CIS (CMOS Image Sensors) is the continual improvement of the performance to cost ratio of these devices. The drivers behind this are the advancements of CMOS image sensor technology such as improved signal to noise ratio as well as advancements in wafer level processing technology related to 3D packaging. Numerous process developments related to both the electrical and optical aspects of 3D packaging of CIS that have enabled this climb up the performance vs. cost curve will be reviewed in this paper with particular attention to:(1) Lens molding – The ability to mold lenses, both spherical and aspherical at the wafer level as well as make full size master stamps from partial masters for lens molding. These lenses can be molded on both sides of a wafer and the lenses aligned to each other;(2) Aligned wafer bonding for optical interconnects consisting of lens stacks and CIS wafer, to allow the thinning of a CIS for BSI (back side illumination), and for electrical interconnects. Together these processes allow the heterogeneous integration of optical and electrical elements at the wafer level and advance the CIS up the performance vs. cost curve.

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TSUKADA, Norikazu. "Molded Interconnect Devices in Japan." Journal of The Surface Finishing Society of Japan 71, no. 4 (2020): 286–87. http://dx.doi.org/10.4139/sfj.71.286.

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Chen, Jyun Yi, and Wen Bin Young. "Two-Component Injection Molding of Molded Interconnect Devices." Advanced Materials Research 628 (December 2012): 78–82. http://dx.doi.org/10.4028/www.scientific.net/amr.628.78.

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Molded Interconnect Device (MID) can be defined as that an injection-molded plastic part combining with electrical and mechanical functions in a single device. This study is to examine the application of micro injection molding technology to the two-component molding process for the MID fabrication. The process involves the first shot of a plastic component with channel patterns on the surface. A second shot by micro injection molding technology is applied to fill the channel with the plateable plastics. The effects of the micro injection molding process parameters on filled line width of the two-component MID will be investigated. It is concluded that, for a MID component, the molding conditions must be designed carefully to keep the thickness variation below the allowable value. It is also found from the experiments that the thickness interference may in the range from 92 m to 196 m to have adequate molding at the second shot.

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Chang, Nam-Hoon, Jeonghee You, and Keun Park. "Fabrication of Molded Interconnect Devices Using Metal Printing." Transactions of the Korean Society of Mechanical Engineers - A 43, no. 8 (2019): 583–89. http://dx.doi.org/10.3795/ksme-a.2019.43.8.583.

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Jürgenhake, Christoph, Christian Fechtelpeter, Roman Dumitrescu, and Daniel Heidsiek. "Optimized Process Sequences for Prototyping of Molded Interconnect Devices." Advanced Materials Research 1038 (September 2014): 19–27. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.19.

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The MID technology offers a high potential for the development of innovative integrated product solutions. The integration of mechanical and electronic functions on a spatial circuit board allows the realization of modules with a high functional density and a significant degree of miniaturization. MID components are spatial injection molded parts, with their surface selectively patterned and metalized. The conventional production of MID applications by an injection molding process is time consuming and expensive. Therefore, the efforts of industry and research show the significance of MID prototyping. Our objective was to develop process overviews and matching sequences for the methodological-assisted prototyping within our MID-Laboratory (MIDLab). First of all, we developed process overviews for any suitable process operations in accordance to the MID reference process. To enable a methodological approach in the production planning, essential information has been summarized in characteristics. The characteristics include a short description of the process and its unique features and a summary of the advantages and disadvantages compared to alternative methods. In addition, the compatibility of subsequent process steps, if limited or restricted, is illustrated. Afterwards, these process steps were combined to production sequences with a focus on costs, benefits and house production. Based on the requirements of the prototype, two scenarios have been developed, covering a wide spectrum of possibilities. In both sequences emphasis has been placed on cost-optimal combinations with a high house production rate. The validation of the results was carried out by two application examples. For this reason demonstrators were designed. On the basis of these modules, the results of the developed process chains were validated.

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Islam, A., H. N. Hansen, P. T. Tang, and J. Sun. "Process chains for the manufacturing of molded interconnect devices." International Journal of Advanced Manufacturing Technology 42, no. 9-10 (2008): 831–41. http://dx.doi.org/10.1007/s00170-008-1660-9.

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METAYER, Pascal. "3D-CERAMIC INTERCONNECTION DEVICES." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, CICMT (2011): 000306–11. http://dx.doi.org/10.4071/cicmt-2011-tha25.

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Electronic packaging can benefit from 3D interconnect devices that combine mechanical and electrical functions on a single 3D-shape part. Design freedom, miniaturisation, simple assembly process, low cost and reliability are some of the advantages that stimulate innovation or replacement of existing products. This monolithic concept was developed for high volume production with moulded thermoplastics as materials used for circuit carriers. Ceramic counterparts have been implemented so far to a smaller extent although their thermal, mechanical and dielectric make them suitable for applications requiring high dimensional stability. This article presents the use of ceramics for 3D-interconnect devices. Ceramics properties will be highlighted with some existing applications. Fabrication processes will be overviewed with emphasis on laser structuring.

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NIINO, Toshiki, and Akifumi NAKAMURA. "Circuit Pattern Structuring of Molded Interconnect Devices by Transmission Laser Beam." Journal of the Japan Society for Precision Engineering 76, no. 9 (2010): 1088–92. http://dx.doi.org/10.2493/jjspe.76.1088.

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Orlob, C., D. Kornek, S. Preihs, and I. Rolfes. "Comparison of methods for broadband electromagnetic characterization of Molded Interconnect Device materials." Advances in Radio Science 7 (May 18, 2009): 11–15. http://dx.doi.org/10.5194/ars-7-11-2009.

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Abstract. Combining the Molded Interconnect Device technology with the Laser Direct Structuring technology exhibits the potential of designing electrical and mechanical components on three-dimensional surfaces to increase functionality, level of integration and to reduce costs. When taking advantage of this technology especially in the design of RF devices, a precise knowledge of the electromagnetic parameters of the MID material is required, as the complex permeability and permittivity strongly influence the device performance. At present time, these materials are not electromagnetically characterized in the RF frequency range. In this paper different methods are therefore presented and compared with respect to their potentials for broadband electromagnetic characterization of Molded Interconnect Device materials.

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Leneke, Thomas, Soeren Hirsch, and Bertram Schmidt. "A multilayer process for the connection of fine‐pitch‐devices on molded interconnect devices (MIDs)." Circuit World 35, no. 2 (2009): 23–29. http://dx.doi.org/10.1108/03056120910953286.

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Tengsuthiwat, Jiratti, Mavinkere Rangappa Sanjay, Suchart Siengchin, and Catalin I. Pruncu. "3D-MID Technology for Surface Modification of Polymer-Based Composites: A Comprehensive Review." Polymers 12, no. 6 (2020): 1408. http://dx.doi.org/10.3390/polym12061408.

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The three-dimensional molded interconnected device (3D-MID) has received considerable attention because of the growing demand for greater functionality and miniaturization of electronic parts. Polymer based composite are the primary choice to be used as substrate. These materials enable flexibility in production from macro to micro-MID products, high fracture toughness when subjected to mechanical loading, and they are lightweight. This survey proposes a detailed review of different types of 3D-MID modules, also presents the requirement criteria for manufacture a polymer substrate and the main surface modification techniques used to enhance the polymer substrate. The findings presented here allow to fundamentally understand the concept of 3D-MID, which can be used to manufacture a novel polymer composite substrate.

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Liu, Ren-Hao, and Wen-Bin Young. "The application of carbon black and printing ink technology in molded interconnect devices." Journal of Polymer Engineering 34, no. 5 (2014): 395–403. http://dx.doi.org/10.1515/polyeng-2013-0292.

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Abstract In this article, the processing of molded interconnect devices (MIDs) was studied via in-mold decoration (IMD) molding technology. A screen printing process using carbon black and printing ink was proposed in the study. For comparison, various conductivity materials such as copper powder, iron powder, carbon black and silver composite were studied with the screen printing method. The results show that there is no electrical conductivity for the ink containing copper or iron powder up to 90% concentration. The low cost carbon black with printing ink was shown to be successful for the IMD process.

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Liu, Ren Hao, Wen-Bin Young, and Hsu Pe Ming. "Design of the printing pattern on film for three-dimensional molded interconnect devices." Advances in Polymer Technology 37, no. 6 (2017): 1722–31. http://dx.doi.org/10.1002/adv.21830.

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Soltani, Mahdi, Moritz Freyburger, Romit Kulkarni, Rainer Mohr, Tobias Groezinger, and André Zimmermann. "Development and Validation of a Novel Setup for LEDs Lifetime Estimation on Molded Interconnect Devices." Instruments 2, no. 4 (2018): 28. http://dx.doi.org/10.3390/instruments2040028.

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Higher energy efficiency, more compact design, and longer lifetime of light-emitting diodes (LEDs) have resulted in increasing their market share in the lighting industry, especially in the industries of consumer electronics, automotive, and general lighting. Due to their robustness and reliability, LEDs have replaced conventional light sources, such as fluorescent lamps. Many studies are examining the reliability of LEDs as such or investigating their long-term behavior on standard printed circuit boards (PCB). However, the thermal performance of LEDs mounted on nonconventional substrates is still not explored enough. An interesting example for this is the molded interconnect devices (MID), which are well known for the great design freedom and the great potential for functional integration. These characteristics not only underline the main abilities of the MID technology, but also present some challenges concerning thermal management. The long-term behavior of LEDs on MID is still quite untapped and this prevents this technology from consolidating its existence. In this context, this work highlights a developed test setup aimed at investigating LEDs, mounted on molded interconnect devices, under combined stress conditions. The results of the reliability study, as well as the resulting lifetime model, are also illustrated and discussed.

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Soltani, Mahdi, Moritz Freyburger, Romit Kulkarni, Rainer Mohr, Tobias Groezinger, and Andre Zimmermann. "Reliability Study and Thermal Performance of LEDs on Molded Interconnect Devices (MID) and PCB." IEEE Access 6 (2018): 51669–79. http://dx.doi.org/10.1109/access.2018.2869017.

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Wang, B., W. Eberhardt, and H. Kück. "Metal deposition on liquid crystal polymers for molded interconnect devices using physical vapor deposition." Journal of Adhesion Science and Technology 18, no. 8 (2004): 883–91. http://dx.doi.org/10.1163/156856104840480.

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Xu, Wen Jin. "Research on MID Application in RFID Based on Intelligent Materials." Advanced Materials Research 282-283 (July 2011): 244–47. http://dx.doi.org/10.4028/www.scientific.net/amr.282-283.244.

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In this paper, the three-dimensional molding mechanical and electrical integration unit Molded Interconnect Devices (MID) is introduced. It is a new type of electronic component. And the following part of the article presents the Internet of Things (IOT). From the design and manufacture process, the paper describes the possibility and necessity using MID in IOT technology, as RFID and Embedded System. In the end, the MID design process is presented.

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Unnikrishnan, Divya, Darine Kaddour, Smail Tedjini, Eloise Bihar, and Mohamed Saadaoui. "CPW-Fed Inkjet Printed UWB Antenna on ABS-PC for Integration in Molded Interconnect Devices Technology." IEEE Antennas and Wireless Propagation Letters 14 (2015): 1125–28. http://dx.doi.org/10.1109/lawp.2015.2395535.

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Schirmer, Julian, Jewgeni Roudenko, and Marcus Reichenberger. "Electrical Functionalization of Interconnect Devices by Digital Printing - Evaluation of Properties and Long-Term Behaviour." Applied Mechanics and Materials 882 (July 2018): 190–98. http://dx.doi.org/10.4028/www.scientific.net/amm.882.190.

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Digital printing technologies are becoming increasingly important for modern electronics production. Besides inkjet printing for low viscosity inks, jetting of pasty materials such as PTF can be a viable alternative to traditional subtractive or additive metallization methods in the future. Hybrid printed electronics, a combination of printed circuitry with classical electronic components, offers many advantages such as low cost, environmental sustainability and others. Until now, the mechanical and electrical properties of printed pastes on molded substrates have not been investigated in detail, just as little as the long-term characteristics of interconnection technologies necessary to mount traditional electronic components onto printed substrates. In different test series, electrical resistance and adhesion of a special PTF material have been investigated. The long-term behavior of the material itself and three alternative interconnection technologies for mounting of SMT components has been evaluated. Results are encouraging, although still a lot of improvements are necessary.

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Feldmann, K., and A. Brand. "Analytical and Experimental Research on Assembly Systems for Molded Interconnection Devices (3D-MID)." CIRP Annals 43, no. 1 (1994): 15–18. http://dx.doi.org/10.1016/s0007-8506(07)62153-2.

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Soussan, Philippe, Kristof Vaesen, Bart Vereecke, and Jian Zhu. "Towards 200mm 3D RF interposer technology." International Symposium on Microelectronics 2015, no. 1 (2015): 000055–61. http://dx.doi.org/10.4071/isom-2015-tp25.

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With the advent of modern and autonomous electronics, applications using RF (radio frequencies) up to millimeter waves and beyond are proliferating. The systems integration becomes increasingly challenging due to variety of devices and passives that typically compose such RF modules, and careful choices of materials are needed for low loss interconnects. One way to minimize RF losses is to integrate the module with high performance interconnect using Si technology, where the different device are mounted on the interposer and the passive are integrated into the silicon. Thanks to the TSV (Through Silicon Via) technology and use of High Resistivity Si substrate, it is possible to have small form factor modules. Such integration approach allows to benefit from the well-established base of 200mm foundries together with the recent progress made in High Resistivity substrate manufacturing. In this work, the process development of a 3D RF interposer technology based on a 200mm process line is reported. The build-up contains 2 levels of metals processed by Cu damascene technology, including a thick 2μm top metal for the lower frequencies applications, an integrated MIM (Metal Insulator Metal) capacitor and use trough silicon via in 5kOhm high resistivity 85μm thick substrate. The TSV are 20μm diameter and 85μm deep made in via first manner with via reveal using temporary carrier handling. Various RF passivation techniques for the silicon have been investigated and a comparison to quartz based on similar test structure is discussed.. Variety of passive devices, transmission line and filter have been processed and characterized. The technology yields 1μm pitch interconnect routing layer, a line loss of 0.34 dB/mm at 40 GHz, and high quality factors inductors larger than 30.

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Rechel, M., S. Bengsch, and M. C. Wurz. "Electroplating through Fluidic Channels as Production Technology for 3D Interconnect Devices and Sensing Structures." ECS Transactions 75, no. 7 (2016): 25–32. http://dx.doi.org/10.1149/07507.0025ecst.

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Buschhaus, Arnd, and Jörg Franke. "Usage of Industrial Robots as Flexible Handling Devices Supporting the Process of Three Dimensional Conductive Pattern Generation." Advanced Materials Research 1038 (September 2014): 89–94. http://dx.doi.org/10.4028/www.scientific.net/amr.1038.89.

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Due to their vast number of benefits, plenty of complex and miniaturized three dimensional molded interconnect devices are developed. One especially demanding process step during their manufacturing is the geometrical exact creation of the conductive pattern layout on the different substrates’ faces. Therefore, sophisticated and flexible technologies like laser direct structuring or printing processes can be used, which are subject to multiple research activities, concentrating for example on coating materials or process parameters. An additional aspect is the necessity of providing a flexible and sufficiently accurate handling device, which three dimensionally moves the substrate relative to the process nozzle applying the coating material. For this task industrial robots could be used, which inherit multiple beneficial features. One main drawback of using this type of kinematic is their relative low absolute accuracy of a few hundred microns, which is not sufficient for moving the substrate during the process with the needed accuracy.

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Darveaux, Robert. "Escalating Challenges in Developing Complex Solutions for Next Generation Package and Interconnect Technologies." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 001306–53. http://dx.doi.org/10.4071/2012dpc-keynote_fc_wlp_amkor.

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There are several application and device trends driving IC package development today. Among the most prevalent are:- Form factor reduction for handheld devices- Increased functionality requiring higher bandwidth- Higher power dissipation- Higher operating frequencies resulting in reduced electrical noise margins- Increased use of sensors- Full conversion to green material sets- Silicon node progression. These trends occur concurrently in many applications, which often results in conflicting requirements. In addition, the market continues to apply relentless pricing pressure on the supply chain. Hence, simple, cost-effective solutions are mandatory. This presentation will highlight packaging technology developments that address the device and application trends listed above. Several innovative packaging platforms will be discussed:- Copper pillar CSP and BGA- Through Mold Via Package on Package (TMV ® PoP)- Flip Chip Molded BGA (FCMBGA)- Wafer Level CSP- Through Silicon Via CSP and BGA. In each case a clear value proposition will be presented, along with key supporting data. It is truly an exciting time to be part of the industry solving complex packaging and interconnect challenges.

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Becker, K. F., T. Braun, A. Neumann, et al. "A New Wafer Level Packaging Approach: Encapsulation, Metallization and Laser Structuring for Advanced System in Package Manufacturing." Journal of Electronic Packaging 127, no. 1 (2005): 1–6. http://dx.doi.org/10.1115/1.1846058.

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One of the general trends in microelectronics packaging is the constant miniaturization of devices. This has led to the development of maximum miniaturization of components on Si level, i.e., CSPs and Flip Chips. To further integrate more functionality into devices, and to further increase the degree of miniaturization, packaging development focus is switching from single chip packaging to the realization of systems in package, SiPs. Two main approaches do exist to realize this goal: one is to integrate all components into one dedicated package, yielding maximum miniaturization for a special application, but little flexibility as far as system design is concerned. The other is to create modular stackable components that can be assembled into a functional system. This integrates both flexibility in system design by exchangeable components and increased reliability potential, as single components can be tested separately. This last approach was considered a promising choice for the generation of SiPs. Within this paper a packaging process is introduced that allows the wafer level manufacturing of stackable, encapsulated devices. Using a transfer molded epoxy demonstrator, a proof-of-concept is performed showing the feasibility of the stackable package approach. This is achieved by combining wafer level encapsulation and molded interconnect device technology. An electroless process for metallization and laser techniques for structuring the metallization layer have been applied to generate structures for reliable interconnects capable for the use of lead-free solders. Summarized, this paper presents the process development and feasibility analysis of wafer level packaging technologies for modular SiP solutions based on a duromer MID approach.

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Yazdani, Farhang, and John Park. "Pathfinding and Design Optimization of 2.5D/3D devices in the context of multiple PCBs." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (2014): 002008–35. http://dx.doi.org/10.4071/2014dpc-tha23.

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As the 2.5D/3D integration technologies shapes the future of semiconductor industry, pathfinding methodology and design optimization of such integration is still at its infancy. 2.5D/3D device integration generates ultra-high density interconnect between the devices. Planning and defining 2.5D/3D I/O cell placement in the context of the overall system is one challenge, optimizing such integration for performance and cost is another challenge. Defining 2.5D/3D partitions and integration feasibility at the early stages of product development is even more pronounced. Often, such early pathfinding feasibility and early assessment of the integration had direct impact on successful product. In this paper, we disclose pathfinding and optimization methodology for integrating 2.5D/3D devices on silicon interposer in the context of multiple PCBs. Various integration schemes are investigated and trade offs are demonstrated. Additionally, we demonstrate constraint based signal assignment for early 2.5D/3D product evaluation and feasibility study. This paper teaches and contributes to rapid integration of 2.5D/3D devices in the context of multiple systems.

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Ghannam, Ayad, Alessandro Magnani, David Bourrier, and Thierry Parra. "Wafer Level 3D System Integration using a Novel 3D-RDL Technology." International Symposium on Microelectronics 2015, no. 1 (2015): 000092–97. http://dx.doi.org/10.4071/isom-2015-tp36.

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A new wafer-level 3D system integration process that relies on a novel multi-level 3D redistribution layer technology (3D-RDL) to interconnect chips together as well as to the substrate was developed. The 3D-RDL technology is based on a single electroplating step that allows routing high density, auto-adaptive vertical copper interconnects (20 μm Line/Space “L/S”) at the edge of known-good dies as well as redistribution layer on top of the die and the substrate. Furthermore, this technology enables 3D interconnection of stacked dies using a single 3D-RDL layer. Additionally, high performance 3D inductive devices with small form factor can be integrated above-IC or above-substrate using the same 3D-RDL processing steps. These capabilities allow miniaturization and performance enhancement and make the technology ideal for various applications requiring functional heterogeneous system integration on a small footprint, such as systems for mobile and Internet-of-Things (IoT) applications, MEMS and Sensors.

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Reed, Jason D., Matthew Lueck, Chris Gregory, Alan Huffman, John M. Lannon, and Dorota S. Temple. "Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration." International Symposium on Microelectronics 2010, no. 1 (2010): 000028–35. http://dx.doi.org/10.4071/isom-2010-ta1-paper5.

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The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10μm and 15μm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (&lt;100 mΩ), high yielding (99.99 % individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 22 consecutive bond pairs was made with the mechanical key, resulting in 98 % aggregate channel yield at 10μm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The results of thermal cycling and humidity-temperature testing on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made. Low temperature bonding (at 210°C, below the melting point of tin) is demonstrated to produce high electrical yield, high shear strength and similar intermetallic compound formation to devices bonded at 300°C. The low temperature process may prove useful for integrating IC devices that have low thermal budgets.

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