Relevant bibliographies by topics / 3D ReRAM

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic '3D ReRAM'

Author: Grafiati
Published: 19 July 2023
Last updated: 31 July 2025

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Journal articles on the topic "3D ReRAM"

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Hudec, Boris, I.-Ting Wang, Wei-Li Lai, et al. "Interface engineered HfO2-based 3D vertical ReRAM." Journal of Physics D: Applied Physics 49, no. 21 (2016): 215102. http://dx.doi.org/10.1088/0022-3727/49/21/215102.

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Lee, Edward, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim, and Saibal Mukhopadhyay. "A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process." ACM Journal on Emerging Technologies in Computing Systems 18, no. 1 (2022): 1–20. http://dx.doi.org/10.1145/3466681.

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We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated Re
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Walden, Candace, Devesh Singh, Meenatchi Jagasivamani, et al. "Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache." ACM Transactions on Architecture and Code Optimization 18, no. 4 (2021): 1–26. http://dx.doi.org/10.1145/3462632.

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Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU’s last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache an
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Kim, Bokyung, Edward Hanson, and Hai Li. "An Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 5 (2021): 1600–1604. http://dx.doi.org/10.1109/tcsii.2021.3067840.

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Fernanda Hernández, Leonardo Sánchez, Gabriela González, and Andrés Ramírez. "Revolutionizing CMOS VLSI with Innovative Memory Design Techniques." Fusion of Multidisciplinary Research, An International Journal 3, no. 2 (2022): 366–79. https://doi.org/10.63995/bduh3010.

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The revolution in CMOS VLSI (Complementary Metal-Oxide-Semiconductor Very-Large-Scale Integration) technology is being driven by innovative memory design techniques that address the ever-growing demand for faster, smaller, and more power-efficient devices. Traditional memory architectures are being reimagined to overcome limitations in speed, density, and energy consumption. Techniques such as multi-level cell (MLC) storage, resistive RAM (ReRAM), and spin-transfer torque magnetic RAM (STT-MRAM) are at the forefront of this transformation, offering significant improvements over conventional SR
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Sun, Chao, Kousuke Miyaji, Koh Johguchi, and Ken Takeuchi. "A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 2 (2014): 382–92. http://dx.doi.org/10.1109/tcsi.2013.2268111.

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Hassanpour, Mehdi, Marc Riera, and Antonio González. "A Survey of Near-Data Processing Architectures for Neural Networks." Machine Learning and Knowledge Extraction 4, no. 1 (2022): 66–102. http://dx.doi.org/10.3390/make4010004.

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Data-intensive workloads and applications, such as machine learning (ML), are fundamentally limited by traditional computing systems based on the von-Neumann architecture. As data movement operations and energy consumption become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as Near-Data Processing (NDP), machine learning, and especially neural network (NN)-based accelerators has grown significantly. Emerging memory technologies, such as ReRAM and 3D-stacked, are promising for efficiently architecting NDP-based accelerators for NN due to the
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Gugnani, Shashank, Arjun Kashyap, and Xiaoyi Lu. "Understanding the idiosyncrasies of real persistent memory." Proceedings of the VLDB Endowment 14, no. 4 (2020): 626–39. http://dx.doi.org/10.14778/3436905.3436921.

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High capacity persistent memory (PMEM) is finally commercially available in the form of Intel's Optane DC Persistent Memory Module (DCPMM). Researchers have raced to evaluate and understand the performance of DCPMM itself as well as systems and applications designed to leverage PMEM resulting from over a decade of research. Early evaluations of DCPMM show that its behavior is more nuanced and idiosyncratic than previously thought. Several assumptions made about its performance that guided the design of PMEM-enabled systems have been shown to be incorrect. Unfortunately, several peculiar perfor
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Husni, M. Afif Rijal, and Aedil Yusuf Afandi. "Perancangan Tata Letak Ruang Unit Rekam Medis Guna Kelancaran Pelayanan Rekam Medis Elektronik di RSU Anna Medika Madura." NURSING UPDATE : Jurnal Ilmiah Ilmu Keperawatan P-ISSN : 2085-5931 e-ISSN : 2623-2871 15, no. 2 (2024): 542–51. http://dx.doi.org/10.36089/nu.v15i2.2250.

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Tata letak ruang adalah penataan sarana dan prasarana kerja petugas yang memadai dengan jarak ideal sehingga menimbulkan kenyamanan bagi para pegawai dalam melakukan pekerjaanya. Di RSU Anna Medika Madura berada pada tahap persiapan menuju Rekam Medis Elektronik. Di RSU Anna Medika Madura diketahui bahwa penyimpanan rekam medis masih menggunakan Roll O Pack dan rak terbuka, ruang pengelolaan rekam medis yang sempit dikarenakan meja kerja petugas saling berdempetan, peneliti bertujuan untuk merancang tata letak ruang di ruang rekam medis berdasarkan metode Mark Karlen. Metode yang digunakan ada
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Qolbi, M. Mahbub Jauhar, and Mochammad Choirur Roziqin. "Desain Ruang Unit Kerja Rekam Medis Berdasarkan Aspek Ergonomi Di Puskesmas Senduro." J-REMI : Jurnal Rekam Medik dan Informasi Kesehatan 4, no. 1 (2022): 24–31. http://dx.doi.org/10.25047/j-remi.v4i1.3347.

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Kenyamanan lingkungan kerja dapat membantu dalam meningkatkan produktivitas kerja parapetugas dalam memberi pelayanan di Puskesmas, sehingga pasien mendapatkan pelayananmaksimal. Ruang kerja unit rekam medis di Puskesmas Senduro belum memenuhi aspekkenyamanan dikarenakan keadaan ruangan yang sempit hanya berukuran 9 m2sehinggaberdampak terhadap pelayanan dan ruang filing yang berukuran 7,5 m2tidak sesuai denganstandar minimal yaitu sebesar 20 m2. Meja, kursi dan rak filing memiliki ukuran yang tidaksesuai dengan antropometri petugas serta sarana dan prasana lain yang masih belum sesuaidengan k
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Dissertations / Theses on the topic "3D ReRAM"

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Ezzadeen, Mona. "Conception d'un circuit dédié au calcul dans la mémoire à base de technologie 3D innovante." Electronic Thesis or Diss., Aix-Marseille, 2022. http://theses.univ-amu.fr.lama.univ-amu.fr/221212_EZZADEEN_955e754k888gvxorp699jljcho_TH.pdf.

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Avec le développement de l'internet des objets et de l'intelligence artificielle, le "déluge de données" est une réalité, poussant au développement de systèmes de calcul efficaces énergétiquement. Dans ce contexte, en effectuant le calcul directement à l'intérieur ou à proximité des mémoires, le paradigme de l'in/near-memory-computing (I/NMC) semble être une voie prometteuse. En effet, les transferts de données entre les mémoires et les unités de calcul sont très énergivores. Cependant, les classiques mémoires Flash souffrent de problèmes de miniaturisation et ne semblent pas facilement adapté
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Conference papers on the topic "3D ReRAM"

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Li, Jiancong, Shengguang Ren, Yi Li, et al. "Demonstration of a Floating-point Deep Neural Matrix Equation Solver using 3D Vertical ReRAM with High Energy- and Area-Efficiency." In 2024 IEEE International Electron Devices Meeting (IEDM). IEEE, 2024. https://doi.org/10.1109/iedm50854.2024.10873550.

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Fukuda, Natsuki, Yutaka Nishioka, and Koukou Suu. "TaOx-based ReRAM stack with NbOx-based selector for 3D cross-point ReRAM application." In 2014 Silicon Nanoelectronics Workshop (SNW). IEEE, 2014. http://dx.doi.org/10.1109/snw.2014.7348604.

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Lee, Edward, Daehyun Kim, Venkata Chaitanya Krishna Chekuri, Yun Long, and Saibal Mukhopadhyay. "A ReRAM Memory Compiler with Layout-Precise Performance Evaluation." In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). IEEE, 2019. http://dx.doi.org/10.1109/s3s46989.2019.9320750.

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Yi-Chung Chen, Hai Li, Yiran Chen, and R. E. Pino. "3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763289.

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Huangfu, Wenqin, Shuangchen Li, Xing Hu, and Yuan Xie. "RADAR: A 3D-ReRAM based DNA Alignment Accelerator Architecture." In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC). IEEE, 2018. http://dx.doi.org/10.1109/dac.2018.8465882.

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Adam, Gina C., Bhaswar Chrakrabarti, Hussein Nili, et al. "3D ReRAM arrays and crossbars: Fabrication, characterization and applications." In 2017 IEEE 17th International Conference on Nanotechnology (IEEE-NANO). IEEE, 2017. http://dx.doi.org/10.1109/nano.2017.8117387.

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Velasquez, Alvaro, and Sumit Kumar Jha. "Computation of Boolean matrix chain products in 3D ReRAM." In 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2017. http://dx.doi.org/10.1109/iscas.2017.8050962.

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Chien, W. C., F. M. Lee, Y. Y. Lin, et al. "Multi-layer sidewall WOX resistive memory suitable for 3D ReRAM." In 2012 IEEE Symposium on VLSI Technology. IEEE, 2012. http://dx.doi.org/10.1109/vlsit.2012.6242507.

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Huang, Yu, Long Zheng, Xiaofei Liao, Hai Jin, Pengcheng Yao, and Chuangyi Gui. "RAGra: Leveraging Monolithic 3D ReRAM for Massively-Parallel Graph Processing." In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019. http://dx.doi.org/10.23919/date.2019.8715192.

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Liu, Bosheng, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen, Yinhe Han, and Peng Liu. "F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM." In 2021 58th ACM/IEEE Design Automation Conference (DAC). IEEE, 2021. http://dx.doi.org/10.1109/dac18074.2021.9586135.

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Journal articles
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