Academic literature on the topic '5T'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic '5T.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Journal articles on the topic "5T"
Wahyudin, Agus, Y. Yuwariah, Fiky Yulianto W, and A. F. Kevin A. "Respons Tanaman Jagung (Zea mays L.) Hibrida Akibat Jarak Tanam Berbeda Pada Sistem Tatam Legowo (2:1) Dan Jenis Pupuk Organik Di Inceptisols Jatinangor." Paspalum: Jurnal Ilmiah Pertanian 6, no. 1 (April 1, 2018): 20. http://dx.doi.org/10.35138/paspalum.v6i1.74.
Full textKim, Young-Ok, Hee Jeong Kong, Sooyeon Park, So-Jung Kang, Kyung-Kil Kim, Dae Yeon Moon, Tae-Kwang Oh, and Jung-Hoon Yoon. "Paracoccus fistulariae sp. nov., a lipolytic bacterium isolated from bluespotted cornetfish, Fistularia commersonii." International Journal of Systematic and Evolutionary Microbiology 60, no. 12 (December 1, 2010): 2908–12. http://dx.doi.org/10.1099/ijs.0.021808-0.
Full textMantovani, Vilma, Paolo Garagnani, Paola Selva, Cesare Rossi, Simona Ferrari, Marinella Cenci, Nilla Calza, Vincenzo Cerreta, Donata Luiselli, and Giovanni Romeo. "Simple Method for Haplotyping the Poly(TG) Repeat in Individuals Carrying the IVS8 5T Allele in the CFTR Gene." Clinical Chemistry 53, no. 3 (March 1, 2007): 531–33. http://dx.doi.org/10.1373/clinchem.2006.074807.
Full textYang, He, Jian Hai Yue, and Jian Yan. "5T Information Fusion System Based on Train Technology Scheme Design." Applied Mechanics and Materials 599-601 (August 2014): 1229–32. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.1229.
Full textSIAD, M. B., Z. EL JOUAD, A. KHELIL, A. MOHAMMED KRARROUBI, S. MORSLI, G. NECULQUEO, M. ADDOU, J. C. BERNÈDE, and L. CATTIN. "COMPARISON OF PERFORMANCES OF ORGANIC PHOTOVOLTAIC CELLS USING SubPc AS CENTRAL AMBIPOLAR LAYER IN TERNARY STRUCTURES AND AS ELECTRON ACCEPTOR IN BINARY STRUCTURES." Surface Review and Letters 27, no. 07 (December 11, 2019): 1950184. http://dx.doi.org/10.1142/s0218625x19501841.
Full textYoon, Jung-Hoon, So-Jung Kang, Soo-Young Lee, Jung-Sook Lee, and Tae-Kwang Oh. "Kangiella geojedonensis sp. nov., isolated from seawater." International Journal of Systematic and Evolutionary Microbiology 62, Pt_3 (March 1, 2012): 511–14. http://dx.doi.org/10.1099/ijs.0.029314-0.
Full textYoon, Jung-Hoon, Yong-Taek Jung, and Jung-Sook Lee. "Loktanella litorea sp. nov., isolated from seawater." International Journal of Systematic and Evolutionary Microbiology 63, Pt_1 (January 1, 2013): 175–80. http://dx.doi.org/10.1099/ijs.0.039198-0.
Full textHe, Hairong, Chongxi Liu, Junwei Zhao, Wenjun Li, Tong Pan, Lingyu Yang, Xiangjing Wang, and Wensheng Xiang. "Streptomyces zhaozhouensis sp. nov., an actinomycete isolated from candelabra aloe (Aloe arborescens Mill)." International Journal of Systematic and Evolutionary Microbiology 64, Pt_4 (April 1, 2014): 1096–101. http://dx.doi.org/10.1099/ijs.0.056317-0.
Full textPark, Sooyeon, So-Jung Kang, Tae-Kwang Oh, and Jung-Hoon Yoon. "Roseivivax lentus sp. nov., isolated from a tidal flat sediment, and emended description of the genus Roseivivax Suzuki et al. 1999." International Journal of Systematic and Evolutionary Microbiology 60, no. 5 (May 1, 2010): 1113–17. http://dx.doi.org/10.1099/ijs.0.014795-0.
Full textShen, Liang, Yongqin Liu, Zhengquan Gu, Tandong Yao, Baiqing Xu, Ninglian Wang, Nianzhi Jiao, Hongcan Liu, and Yuguang Zhou. "Arcticibacter eurypsychrophilus sp. nov., isolated from ice core." International Journal of Systematic and Evolutionary Microbiology 65, Pt_2 (February 1, 2015): 639–43. http://dx.doi.org/10.1099/ijs.0.066365-0.
Full textDissertations / Theses on the topic "5T"
Carlson, Ingvar. "Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2286.
Full textThis thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre.
Shaik, Khajaahmad. "High-speed low-power 0.5-V 28-nm FD-SOI 5T-cell SRAMs." Thesis, Paris 6, 2016. http://www.theses.fr/2016PA066046.
Full textThe goal of the thesis is to achieve 0.5-V high-speed low-power SRAMs. To do so, state-of-the-art SRAM cells, arrays, and bus-architectures are reviewed. The challenging issues are then clarified as 1) reduction of the minimum operating voltage VDD (Vmin) of the cell, 2) reducing bitline (BL)-active power, and 3) achieving low-power bus architecture. To meet the requirements, a static boosted-power-supply 5T cell, combined with boosted-WL and mid-point-sensing, and an open-BL multi-divided-array are proposed and evaluated. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5 V.To further speed up the write operation, a selectively-boosted-power-supply 5T-cell 4-kb array is proposed and evaluated by simulation, showing that the 4-kb array operates at 350-ps cycle with x6 faster cycle time and x13 lower power than the 6T-cell array, while maintaining a small leakage current. We find out that the mid-point-sensing with half-VDD BL-precharging is more stable during read than the conventional full-VDD precharging. Furthermore, to achieve a 0.5-V low-power high-speed robust bus, a dynamic bus architecture with a dummy bus, which consists of a dynamic driver and a dynamic receiver, is proposed. In particular, the dynamic driver enables high speed even at 0.5 V with increased gate-over-drive by changing the power lines from VDD/2 in the standby mode to VDD in the active mode. It further speeds up with the help of the dummy bus that generates a pulse to track the bus-voltage detecting point for reducing the bus swing. Then, a 0.5-V 28-nm-FD-SOI 32-bit bus architecture using the proposal is evaluated by simulation. It turns out that the architecture has a potential to operate a 1-pF bus at about 50-mV swing, 1.2 GHz, and a standby current of 1.1 µA, with x3-5 faster and more than two-order lower standby current than the conventional static architecture. Based on the results, further challenges to 0.5-V and sub-0.5-V SRAMs are described
Bester, Jacques. "Ballistic and dynamic mechanical characterisation of 5t prototype cast of a new locally developed armour steel alloy." Thesis, University of Pretoria, 2017. http://hdl.handle.net/2263/64044.
Full textThesis (MEng)--University of Pretoria, 2017.
Materials Science and Metallurgical Engineering
MEng
Unrestricted
Wang, Deng-Shian, and 王登賢. "Design and Implementation of Leakage Compensation Circuit for 5T SRAM." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/48vp43.
Full text國立中山大學
電機工程學系研究所
106
To reduce the SRAM area, a 5T single-ended SRAM cell has been proposed by our laboratory before. This dissertation presents two compensation designs for the 5T single-ended SRAM to reduce the power consumption of consumer electronics, e.g., smartphones. The first compensation design is a Slew Rate Compensation Circuit to fasten the slew rate of output signals. This compensation circuit consists of a Leakage Current Sensor and a Current Compensation Circuit. When the leakage of the SRAM cell is too high, the Current Compensation Circuit will be enabled by the Leakage Current Sensor to elevate the slew rate of the output on the bitline. This makes it possible to speed up the subsequent digital circuitry into a stable state, thereby reducing the associative active power.The SRAM using the proposed design was implemented using TSMC 40 nm CMOS logic technology. At the system voltage of 0.6 V, the proposed compensation design reduced the average power dissipation by 27.86%, and read delay by 54.88%, with only 3.64% area overhead. The second compensation design is to add a circuit in the SRAM cell to boost the gate voltage of the access transistor, thereby allowing an increase in the slew rate of the output, resulting in faster read and write operations. The SRAM using this gate drive boost circuit was implemented using TSMC 28 nm CMOS logic low power technology. When operating at a system voltage of 0.8 V, the proposed compensation scheme was demonstrated to reduce power dissipation by 17.2% and attain a 46.5% improvement in the output slew rate with only 6.6% area overhead. Finally, two compensation circuits are implemented using 40 nm and 28 nm logic processes to justify their performance, respectively. According to the Figure-of-Merit (FOM), the SRAMs using the proposed compensation designs have been proved are the state of art to date of the 5T single-ended SRAMs.
Chen, Sih-Yu, and 陳思瑜. "Single-ended Disturb-free 5T Load-less 4Kb SRAM with Leakage Current Sensor and Compensation Circuit." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/34839895392177144851.
Full text國立中山大學
電機工程學系研究所
101
This thesis consists of two topics, including a single-ended disturb-free 5T load-less 4Kb SRAM, and the leakage current sensor and compensation circuit mainly designed for memories, e.g., the mentioned single-ended disturb-free 5T load-less SRAM. The first topic presents a single-ended disturb-free 5T load-less 4Kb SRAM. The single-ended load-less SRAM cell consist of 5 transistors, where a write assistant loop and an isolated wordline-controlled transistor (WLC) are integrated therewith. The proposed cell is proved to attain the smallest area and disturb-free during the memory access. A shared bitline inverter is included to boost the read access speed at the minimal expense of area cost. Furthermore, a build-in self-test (BIST) circuit is included in the memory for testable R/W access. Based on the on-silicon measurements, the proposed 5T 4Kb SRAM shows superior performance in terms of power per access after normalization of the technology parameters. The second topic discloses a leakage current sensor and compensation circuit, consisting of a SRAM cell model, a reference voltage circuit, a comparator and the compensation circuit. The circuit is implemented in the mentioned single-ended disturb-free 5T load-less 1Kb SRAM. When the leakage current seriously endangers the state of the data bit, the sensor will notify a warning message to the compensation circuit and wake it up to refresh the corresponding bit. This circuit is proven to reduce 27.86% of the power consumption and boost 36.68 % of the speed during read access based on all-PVT-corner post-layout simulations results.
Tang, Kuei-Hua, and 湯貴華. "A Sub-ns-Access Sub-mW/GHz 28nm 0.45V 32Kb 5T SRAM Implementation and In Memory Computing Architecture." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/86b82b.
Full textSu, Yu-hsun, and 蘇鈺勛. "Low Power Cross-Domain High-Voltage Data Transmitters for Battery Management Systems and A 5T SRAM with Readout Slew-Rate Compensation." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/43cea2.
Full text國立中山大學
電機工程學系研究所
103
This thesis consists of two research topics, i.e., a high-voltage data transmitter for Battery Management Systems (BMS) and an SRAM with readout slew-rate compensation. The first topic demonstrates a low power cross-domain high-voltage transmitter for BMS. The design is aimed at applications to a 13-cell string in E-scooters''s BMS. The voltage range of the battery string is from 36.4 V to 54.6 V. The individual battery information is expected to be transmitted to the low voltage side where the BMS will carry out the management and analysis. To resolve the voltage level unmatching issue in digital data between a high voltage domain and a low voltage domain, a novel circuit design consisting of high to low transmitters and low to high transmitters is proposed. The advantages of the proposed transmitters are low power dissipation, small area, and no need of any isolator. Measurement results on silicon using TSMC 0.25 μm CMOS High Voltage Mixed Signal General Purpose IIA based BCD process justify that the power dissipation is 0.425 mW/Mbps, and the propagation delay is 1.9 us. A 5T SRAM with readout voltage slew-rate compensation is proposed in the second part. When the supply voltage is low, an adaptive voltage detector will switch on the word-line boosting circuit to compensate the readout for the single-ended disturb-free 5T load-less SRAM. Post-layout simulations based on implementation using TSMC 28 nm CMOS LOGIC Low Power ELK Cu 1P10M process demonstrate that the readout slew-rate is enhanced by 27.077%, and the average power dissipation is reduced by 13.694%.
He, Chen-Yu, and 何宸宇. "A Sub-ns-Access with Sub-mW/GHz 32Kb 5T SRAM Implementation and A Multi-Bit Buffer Design of ADC Input for In-SRAM Computing Architecture." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/kgce86.
Full text國立交通大學
電子研究所
108
This thesis has two portions, one is low power and high speed SRAM design. In this design, we propose a new 5T SRAM cells with multiple power supply voltages pulsed. Besides, we apply compact array architecture and open-BL to have smaller core area as compared to memory compiler. In idle, read or write mode, using assistant circuits and adaptive supply voltages of cells to optimize speed, power and reliability, respectively. Moreover, the design of tracking circuit is to ensure control correctness within PVT variation. In 28nm CMOS technology, the measurement results show the correct function. After the enhanced key modules design, the simulation results show the performance of sub-ns access with sub-mW/GHz. The second portion of this thesis is designs of multi-bit buffer in In-Memory Computing. Because SRAM cells can just store single bit data, we arrange the storing order of data and have multi-bit buffers to propose the reconfigurable architecture. This architecture can provide optional bit number of input, weigh and output. In buffer designs, we apply Two stage OTA to form a closed loop unity-gain buffer. In 28nm CMOS technology, simulation results show the function correctness within PVT variation.
Books on the topic "5T"
Bacon, Roy H. Triumph Touring Twins, 3T-5T-6T-3TA-5TA, 1938-1966. Niton Publishing, 1990.
Find full textFerrari, Héctor Ricardo, Laura Cecilia Lázaro, and Carolina Emilse Tarzia. Las cuatro preguntas de Tinbergen. Editorial de la Universidad Nacional de La Plata (EDULP), 2018. http://dx.doi.org/10.35537/10915/73678.
Full textWoolridge, Harry. Triumph Speed Twin & Thunderbird Bible: All 5T 498cc & 6T 649cc Models 1938 To 1966. Veloce Publishing Limited, 2016.
Find full textBook chapters on the topic "5T"
Shoaff, P. V., J. Schwartz, S. W. Van Sciver, and H. W. Weijers. "HTS Coil and Joint Development for a 5T NMR Insert Coil." In A Cryogenic Engineering Conference Publication, 413–18. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4613-0373-2_53.
Full textShibutani, K., S. Itoh, O. Ozaki, T. Takagi, T. Miyazaki, R. Hirose, S. Hayashi, et al. "Development of Two Types of Cryogen Free Superconducting Magnets (5T-ϕ300min and 10T-ϕ100mm)." In Advances in Cryogenic Engineering, 299–305. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-9047-4_35.
Full textTiwari, Nidhi, Varun Sankath, Akhilesh Upadhyay, Mukesh Yadav, Ruby Jain, Pallavi Pahadiya, Madhavi Bhanwsar, and Shivangini Mouraya. "Modelling and Design of 5T, 6T and 7T SRAM Cell Using Deep Submicron CMOS Technology." In Algorithms for Intelligent Systems, 305–9. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-6707-0_28.
Full textSnigdha Chandrika, V., and M. Maria Dominic Savio. "Designing 5T Embedded DRAM Cell for Ultra-Low-Power Low-Voltage Applications Based on Schmitt Trigger." In Lecture Notes in Electrical Engineering, 99–108. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7251-2_11.
Full textFurino, S. C., and S. A. Vanstone. "Pairwise Balanced Designs with Block Sizes 5t + 1." In graphs, matrices, and designs, 147–70. Routledge, 2017. http://dx.doi.org/10.1201/9780203719916-11.
Full textConference papers on the topic "5T"
Samson, Mamatha, and Satyam Mandavalli. "Adiabatic 5T SRAM." In 2011 International Symposium on Electronic System Design (ISED). IEEE, 2011. http://dx.doi.org/10.1109/ised.2011.57.
Full textRollini, R., Jenyfal Sampson, and P. Sivakumar. "Comparison on 6T, 5T and 4T SRAM cell using 22nm technology." In 2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE). IEEE, 2017. http://dx.doi.org/10.1109/iceice.2017.8191924.
Full textHadi Saputro, Prabowo, and Mr Siswantoyo. "Developing a Model of Character Education of 5t-Based Pencak Silat." In Proceedings of the 2nd Yogyakarta International Seminar on Health, Physical Education, and Sport Science (YISHPESS 2018) and 1st Conference on Interdisciplinary Approach in Sports (CoIS 2018). Paris, France: Atlantis Press, 2018. http://dx.doi.org/10.2991/yishpess-cois-18.2018.47.
Full textSasaki, A. "Optimization of Peltier Current Leads for 5T Cryogen-Free Superconducting Magnets." In ADVANCES IN CRYOGENIC ENGINEERING. AIP, 2006. http://dx.doi.org/10.1063/1.2192375.
Full textKumar, Seelam Vasavi Sai Viswanada Prabhu Deva, and Shyam Akashe. "Designed & Comparison of Reliability Analysis in 6T & 5T SRAM Cell." In 2018 4th International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2018. http://dx.doi.org/10.1109/icdcsyst.2018.8605164.
Full textYadav, Jitendra Kumar, Pallavi Das, Abhinav Jain, and Anuj Grover. "Area compact 5T portless SRAM cell for high density cache in 65nm CMOS." In 2015 19th International Symposium on VLSI Design and Test (VDAT). IEEE, 2015. http://dx.doi.org/10.1109/isvdat.2015.7208095.
Full textJeon, Dongsuk, Qing Dong, Yejoong Kim, Xiaolong Wang, Shuai Chen, Hao Yu, David Blaauw, and Dennis Sylvester. "A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory." In 2015 Symposium on VLSI Circuits. IEEE, 2015. http://dx.doi.org/10.1109/vlsic.2015.7231322.
Full textSih-Yu Chen and Chua-Chin Wang. "Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process." In 2012 IEEE International Conference on IC Design & Technology (ICICDT). IEEE, 2012. http://dx.doi.org/10.1109/icicdt.2012.6232848.
Full textRodricks, Brian, Boyd Fowler, John Lowes, and Paul Vu. "Radiation damage studies on a 5T sCMOS image sensor with integrated readout electronics." In SPIE NanoScience + Engineering, edited by Eustace L. Dereniak, John P. Hartke, Paul D. LeVan, Ashok K. Sood, Randolph E. Longshore, and Manijeh Razeghi. SPIE, 2010. http://dx.doi.org/10.1117/12.862081.
Full textRodricks, Brian, Boyd Fowler, John Lowes, and Paul Vu. "Radiation damage studies on a 5T sCMOS image sensor with integrated readout electronics." In SPIE Optical Engineering + Applications, edited by Arnold Burger, Larry A. Franks, and Ralph B. James. SPIE, 2010. http://dx.doi.org/10.1117/12.862082.
Full text