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Relevant bibliographies by topics / 8-bit multiplier

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Academic literature on the topic '8-bit multiplier'

Author: Grafiati

Published: 5 June 2025

Last updated: 16 July 2025

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Journal articles on the topic "8-bit multiplier"

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Sadaf, Sumaya, and V. Radha Krishna. "Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 667–78. http://dx.doi.org/10.22214/ijraset.2023.56018.

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Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

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Senathipathi, Mr N., R. Rasiha, R. Sadhurya, and S. Sangeetha. "Design of Power Efficient Posit Multiplier using Compressor Based Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (2023): 2768–73. http://dx.doi.org/10.22214/ijraset.2023.51597.

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Abstract: Posit number system has been used in many applications, especially the deep learning. Because of how well its nonuniform number distribution aligns with deep learning's data distribution, deep learning's training process can be sped up. The hardware multiplier is typically built with the widest mantissa bit-width available due to the flexibility of posit numbers' bitwidth. Such multiplier designs consume a lot of power since the mantissa bit-width is not necessarily the maximum value. This is especially true when the mantissa bit-width is tiny. The mantissa multiplier is still built to have the widest bit-width feasible, but it is broken into numerous smaller multipliers. At run-time, just the necessary tiny multipliers are turned on. The regime bitwidth, which can be used to determine the mantissa bit-width, controls those smaller multipliers. This design technique is applied to 8-bit, 16-bit, and 32-bit posit formats.

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Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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Pinto, Rohan, and Kumara Shama. "Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950019. http://dx.doi.org/10.1142/s0218126619500191.

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Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

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Berezin, N. M., I. E. Chernetskaya, V. S. Panishchev, and A. M. Shabarov. "Development of a device for multiplying numbers by means of FPGA." Journal of Physics: Conference Series 2142, no. 1 (2021): 012001. http://dx.doi.org/10.1088/1742-6596/2142/1/012001.

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Abstract The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.

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Raj Narain, B., and Dr T. Sasilatha. "Implementation of reconfigurable galois field multipliers over2m using primitive polynomials." International Journal of Engineering & Technology 7, no. 2.12 (2018): 386. http://dx.doi.org/10.14419/ijet.v7i2.12.11356.

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The Galois field multiplier finds extensive use in cryptographic solutions and applications. The Galois field multiplier can be implemented as fixed bitwise or reconfigurable. For fixed length, the data is restricted to the fixed length. But in reconfigurable GF multipliers, the bit length of the multiplier is flexible and is independent of hardware architecture. This paper proposes a method to implement a reconfigurable GF multiplier for various bit values from 8 to 128 bits. This paper compares the area complexity of various bit size in Xilinx Spartan 3E family FPGA and estimates the resources required for the implementation.

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Bhusare, Saroja S., and V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.

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In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an [Formula: see text]-bit product with two [Formula: see text]-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that the radix-8 direct truncated multiplier reduces the maximum absolute error by 33%, the average error by 22% and the mean square error by 39% for a 12-bit multiplier compared with the radix-4 direct truncated multiplier. Results also demonstrate that, with the probabilistic estimation technique applied to the fixed-width radix-8 Booth multiplier, there is a reduction of 25% in the maximum absolute error, 13.4% reduction in the average error, and 25.13% reduction in the mean square error have been realized compared with the existing fixed-width radix-4 Booth multiplier with probabilistic estimation technique. Standard EDA design tools are used for simulations.

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Zhang, Yu Long, Guo Chu Shou, Yi Hong Hu, and Zhi Gang Guo. "Low Complexity GF(2^m) Multiplier Based on Iterative Karatsuba Algorithm." Advanced Materials Research 546-547 (July 2012): 1409–14. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.1409.

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The complexity is one important index for Galois Field multiplier. This paper presents one low complexity GF(2m) multiplier based on iterative Karatsuba algorithm. The multiplication is replaced iteratively by three ones of half-length operands which are performed in parallel. The operands are divided into different width such as 64-bit, 32-bit, 16-bit and so on. For the 2m*2mmultiplier, we take 128 bit-widthGF(2128) multipliers as an example. We implement them on FPGA and count the number of the used LUTs and the used registers. Through analyzing the statistic, we find that, when the width of the two multiplication operands is divided to 8 bit, the multiplier consumes the least resources. Compared with the FPGA implementation of the other previous multiplier, this optimum multiplier can save 50% resources in LUTs and the registers.

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Chandrasekharan, Raji, and Sarappadi Narasimha Prasad. "Fault tolerant design for 8-bit Dadda multiplier for neural network applications." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 3 (2025): 2697. https://doi.org/10.11591/ijece.v15i3.pp2697-2705.

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As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient. Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient. However, traditional fault free designs consume excessive power and require substantial silicon real estate. Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications. Therefore, there is need to design a power efficient and fault free Dadda multiplier that can address these challenges without significantly increasing power consumption or hardware complexity. In this paper a solution involving a fault tolerant Dadda multiplier optimized for neural network applications is proposed. Because of its speed and efficiency when compared to other multipliers Dadda multiplier is used as the base architecture which is designed using carry select adder (CSA) in conjunction with binary to excess one converter to reduce power and complexity. To enhance fault tolerance, self-repairing full adder is used to implement the CSA. This allows the system to detect and correct errors, ensuring robust operation in the presence of transient faults. This combination achieves a power efficient, fault tolerant multiplier with a power consumption of 52.3 mW, reflecting a 3% reduction in power compared to existing designs.

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Madaka, Venkata Subbaiah, and Umamaheswara Reddy Galiveeti. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1367–78. https://doi.org/10.11591/ijece.v13i2.pp1367-1378.

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In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.

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Dissertations / Theses on the topic "8-bit multiplier"

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Le, Chin Aik. "An 8-bit inner product multiplier by parallel pipeline algorithm." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182863777.

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Chi, Hsing-Yu, and 吉星宇. "A 8-bit Domino-style with Multiple Comparator Successive Approximation Register Analog to Digital Converter." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/yw9ang.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>107<br>This thesis adopt a 90-nm TSMC process to complete a single-channel Domino-Successive Approximation Register Analog to Digital Converter progressive digital analog converter. In the case of medium and high speed, in order to make the ADC have a certain fault tolerance, we added a redundant bit, so the whole conversion step is used to achieve the effect of eight bits. In order to improve the overall conversion speed, the first comparison is performed without switching any logic switches after sampling. This method can speed up the overall circuit speed by reducing the capacitance by half. In addition, Loop-unrolled technology is used to convert multiple comparators. The action of the comparator is like the action of a domino. One level pushes one level, which can greatly reduce the reset time of the comparator. The comparator uses a dynamic comparator from the Two Stage to achieve lower power consumption. Because multiple comparators are used, the output of the comparison can be stored in the latch side of the comparator, so the number of the register can be greatly reduced compared to the single or more than two comparators. It can effectively reduce a part of core area. The supply voltage is 1.2V, Vp-p is 1V, the maximum and minimum values of DNL and INL under the static performance are (0.244, -0.254), (0.545, -0.029); the input signal at Nyquist is Fin=173.63281250MHz, Sampling frequency Fs=350MHz Dynamic performance: SNDR is 48.303dB

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Tseng, Jiunn-Chin, and 曾俊欽. "A 8-bit 280MS/s Multiple Sampling Single Conversion CMOS A/D Converter for IQ Demodulation." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/58317040590469174874.

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碩士<br>國立交通大學<br>電子研究所<br>84<br>In this thesis, a CMOS 70 MHz IF Quadrature demodulator is presented. This IFdemodulator uses the sample-and-hold ckt operated at 4 times IF frequency,280MHz The IF modulated signal is sampled successively to different capacitors in samplingcapacitor array of I and Q channel(The capacitor ratios in sampling capacitor arrayrepresent the coefficient of IQ channel filter).The filter function is achievedby analog charge addition in sampling capacitors.The resultant discrete-time basebandI and Q signals are digitalized by 8-bit successive approximation ADC.The dataoutput rate in each channel is 1.09MS/ s. This IF quadrature demodulator which includes mixer,lowpass filters and successiveapproximation AD converter and utilizes the multiple sampling,single conversionarchitecture is fabricated in UMC 0.8 DPDM CMOS process.The whole chip area is5000um x 4000um,and the average power dissipation is about 100mW.

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Books on the topic "8-bit multiplier"

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Wunderlich, Paul. Paul Wunderlich: Graphik und Multiples, 1948-1987 : Katalog der Ausstellung zum 60. Geburtstag am 10. März 1987, Band 2 : Schleswig-Holsteinisches Landesmuseum, Schleswig, Schloss Gottorf, 8. November 1987 bis 31.Januar 1988. Schleswig-Holsteinisches Landesmuseum, 1987.

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Kotb, Dr. Go Big or Go Home: Penile Enlargements Exercises - The uncensored Ultimate Guide of 8 Wауѕ Tо Gіvе Your Wоmаn Multiple Orgаѕms. Independently published, 2019.

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Book chapters on the topic "8-bit multiplier"

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Xiong, Xingguo, and Muzi Lin. "Low Power 8-Bit Baugh–Wooley Multiplier Based on Wallace Tree Architecture." In Lecture Notes in Electrical Engineering. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-3558-7_73.

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Sakthimohan, M., and J. Deny. "An Efficient Design of 8 * 8 Wallace Tree Multiplier Using 2 and 3-Bit Adders." In Lecture Notes in Networks and Systems. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4355-9_3.

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Pradhananga, Umatri, Xingguo Xiong, and Linfeng Zhang. "PSPICE Implementation of Block-Wise Shut-Down Technique for 8 × 8 Bit Low Power Pipelined Booth Multiplier." In Lecture Notes in Electrical Engineering. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-06764-3_40.

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Panigrahi, Amrit Kumar, Sakshi, Nishant Kumar Pradhan, and Vishakha Singh. "Timing and Power Optimisation of High Speed 8-Bit Multiplier Using BASYS-3 FPGA Board." In Learning and Analytics in Intelligent Systems. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30271-9_9.

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Pasuluri, Bindu Swetha, and V. J. K. Kishor Sonti. "Performance Analysis of 8-Bit Vedic Multipliers Using HDL Programming." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1420-3_114.

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Wang, Miao, Zhihong Huang, Gang Cai, and Junxuan Wang. "A FPGA Embedded DSP Supporting Parallel Multiple Low Bit-Width Multiply-Accumulate Operations." In Advances in Transdisciplinary Engineering. IOS Press, 2023. http://dx.doi.org/10.3233/atde230112.

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With the continuous development of big data and hardware computing platforms, deep learning has been substantially applied in many intelligent scenarios. Recent studies have shown that using low bit-width networks in deep learning inference can effectively improve the overall performance of accelerator by reducing the computational ability requirements while maintaining the recognition accuracy of accelerator. Among them, low bit-width convolutional operations such as 8bit and 4bit are widely used in applications such as graph recognition. FPGA chip is the core key device of digital system, due to the excellent reconfigurability of FPGA, it has become one of the mainstream platforms in the field of deep learning accelerator. The current mainstream FPGAs are composed of higher bit-width multipliers due to the need to adapt to different computing application requirements, and the DSP module resources are used to perform low bit-width convolutional operations, which only occupy part of the multiplier bit-width, thus wasting a large amount of hardware on chip resources. Therefore, this paper proposes a DSP architecture of using large bit-width multipliers to compute low bit-width multiplications in parallel, so that the new DSP can realize double 8bit and 4bit multiply-accumulate operations without adding multipliers, and can support any combination of signed and unsigned data operations. The design is based on the commercial Stratix IV DSP architecture, and the overall circuit is designed with SMIC 14nm standard CMOS process. The experimental results show that when calculating the same number of 4-bit and 8-bit multiply-accumulate operations, the resource consumption area of the improved DSP is reduced by 43.5% and the speed is increased by 48%.

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., Dhanabalan, and Tamil Selvi. "Implementation of High Speed 8-bit Multiplier in FPGA with Lesser Adder Elements." In Novel Perspectives of Engineering Research Vol. 7. Book Publisher International (a part of SCIENCEDOMAIN International), 2022. http://dx.doi.org/10.9734/bpi/nper/v7/1763b.

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Uppala, Anitha Jyothi, Nikshipta Koya, Sai Neha Penmetsa, Srivinni Gutha, E. Bharat Babu, and Santhosh Kumar Veeramalla. "Power-Efficient Stochastic Number Generator Design and Implementation for Encryption." In Advances in Civil and Industrial Engineering. IGI Global, 2023. http://dx.doi.org/10.4018/979-8-3693-0044-2.ch020.

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Stochastic computing utilizes random bit streams to encode continuous data efficiently. One important aspect is the stochastic number generator (SNG) that encodes numbers into random binary bit streams. This work presents power-efficient 4-bit and 8-bit SNGs by using a modified Non-linear Feedback Shift Register (NLFSR) as the random number source and a Weighted Binary Generator (WBG) as the probability conversion circuit. A bipartite approach is employed to reduce power and delay consumption in the SNGs. Additionally, the concept of sharing a single random number source with multiple probability conversion circuits is explored to achieve further power savings. This project offers enhanced power efficiency in SNGs, contributing to advancements in stochastic computing and power circuit designs. The main application of this project is encryption, as random number sequences are required for various stages of encryption protocols.

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Schumer, Peter D. "A Very Brief Introduction to Matrices." In Fractions. Oxford University PressOxford, 2024. http://dx.doi.org/10.1093/9780198916567.003.0007.

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Abstract As a useful and somewhat less-taxing interlude, matrices and basic matrix arithmetic are introduced. Matrices can be multiplied by scalars and matrices of the same size can be added and subtracted. Matrix multiplication is a bit trickier. The product of matrices AB can be computed if the number of columns of A equals the number of rows of B. A key concept is that matrix multiplication is not commutative. Matrices are an important topic generally, being indispensable for the deeper study of mathematics, statistics, computer science, and all social and natural sciences. As preparation for Chapter 8, 2 × 2 matrices are studied along with their determinant and inverse.

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"Brainstorming Multiple Valid Answers/Responses." In The Big Book of Literacy Tasks, Grades K–8: 75 Balanced Literacy Activities Students Do (Not You!). Corwin, 2018. http://dx.doi.org/10.4135/9781071873052.n60.

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Conference papers on the topic "8-bit multiplier"

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Karthikeya, Dhulipala, P. R. Teja Sree, and Guru Prasad Mishra. "8-Bit Approximate Multiplier using Approximate Full Adder." In 2025 Devices for Integrated Circuit (DevIC). IEEE, 2025. https://doi.org/10.1109/devic63749.2025.11012648.

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T, Revanna J., Gurudatt B. M, G. R. Deepakkumar, Vedashree B. S, and Shylashree N. "Static Timing Analysis of Modified 8 Bit Pipelined Multiplier with Carry Lookahead Adder Approach." In 2024 8th International Conference on Computational System and Information Technology for Sustainable Solutions (CSITSS). IEEE, 2024. https://doi.org/10.1109/csitss64042.2024.10816828.

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Mishra, Padum Kant, Ekta Gupta, and Aniket Kumar. "Comparative Research on Power and Junction Temperature in 2, 4, 8 bit Multiplier Using Nikhlam Sutra." In 2024 International Conference on Recent Advances in Science and Engineering Technology (ICRASET). IEEE, 2024. https://doi.org/10.1109/icraset63057.2024.10895106.

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Swetha, Siliveri, and Tokala Shreya. "Design and Analysis of 4-bit and 8-bit Vedic Multipliers Using Variable Bit CSLA." In 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. https://doi.org/10.1109/dicct64131.2025.10986739.

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Muttu, Yeshudas, Lokesh Kumar Bramhane, Amol D. Rahulkar, and T. Veerakumar. "Implementation and Performance Analysis of 8-bit Digital Parallel Array Multipliers." In 2024 International Conference on Intelligent Computing and Sustainable Innovations in Technology (IC-SIT). IEEE, 2024. https://doi.org/10.1109/ic-sit63503.2024.10862414.

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Meng, Xiansong, Kwangwoong Kim, Po Dong, Deming Kong, and Hao Hu. "Digital optical phase and amplitude matrix multiplication processor for neural networks." In CLEO: Science and Innovations. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_si.2024.sth5c.8.

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We propose a high-precision digital optical matrix multiplier utilizing phase and amplitude for neural networks. Results show error-free performance with 16-bit precision in high-definition image processing and no accuracy loss in handwritten digit recognition task.

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Saha, A., D. Pal, Mahesh Chandra, and M. K. Goswami. "Novel High Speed MCML 8-Bit by 8-Bit Multiplier." In 2011 International Conference on Devices and Communications (ICDeCom). IEEE, 2011. http://dx.doi.org/10.1109/icdecom.2011.5738526.

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Kamdi, Rahul, Prasheel Thakre, Aniket Pathade, Sandeep Kumar Tiwari, and Kamlesh Kalbande. "4 Bit and 8 Bit Convolution Using Vedic Multiplier." In 2022 International Conference on Emerging Trends in Engineering and Medical Sciences (ICETEMS). IEEE, 2022. http://dx.doi.org/10.1109/icetems56252.2022.10093621.

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Lakshmi, G. Sree, DrKaleem Fatima, and B. K. Madhavi. "Compressor based 8×8 BIT vedic multiplier using reversible logic." In 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2016. http://dx.doi.org/10.1109/icdcsyst.2016.7570588.

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Garg, Sasha, Swati Garg, and Vidhi Sachdeva. "Comparative analysis of 8 X 8 Bit Vedic and Booth Multiplier." In 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2014. http://dx.doi.org/10.1109/icacci.2014.6968224.

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Reports on the topic "8-bit multiplier"

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programme, CLARISSA. Children Enter the Adult Entertainment Sector and Face Labour Exploitation and Sexual Abuse. Institute of Development Studies, 2024. http://dx.doi.org/10.19088/clarissa.2024.032.

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This is a report of CLARISSA Nepal Action Research Group 8, which is located in a busy commercial, historical and tourist destination in the centre of Kathmandu Valley. The area is famous for its multiple big-scale shopping complexes and wholesale markets and for being a hotspot for street vendors and small-scale Adult Entertainment Sector (AES) venues. As many children and young people work in the AES in this area, the location was selected as one of the most important working locations for CLARISSA Action Research. The theme of this group was 'Children enter the AES through friends, relatives, and unknown persons and face labour exploitation and sexual abuse'.

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