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Journal articles on the topic '8 stage voltage multiplier'

Author: Grafiati

Published: 3 June 2025

Last updated: 20 July 2025

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Udechukwu, Felix Chimezie, Mamilus Ahaneku, Vincent Chukwudi Chijindu, Dumtoochukwu Oyeka, Douglas Amobi Amoke, and Chiagozie Mbah. "Comparative Analysis of an 8 – Stage Cockcroft Walton Voltage Multiplier and A Dickson Voltage Multiplier in The Context of Radio Frequency Energy Harvesting." Revista de Gestão Social e Ambiental 18, no. 10 (2024): e08786. http://dx.doi.org/10.24857/rgsa.v18n10-241.

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Purpose: This study seeks to enhance voltage multipliers for Radio Frequency (RF) energy harvesting, with an emphasis on increasing the efficiency of harvested energy. This improvement is vital for sustainable energy applications and reducing environmental pollution caused by fossil fuels. Theoretical reference: RF energy harvesting technology is gaining recognition as a viable sustainable method for capturing ambient energy, with earlier research primarily focused on antenna and circuit design. Nonetheless, the effectiveness of energy harvesting is still constrained by inadequate power output. This study expands on prior research by directly comparing two commonly utilized voltage multipliers, the Cockcroft Walton and Dickson multipliers, in the context of RF energy harvesting. Method: The Cockcroft Walton and Dickson voltage multipliers were optimally designed using Multisim and their performance was analysed using MATLAB. The comparison was conducted at an input voltage of 1V within two frequency ranges: 85 MHz – 110 MHz (FM band) and 1.8 GHz – 3.0 GHz (4G band). Output voltages for both multipliers were recorded and compared across these frequency bands. Results and Conclusion: At an input voltage of 1V within the FM band (85 MHz – 110 MHz), the Dickson voltage multiplier outperformed the Cockcroft Walton multiplier, delivering an output voltage of 11.1V compared to 6.6V. However, in the 4G band (1.8 GHz – 3.0 GHz), the Cockcroft Walton multiplier was more effective, providing a maximum output voltage of 5.2V against Dickson's 4.1V. The study concludes that the Dickson multiplier is more suitable for harvesting RF energy from the FM band, while the Cockcroft Walton multiplier is better for 4G band energy harvesting. Implications of research: The findings suggest that different RF energy harvesting applications may benefit from distinct voltage multipliers, depending on the frequency band in question. This could guide the design of more efficient RF energy harvesting circuits in future technologies aimed at sustainable energy solutions. Originality/value: This study offers a direct comparison of two voltage multipliers under different RF frequency conditions, providing valuable insights into optimizing energy harvesting technologies for green energy applications. The results help advance the understanding of efficient circuit design for specific RF frequency bands, contributing to the development of more effective energy harvesting systems.

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Udechukwu, Felix Chimezie, Mamilus Ahaneku, Vincent Chukwudi Chijindu, Dumtoochukwu Oyeka, Chineke-Ogbuka Ifeanyi Maryrose, and Douglas Amobi Amoke. "Hybridization of Cockcroft-Walton and Dickson Voltage Multipliers for Maximum Output Through Effective Frequency Dedication in Harvesting Radio Frequency Energy." Revista de Gestão Social e Ambiental 18, no. 11 (2024): e09750. http://dx.doi.org/10.24857/rgsa.v18n11-102.

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Objective: This study investigates solutions to the challenges of limited RF energy harvesting by designing a hybridized voltage multiplier system aimed at optimizing output across a wide frequency range. Theoretical Framework: The research centers on the principles and comparative efficiencies of the Cockcroft-Walton and Dickson voltage multipliers, known for their applications in RF energy harvesting. These multipliers’ performance was analyzed theoretically to guide a hybrid design that could adaptively respond to input frequency variations. Method: Voltage multipliers were designed and simulated in Multisim, with further analysis in MATLAB. Both the Cockcroft-Walton and Dickson voltage multipliers were subjected to a constant input of 1V across frequencies from 50 Hz to 5 GHz to assess their respective efficiencies. Subsequently, a hybrid voltage multiplier system was developed, combining an 8-stage Cockcroft-Walton and an 8-stage Dickson multiplier. A fast Fourier transform (FFT) frequency-selective algorithm, implemented in MATLAB, dynamically directed input voltages to the optimal multiplier based on frequency. Results and Discussion: Results showed that the Dickson multiplier excelled in the lower frequency range (50 Hz to 1 MHz), achieving a maximum output of 14.763V at 5 kHz and 10 kHz. In contrast, the Cockcroft-Walton multiplier was more effective in the higher frequency range (1 MHz to 5 GHz), reaching a peak output of 6.671V at 5 GHz. The hybrid system demonstrated efficient, frequency-dependent voltage multiplication and aligned well with anticipated performance metrics, suggesting an improvement in RF energy harvesting across the tested frequency range. Research Implications: This work contributes to the field of RF energy harvesting by introducing a frequency-adaptive system that enhances voltage output through targeted frequency routing. The results underscore the potential for hybrid designs to overcome limitations associated with individual voltage multipliers, presenting a versatile approach to harvesting RF energy effectively across broad frequency spectra. Originality/Value: By implementing a hybrid approach with a frequency-selective algorithm, this study offers an innovative solution for frequency-dependent RF energy harvesting. The findings provide a foundation for future research into adaptable energy harvesting systems that optimize voltage output across diverse frequencies, with practical implications for RF-powered devices and wireless energy transfer applications.

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Mr., A. Raghavendra Prasad Mr.K.Rajasekhara Reddy &. Mr.M.Siva sankar. "HIGH VOLTAGE DC UP TO 2 KV FROM AC BY USING CAPACITORS AND DIODES IN LADDER NETWORK." INTERNATIONAL JOURNAL OF RESEARCH SCIENCE & MANAGEMENT 5, no. 6 (2018): 73–85. https://doi.org/10.5281/zenodo.1291902.

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The aim of this project is designed to develop a high voltage DC around 2KV from a supply source of 230V AC using the capacitors and diodes in a ladder network based on voltage multiplier concept. The method for stepping up the voltage is commonly done by a step-up transformer. The output of the secondary of the step up transformer increases the voltage and decreases the current. The other method for stepping up the voltage is a voltage multiplier but from AC to DC. Voltage multipliers are primarily used to develop high voltages where low current is required. This project describes the concept to develop high voltage DC (even till 10KV output and beyond) from a single phase AC. For safety reasons our project restricts the multiplication factor to 8 such that the output would be within 2KV.  This concept of generation is used in electronic appliances like the CRT’s, TV Picture tubes, oscilloscope and also used in industrial applications. The design of the circuit involves voltage multiplier, whose principle is to go on doubling the voltage for each stage. Thus, the output from an 8 stage voltage multiplier can generate up to 2KV. As this is not possible to be measured by a standard multimeter, a potential divider of 10:1 is used at the output such that 200V reading means 2KV. Due to low input impedance of the multimeter, the reading would actually be approximately 7 times the input AC voltage. Further the project can be enhanced to generate the high voltage DC up to the range of 30-50 KV by increasing the number of stages. It can then be used for required industrial and medical applications.

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RESHMA, V. P. "GENERATION OF HIGH VOLTAGE DC BY USING SINGLE PHASE AC SUPPLY A CASE STUDY." IJIERT - International Journal of Innovations in Engineering Research and Technology 3, no. 12 (2016): 51–55. https://doi.org/10.5281/zenodo.1462371.

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<strong>The main concept of the project here is to generate a high voltage DC from a single phase AC with the help of the capacitors and diodes connected in a ladder network. This concept is often used in electronic appliances like the CRTs,TV picture tube,and o scilloscope and also in industrial appliances. It is also possible to generate up to 10KV DC from this single phase supply,but owing to safety concerns and reasons,this system limits the generating voltage to a 2KV output by limiting the capacitor and diode multiplication factor to about 8.</strong> <strong>https://www.ijiert.org/paper-details?paper_id=140978</strong>

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Moghaddam, Majid, Mohammad Hossein Moaiyeri, Mohammad Eshghi, and Ali Jalali. "A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter." Journal of Circuits, Systems and Computers 24, no. 08 (2015): 1550124. http://dx.doi.org/10.1142/s0218126615501248.

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This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V DDL , V DDH ) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

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Palati, Madhu, and Prashanth Narayanappa Ananda. "Characterization of a compact low cost 6.5kV Cockcroft voltage multiplier." Bulletin of Electrical Engineering and Informatics 11, no. 4 (2022): 1789–97. http://dx.doi.org/10.11591/eei.v11i4.3809.

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Generation of high voltages is often necessary in Industrial, Medical, civilian and defense applications. One of the popular methods of generation of high voltage DC is using a Cockcroft voltage multiplier generator. Knowledge on characterization of the voltage multiplier circuit helps the designer to study the effect of various input parameters on output, saves lot of time and money. In this paper various methods of generation of high voltages, advantages and disadvantages of each method are discussed. Design of five stage voltage multiplier circuit, fabrication and characterization of the 6.5kV voltage multiplier generator are presented. Simulation was carried using PSPICE software under different load conditions. Effect on the output voltage, ripple voltage with different values of load, frequency was studied. Experiments were carried out on the proposed prototype model and validated by comparing the values obtained from experimentation with the simulation and theoretical values

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Madhu, Palati, and Narayanappa Ananda Prashanth. "Characterization of a compact low cost 6.5kV Cockcroft voltage multiplier." Bulletin of Electrical Engineering and Informatics 11, no. 4 (2022): 1789~1797. https://doi.org/10.11591/eei.v11i4.3809.

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Generation of high voltages is often necessary in industrial, medical, civilian and defense applications. One of the popular methods of generation of high voltage DC is using a Cockcroft voltage multiplier generator. Knowledge on characterization of the voltage multiplier circuit helps the designer to study the effect of various input parameters on output, saves lot of time and money. In this paper various methods of generation of high voltages, advantages and disadvantages of each method are discussed. Design of five stage voltage multiplier circuit, fabrication and characterization of the 6.5kV voltage multiplier generator are presented. Simulation was carried using PSPICE software under different load conditions. Effect on the output voltage, ripple voltage with different values of load, frequency was studied. Experiments were carried out on the proposed prototype model and validated by comparing the values obtained from experimentation with the simulation and theoretical values.

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Amudhavalli, Dhanaraj, Nalin Kant Mohanty, and Ashwin Kumar Sahoo. "Interleaved quadratic boost converter integrated with Dickson voltage multiplier with energy storage for high power photo voltaic applications." International Journal of Power Electronics and Drive Systems (IJPEDS) 12, no. 2 (2021): 957. http://dx.doi.org/10.11591/ijpeds.v12.i2.pp957-967.

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In this paper interleaved quadratic boost converter with Dickson voltage multiplier is proposed. Photovoltaic system is connected to high power load through the proposed converter. Structure of this high gain interleaved converter comprised of two stages: interleaved quadratic boost converter stage and Dickson voltage multiplier stage. Interleaved quadratic boost converter is a parallel combination of two quadratic boost converter. The interleaving increases frequency of converter that could be filtered using small capacitors, making input current smoother than the current of conventional quadratic boost converter. Thus, interleaved circuit minimizes current ripple present in input current, cascading of voltage multiplier cell increases the gain voltage ratio of converter making it suitable for high power, high voltage gain photo voltaic applications. Stress voltage of the switches and reverse recovery problems gets reduced, thereby reducing EMI problems. 300W prototype capable of increasing 24V input voltage to 400V output voltage is designed and results tested using MATLAB/Simulink software. Hardware prototype is also implemented to verify simulation results. Also, application of this converter in integrated energy storage is demonstrated.

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D., Amudhavalli, Kant Mohanty Nalin, and Kumar Sahoo Ashwin. "Interleaved quadratic boost converter integrated with Dickson voltage multiplier with energy storage for high power photo voltaic applications." International Journal of Power Electronics and Drive System (IJPEDS) 12, no. 2 (2021): 957–67. https://doi.org/10.11591/ijpeds.v12.i2.pp957-967.

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Wijono, Wijono, Zainul Abidin, Waru Djuriatno, Eka Maulana, and Nola Ribath. "Design of 4-stage Marx generator using gas discharge tube." Bulletin of Electrical Engineering and Informatics 10, no. 1 (2021): 55–61. http://dx.doi.org/10.11591/eei.v10i1.1949.

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In this paper, a Marx generator voltage multiplier as an impulse generator made of multi-stage resistors and capacitors to generate a high voltage is proposed. In order to generate a high voltage pulse, a number of capacitors are connected in parallel to charge up during on time and then in series to generate higher voltage during off period. In this research, a 6kV Marx generator voltage multiplier is designed using gas discharge tube (GDT) as an electronic switch to breakdown voltage. The Marx generator circuit is designed to charge the storage capacitor for high impulse voltage and current generator applications. According to IEC 61000-4-5 class 4 standards, the storage capacitor must be charged up to 4 kV. The results show that the proposed Marx generator can produce voltages up to 6.8 kV. However, the storage capacitor could be charged up to 1 kV, instead of 4 kV in the standard. That is because the output impulse voltage has narrow time period.

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Wijono, Abidin Zainul, Djuriatno Waru, Maulana Eka, and Ribath Nola. "Design of 4-stage Marx generator using gas discharge tube." Bulletin of Electrical Engineering and Informatics 10, no. 1 (2021): 55–61. https://doi.org/10.11591/eei.v10i1.1949.

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Wijono, Maulana Eka, Darmawan Putra Dony, and Djuriatno Waru. "Plasma generator: design of six stage cockcroft-walton voltage multiplier 12 kV for impulse voltage generation." TELKOMNIKA Telecommunication, Computing, Electronics and Control 17, no. 4 (2019): 1890–97. https://doi.org/10.12928/TELKOMNIKA.v17i4.11828.

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Cockcroft-Walton (CW) voltage multiplier is a voltage booster circuit with an array of series-connected only diodes and capacitors. In this research, voltage multiplier is designed to generate voltage up to 12 kV that the modified 6-stage constructed generator. It is designed as circuit charger of storage capacitor (CS) to generate combination wave impulse application which following standard those set in IEC (International Electrotecnical Commission) 61000-4-5 class 4. CS should be charged up to 4 kV according this standard. High impulse voltage and current works repeatedly in a short time, so the charging system is expected to reach targeted voltage within a maximum time of 10 seconds. Besides charging is also required to design of circuit discharger for discharging electric charge inside the CS. It is expected to reach 0 kV within a maximum time of 15 seconds with overdamped technique. There are three results of the research projects such as output voltage of CW voltage multiplier before connecting CS, charging time of CS, and discharging time of CS. The result showed that CW voltage multiplier can generate up to 12.01 kV on simulation and 11.9 kV on experiment. CS can be charged up to 4 kV in 9.8 seconds on simulation and 7.9 seconds on experiment. CS can be discharged in 14.2 seconds on simulation and 10 seconds on experiment. These results are in accordance with the expectation.

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K., Prasath, Karthigeyan M., Suresh Moorthy P., and Prasanth S. "Generation of High Voltage with Voltage Multiplier for Insulation Testing." Journal of Signal Processing 6, no. 2 (2020): 1–5. https://doi.org/10.5281/zenodo.3778251.

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DC high voltage is used in testing a variety of insulating material. To obtain higher D.C voltage with the low input source in small scale circuit a high step up D.C to D.C converter with voltage multiplier module is designed. Simulation of high step up D.C to D.C converter with 24 stage cascaded voltage multiplier module is designed and the multi-module circuit is developed by connecting the output voltage of each module in series is done using software MATLAB Simulink. The maximum D.C. yield voltage of 50.93 k V is produced utilizing this smaller converter in reenactment. Then the voltage divider is to divided the output voltage for the insulation testing.

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Alzahrani, Ahmad. "A Hybrid DC–DC Quadrupler Boost Converter for Photovoltaic Panels Integration into a DC Distribution System." Electronics 9, no. 11 (2020): 1965. http://dx.doi.org/10.3390/electronics9111965.

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This paper presents a non-isolated DC–DC boost topology with a high-voltage-gain ratio for renewable energy applications. The presented converter is suitable for converting the voltage from low-voltage sources, such as photovoltaic panels, to higher voltage levels. The proposed converter consists of a multiphase boost stage with an interleaving switching technique and a voltage multiplier cell to provide a voltage level at a reduced duty cycle. The interleaved boost stage consists of two legs and can be either fed from single or multiple voltage sources with the ability to control each source separately. The voltage multiplier cell can increase the voltage level by charging and discharging the capacitors. Several advantages are associated with the converter, such as reduced voltage stress on semiconductor elements and a scalable structure, where the number of voltage multiplier cells can be increased. The inductors in the interleaved boost stage share the input current equally, which reduces the conduction loss in the inductors. The input and the output of the converter share the same ground, and all active switches are low-side, which means no feedback or signal isolation is required. The theory of operation and steady-state analysis of the converter operating in the continuous conduction mode is presented. Components selections and efficiency analysis are presented and validated by comparative analysis and simulation results. A 0.195 kW experimental prototype was designed and implemented to convert the voltage from 20 V input source to 400 V output load, at 50 kHz. The test results show a high-performance of the converter as the maximum efficiency point is above 97%.

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Kamarudin, Mohd Khuzairi Bin Che. "CMOS Based SNR Measurement for Wireless Application." Journal of Applied Engineering & Technology (JAET) 2, no. 1 (2018): 9–13. http://dx.doi.org/10.55447/jaet.02.01.7.

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This paper presents the design of a CMOS based Signal to Noise Ratio (SNR) detection system. The design system is developed using divider, multiplier and an additional multiplier in a feedback loop. The divider in the designed system produce 1/V of the signal and multiplier produces the average squared SNR signal. The last stage in this design circuit is a low pass filter necessary to implement the desired “average” measure of the signal to noise ratio (SNR). From simulation, the output voltage of SNR is 9.167mVp-p and from practical, the output voltage is 13.2mVp-p.

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Rohana, Assa Kesthy, Wisnu Djatmiko, Efri Sandi, Agung Pangestu, and Rosyid Ridlo Al Hakim. "Prototype Design of Radio Frequency Energy Harvesting for Lighting Applications." Journal of Global Engineering Research and Science 2, no. 1 (2023): 1–7. http://dx.doi.org/10.56904/j-gers.v2i1.42.

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The prototype resonant frequency is designed to work at 150 MHz. The signal source prototype is the signal that comes from handy talky (HT). There are two subsystems, which are Matching Impedance and Voltage Multiplier. The resonant frequency of the matching impedance subsystem at 143 MHz from 0.053 mH inductor and 0.0233 pF capacitor. The output of the matching impedance subsystem is then amplified by the multiplier voltage subsystem using parallel PH4148 diodes with the 6-stage multiplier. Load prototype is a CR-151 LED that works at 12 volts 1 watt. When the HT battery has a voltage of 7.3 volts, the prototype can turn on the lamp with the distance between the TX antenna and the antenna on the prototype less than 36 cm. The maximum voltage on the load is 6.8 volts with a length of 5 cm between the antenna and the lamp 774 lumen.

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Sinyukin, A. S., B. G. Konoplev, and A. V. Kovalev. "Design of integrated voltage multipliers using standard CMOS technologies." Микроэлектроника 52, no. 6 (2023): 508–17. http://dx.doi.org/10.31857/s0544126923600203.

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Results of the design of the integrated multistage voltage multipliers as components of supply modules for wireless passive microdevices are presented. Parameters of MOS transistors significant for the multipliers design and presented in three standard CMOS technologies, CM018G 180 nm, HCMOS8D 180 nm and C250G 250 nm, are considered. CAD Cadence simulation results have demonstrated that in the case of eight-stage multiplier implementation using CM018G technology minimum output voltage level requisite for microchip operation is achieved at input amplitude 250 mV and in the case of the similar device implementation using HCMOS8D technology - at 375 mV. Using sixteen-stages multiplier as example it is shown that voltage multiplication efficiency is from 20% to 54% for wide range of the input voltage, and the efficiency decreases only by 1-3% compared to eight-stage implementation. Proposed recommendations for the integrated voltage rectifiers-multipliers design could be applied at development of the passive supply units for microelectronic devices.

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Alzahrani, Ahmad, Pourya Shamsi, and Mehdi Ferdowsi. "Interleaved Multistage Step-Up Topologies with Voltage Multiplier Cells." Energies 13, no. 22 (2020): 5990. http://dx.doi.org/10.3390/en13225990.

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This paper proposes a family of high-voltage-gain step-up dc-dc converters for photovoltaic integration application. The proposed converters are capable of converting the low voltage from input sources to a dc bus. The proposed family is constructed of interleaved single-switch multistage boost converters and voltage multiplier cells (VMC). The proposed converters feature low voltage stress across the components, equal current sharing among all phases, and a smooth input current. Moreover, the proposed family of converters has a modular structure in both the VMC and the boost stage. That is, the VMC can have N number of cells, and the boost stage can have k number of stages. The k can be different in each phase, allowing the designers to integrate two independent renewable energy sources with different output voltages. An example converter was explained, analyzed, and simulated. An 80 W hardware prototype was implemented to confirm the converter’s operation and validate the analysis.

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Nguyen, Minh-Khai, and Youn-Ok Choi. "Voltage Multiplier Cell-Based Quasi-Switched Boost Inverter with Low Input Current Ripple." Electronics 8, no. 2 (2019): 227. http://dx.doi.org/10.3390/electronics8020227.

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A novel single-phase single-stage voltage multiplier cell-based quasi-switched boost inverter (VMC-qSBI) is proposed in this paper. By adding the voltage multiplier cell to the qSBI, the proposed VMC-qSBI has the following merits; a decreased voltage stress on an additional switch, a high voltage gain, a continuous input current, shoot through immunity, and a high modulation index. A new pulse-width modulation (PWM) control strategy is presented for the proposed inverter to reduce the input current ripple. To improve the voltage gain of the proposed inverter, an extension is addressed by adding the VMCs. The operating principle, steady-state analysis, and impedance parameter design guideline of the proposed inverter are presented. A comparison between the proposed inverter and other impedance source-based high-voltage gain inverters is shown. Simulation and experimental results are provided to confirm the theoretical analysis.

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Oren, Yarden, Eliav Dahan, Aaron Shmaryahu, et al. "Modeling and Experimental Validation of Broad Input-Output Range Three-Voltage-Level Rectifier." Inventions 9, no. 2 (2024): 37. http://dx.doi.org/10.3390/inventions9020037.

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A new type of single–conversion–step wide–input–range versatile step–up/down three–voltage–level power–factor correction stage is presented in this manuscript. The rectifier can operate both in continuous–conduction mode and discontinuous–conduction mode. First, the rectifier’s principle of operation is described, and then the innovative rectifier is analyzed in continuous and discontinuous–conduction modes. After, an average model for the innovative rectifier is developed. Lastly, the proposed theory is experimentally validated using a multiplier–less dual–control–loop mode at discontinuous–conduction modes. It is shown that although no multiplier is used in the control circuitry, the power factor is near unity. It is revealed that the rectifier can swing the output voltage from 50 V to 900 V while the input voltage is 230 Vrms. Although the rectifier output has a split DC bus with three voltage levels, the required control effort is low, and the output voltage is balanced. The innovative topology suits any standard power–factor correction rectifier application, dual–stage low–voltage power supply, and three–level voltage supplement for low–harmonic inverters. Since the rectifier’s output–voltage swing is extremely wide, energy storage systems and electric vehicle batteries are suitable applications.

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Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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Maezawa, M., F. Hirayama, M. Suzuki, M. Ochiai, and H. Kimura. "Fabrication and operation of a 1024-stage voltage multiplier for ac voltage standard applications." Journal of Physics: Conference Series 43 (June 1, 2006): 1187–90. http://dx.doi.org/10.1088/1742-6596/43/1/289.

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R, Alamelu. "Ultra-High Voltage Boost Converter using Multistage Topology." International Journal for Research in Applied Science and Engineering Technology 13, no. 4 (2025): 3461–66. https://doi.org/10.22214/ijraset.2025.69022.

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This paper presents an Ultra-High Voltage Boost Converter using Multistage Topology that achieves ultrahigh voltage gain with minimal power losses. The proposed converter integrates a dual-stage boost converter, a coupled inductor, and a voltage multiplier cell, enabling efficient energy transfer and recycling of leakage energy. The converter ensures continuous input current, reduces voltage stress on power switches, and decreases passive component size. With its high voltage gain, high efficiency, and compact design, this converter is suitable for various applications, including renewable energy systems, electric vehicles, and high-voltage DC transmission systems

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Kim, Juwan, Inho Park, and Hyunchul Ku. "Design of a Highly Efficient N-Stage Harmonic Terminated Voltage Multiplier for Wireless Power Transfer." Energies 14, no. 21 (2021): 7203. http://dx.doi.org/10.3390/en14217203.

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This paper proposes a 5.8 GHz highly efficient rectifier design using harmonic termination for wireless power transfer. The diode used to convert the received RF power to DC is a non-linear device, and a harmonic component is generated, which causes performance degradation. Therefore, in this paper, we designed a band stop filter for harmonic termination and proposed the N-stage harmonic terminated voltage multiplier (N-stage HTVM). The number of stages N can be designed differently to operate with high efficiency at various input powers for the proposed rectifier. In the proposed rectifier circuit, mathematical analysis of output DC voltage, power loss of the diode, and the power conversion efficiency (PCE) were evaluated through voltage/current waveform analysis of the diode. The design method of the filter for terminating harmonics is presented. Furthermore, the change of PCE according to the increase in the number of stages was analyzed using the equivalent model of the proposed circuit and verified through measurement. The maximum PCE of one-stage HTVM was 68% when 18 dBm of input power was applied. The DC output voltage was measured to 11.6 V. When the RF input power was 25 dBm and the load was 1500 Ω, the maximum PCE of the two-stage HTVM was 71% and the maximum DC output voltage was measured as 15.8 V. The measured performance of three-stage HTVM had a PCE of 67% and DC output voltage of 19.8 V when the input power was 30 dBm.

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CHANG, YUEN-HAW. "HIGH-GAIN/EFFICIENCY MULTISTAGE SWITCHED-CAPACITOR-VOLTAGE-MULTIPLIER DC–DC CONVERTER." Journal of Circuits, Systems and Computers 21, no. 03 (2012): 1250023. http://dx.doi.org/10.1142/s0218126612500235.

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A closed-loop interleaved multistage switched-capacitor-voltage-multiplier (mc × nc-stage SCVM) dc–dc converter is proposed by combining a variable-conversion-ratio (VCR) and pulse-width-modulation (PWM) control for low-power step-up conversion and high-efficiency regulation. In this SCVM, the power part is composed of two mc-stage SC cells (front) and two nc-stage SC cells (rear) in cascade, and these cells are operated by two-phase nonoverlapping clocks for an interleaved operation with voltage gain of mc × nc at most. This paper presents the VCR control to change the running stage number m,n and topological path for a more flexible and suitable gain level m × n (1 × 1, 2 × 1, 2 × 2, 3 × 1, 3 × 2, 3 × 3,…, mc × nc) according to the desired output so as to improve power efficiency, especially for the lower output. Besides, PWM is adopted not only to enhance output regulation for different outputs, but also to reinforce output robustness to source/loading variation. Further, some theoretical analysis and design include: SCVM model, steady-state analysis, conversion ratio, power efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed-loop SCVM is simulated, and the hardware is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme.

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Thulasidas, Jeya Shree, Srinivasan Purushothaman, Srivatsen Ravishanker, Thejaswaroopan Mourougaiyan, and Arruthra Anilkumar. "Low cost pulsed electric field generator using DC-DC boost converter and capacitor diode voltage multiplier." International Journal of Applied Power Engineering (IJAPE) 13, no. 4 (2024): 874. http://dx.doi.org/10.11591/ijape.v13.i4.pp874-885.

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Traditional high-voltage pulse generators, like Marx generators often face challenges related to efficiency and complexity. In this paper, a solid-state multi-module high-voltage pulse generator that integrates capacitor-diode voltage multipliers (CDVM) with DC-DC boost converters and closed-loop voltage control is proposed to overcome these challenges. The system achieves high output voltage by coupling the pulsed output voltages of individual low-voltage DC sources in series across each module. The proposed design was modeled using MATLAB, and experimental testing was conducted on a single stage. Comparative analyses between timedomain parameters, proportional-integral (PI), and fractional order proportional integral derivative (FOPID) controllers were performed. Both MATLAB simulations and experimental validations demonstrate the effectiveness of this approach. The rise time, peak time, settling time, and steady-state error are all improved using an FOPID controller, decreasing from 0.32 to 0.31 seconds, 0.42 to 0.35 seconds, and 3.15 to 2.20 seconds, respectively. These findings indicate that a closed-loop FOPID controller enhances time-domain performance parameters more effectively than a PI controller for a two-stage DC-DC voltage multiplier.

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Thulasidas, Jeya Shree, Srinivasan Purushothaman, Srivatsen Ravishanker, Thejaswaroopan Mourougaiyan, and Arruthra Anilkumar. "Low cost pulsed electric field generator using DC-DC boost converter and capacitor diode voltage multiplier." International Journal of Applied Power Engineering 13, no. 4 (2025): 874–85. https://doi.org/10.11591/ijape.v13.i4.pp874-885.

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Traditional high-voltage pulse generators, like Marx generators often face challenges related to efficiency and complexity. In this paper, a solid-state multi-module high-voltage pulse generator that integrates capacitor-diode voltage multipliers (CDVM) with DC-DC boost converters and closed-loop voltage control is proposed to overcome these challenges. The system achieves high output voltage by coupling the pulsed output voltages of individual low-voltage DC sources in series across each module. The proposed design was modeled using MATLAB, and experimental testing was conducted on a single stage. Comparative analyses between time-domain parameters, proportional-integral (PI), and fractional order proportional integral derivative (FOPID) controllers were performed. Both MATLAB simulations and experimental validations demonstrate the effectiveness of this approach. The rise time, peak time, settling time, and steady-state error are all improved using an FOPID controller, decreasing from 0.32 to 0.31 seconds, 0.42 to 0.35 seconds, and 3.15 to 2.20 seconds, respectively. These findings indicate that a closed-loop FOPID controller enhances time-domain performance parameters more effectively than a PI controller for a two-stage DC-DC voltage multiplier.

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Lara-Reyes, Josué, Mario Ponce-Silva, Leobardo Hernández-González, Susana E. DeLeón-Aldaco, Claudia Cortés-García, and Jazmin Ramirez-Hernandez. "Series RLC Resonant Circuit Used as Frequency Multiplier." Energies 15, no. 24 (2022): 9334. http://dx.doi.org/10.3390/en15249334.

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Currently, the design of resonant power converters has only been developed while operating in the steady state, while the design operating in the transient stage has not been considered nor reported. This paper is interested in testing the performance of the resonant circuits operating in the transient stage and finding applications where benefits can be obtained from this form of operation. One application in which it is possible to obtain benefits from designing resonant circuits in the transient state is in the area of frequency multiplication. Usually, to achieve frequency multiplication, it is necessary to resort to complex methods and special devices that increase the complexity of the design and the total cost of the circuit. This paper evaluates the performance of a series RLC resonant circuit operating in the transient stage and with an underdamped response acting as a frequency multiplier, where the oscillation frequency of the current in the resonant tank is “n” number of times the switching frequency of the square voltage source at the input with a duty cycle of D = 50%. To validate the analysis, a circuit was designed to deliver an output power of 30 watts to a resistive load, where the switching frequency of the square voltage source at the input was 500 kHz. Since a multiplier value “n” equal to fifteen was chosen, the current in the resonant tank reached an oscillation frequency of 7.5 MHz. The design methodology was validated by simulations in SPICE, complying with the established design parameters.

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Choubey, Abhishek, and Shruti Bhargava Choubey. "An area-delay efficient Radix-8 12x12 Booth multiplier in CMOS for ML accelerator." ITM Web of Conferences 74 (2025): 02007. https://doi.org/10.1051/itmconf/20257402007.

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The multiplier is a significant module of graphics processing units (GPUs) and digital signal processing (DSP). These applications need low power consumption. This paper proposes a low-power radix-8 12-by-12 Booth multiplier. The proposed radix-8 Booth multiplier is implemented using an optimized Binary to 2-’s complement (B2C), convertor, and optimized multiplexer at each stage of the Booth multiplier architecture. The proposed architecture uses 23% less power and 12% less delay compared to existing architecture. To validate the results, all designs are synthesized using Cadence CMOS technology 45nm.

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Lin, Jin-Fa, Cheng-Yu Chan, and Shao-Wei Yu. "Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications." Electronics 8, no. 12 (2019): 1429. http://dx.doi.org/10.3390/electronics8121429.

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In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

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Chang, Yuen-Haw, and Ming-Zong Wu. "Generalisedmc × nc-stage switched-capacitor-voltage-multiplier-based boost DC–AC inverter." International Journal of Electronics 99, no. 1 (2012): 29–53. http://dx.doi.org/10.1080/00207217.2011.609978.

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Dalla Vecchia, Mauricio, Giel Van den Broeck, Simon Ravyts, and Johan Driesen. "Novel Step-Down DC–DC Converters Based on the Inductor–Diode and Inductor–Capacitor–Diode Structures in a Two-Stage Buck Converter." Energies 12, no. 6 (2019): 1131. http://dx.doi.org/10.3390/en12061131.

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This paper explores and presents the application of the Inductor–Diode and Inductor-Capacitor-Diode structures in a DC–DC step-down configuration for systems that require voltage adjustments. DC micro/picogrids are becoming more popular nowadays and the study of power electronics converters to supply the load demand in different voltage levels is required. Multiple strategies to step-down voltages are proposed based on different approaches, e.g., high-frequency transformer and voltage multiplier/divider cells. The key question that motivates the research is the investigation of the aforementioned Inductor–Diode and Inductor–Capacitor–Diode, current multiplier/divider cells, in a step-down application. The two-stage buck converter is used as a study case to achieve the output voltage required. To extend the intermediate voltage level flexibility in the two-stage buck converter, a second switch was implemented replacing a diode, which gives an extra degree-of-freedom for the topology. Based on this modification, three regions of operation are theoretically defined, depending on the operational duty cycles δ2 and δ1 of switches S2 and S1. The intermediate and output voltage levels are defined based on the choice of the region of operation and are mapped herein, summarizing the possible voltage levels achieved by each configuration. The paper presents the theoretical analysis, simulation, implementation and experimental validation of a converter with the following specifications; 48 V/12 V input-to-output voltage, different intermediate voltage levels, 100 W power rating, and switching frequency of 300 kHz. Comparisons between mathematical, simulation, and experimental results are made with the objective of validating the statements herein introduced.

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Wijono, Wijono, Eka Maulana, Dony Darmawan Putra, and Waru Djuriatno. "Plasma generator: design of six stage cockcroft-walton voltage multiplier 12 kV for impulse voltage generation." TELKOMNIKA (Telecommunication Computing Electronics and Control) 17, no. 4 (2019): 1890. http://dx.doi.org/10.12928/telkomnika.v17i4.11828.

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Razavi, Seyyed Masoud, and Seyyed Reza Talebiyan. "Novel design of array multiplier." Ciência e Natura 37 (December 19, 2015): 312. http://dx.doi.org/10.5902/2179460x20788.

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In this paper a new array multiplier has been proposed, which has lower power consumption than the regular array multipliers. This technique has been applied on two conventional and leapfrog array multipliers. In the formation of 8×8 multiplier all designs proposed in this paper have been implemented using the HSPICE by the use of 180 nm TSMC technology at a supply voltage 1v. To verify the performance of the proposed structures, structures have been simulated in 130 nm & 65 nm PTM technologies. The simulation results show that applying the return technique in the array structures causes power consumption reduction and consequently PDP reduction. This improvement for 180 nm technology in the conventional array structure is 13.32 % and in the leapfrog array structure is 23.27 %. It should be noted that this technique substantially makes the number of transistors less and as a result area reduction.

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Kosuri, Lakshmi Thirumala, M. Deepika Krishna, Adilakshmi i. Karapat, B. S. B. Ayyappa Swamy, and Dinesh Nayak S. "A Low Power High Speed Accuracy Controllable Approximate Multiplier Design." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (2022): 1625–30. http://dx.doi.org/10.22214/ijraset.2022.41617.

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Abstract: For energy effective and high performance design, the low power VLSI circuit is used. Multiplier is an essential part of low power VLSI design, since the effectiveness of the digital signal processor depends upon the multiplier. In multiplier circuit, utmost of the power is dissipated across in full adder circuits. Multiplication is one of the important process in microprocessor and there will be a lot of delay because of array multiplier, which can be compressed with the help of the column compressor approach. It uses a selection of half adders, full adders and compressors to sum the partial products in stages until two numbers are left. An 8 * 8 and 16 * 16 bit multiplier design is executed by assigning the adder and compressor. Partial product totality is the speed limiting operation in multiplication due to the propagation detention in adder networks. In order to reduce the propagation detention, compressors are introduced. Compressors calculate the sum and carry at each position concurrently. The attendant carry is added with a advanced significant sum bit in the coming stage. This is continued until the final product is generated. The partial product tree of the multiplier is estimated by the proposed tree compressor ( High Speed Compressor, Dual Stage Compressor, Exact Compressor). Keywords: Partial Products, Half Adder, Full Adder, High Speed Compressor, Dual Stage Compressor, Exact Compressor.

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Sahoo, Girija Shankar, Mansingh Meena, Ananya Saha, and Kuldeep Singh Kulhar. "Design of a three level boost converter for fuel cell applications." E3S Web of Conferences 540 (2024): 11003. http://dx.doi.org/10.1051/e3sconf/202454011003.

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This paper presents a simple 3 level DC-DC boost converter for fuel cell applications to boost voltage from 48 V DC to 210 V DC. The main advantages of this converter are its simple design, presence of a single switching element for easy controllability, compact size, low cost and high power density. It is basically a simple boost converter with 3 stage voltage multiplier connected to the output side. Simulation and Hardware results for a power level of 250 W are provided in this paper.

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Kishore Kumar, A., D. Somasundareswari, V. Duraisamy, and T. Shunbaga Pradeepa. "Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL." VLSI Design 2013 (March 21, 2013): 1–9. http://dx.doi.org/10.1155/2013/157872.

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Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

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Young, C. M., M. H. Chen, and C. C. Ko. "High power factor transformerless single-stage single-phase ac to high-voltage dc converter with voltage multiplier." IET Power Electronics 5, no. 2 (2012): 149. http://dx.doi.org/10.1049/iet-pel.2010.0380.

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Dr Vasudevan K, Pilli Swapana Priya, Katta Mounisha, Gudise Venkata Lakshmi Narayana Reddy, Kommuri V Naga Sai Lakshmi Sowmya, and Kummararamannagari Dheeraj`. "Power quality improvements in a zeta conveter for brushless dc motor drives." South Asian Journal of Engineering and Technology 12, no. 2 (2022): 44–49. http://dx.doi.org/10.26524/sajet.2022.12.30.

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   An isolated Zeta converter is proposed as a power factor correction (PFC) converter with DC link voltage control for speed control of a induction motor (3 IM). The voltage source inverter (VSI). The proposed converter performs the PFC action and DC link voltage control in single stage using only one controller. The current multiplier approach with average current control is used for operation of the isolated Zeta converter in continuous conduction mode (CCM). A rate limiter in the reference DC link voltage is designed for the control of current and torque in 3 PHASE IM. The designed PFC converter results in an improved power quality at AC mains in a wide range of speed control and input AC voltage  

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Tao, Xiaobing, Chao Liu, and Tao Zhao. "A four-quadrant analog multiplier under a single power supply voltage." Analog Integrated Circuits and Signal Processing 71, no. 3 (2011): 525–30. http://dx.doi.org/10.1007/s10470-011-9692-8.

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Vyas, Rushi, Sichong Li, and Fadhel Ghannouchi. "Using 2.4 GHz load-side voltage standing waves to passively boost RF-DC voltage conversion in RF rectifier." Wireless Power Transfer 6, no. 2 (2019): 113–25. http://dx.doi.org/10.1017/wpt.2019.12.

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AbstractA novel, dual-band, voltage-multiplying (RF-DC) rectifier circuit with load-tuned stages resulting in a 50 Ω input-impedance and high RF-DC conversion in 2.4 and 5.8 GHz bands for wireless energy-harvesting is presented. Its novelty is in the use of optimal-length transmission lines on the load side of the 4 half-wave rectifying stages within the two-stage voltage multiplier topology. Doing so boosts the rectifier's output voltage due to an induced standing-wave peak at each diode's input, and gives the rectifier a 50 Ω input-impedance without an external-matching-network in the 2.4 GHz band. Comparisons with other rectifiers show the proposed design achieving a higher DC output and better immunity to changing output loads for similar input power levels and load conditions. The second novelty of this rectifier is a tuned secondary feed that connects the rectifier's input to its second stage to give dual-band performance in the 5.8 GHz band. By tuning this feed such that the second stage and first stage reactances cancel, return-loss resonance in the 5.8 GHz band is achieved in addition to 2.4 GHz. Simulations and measurements of the design show RF-DC sensitivity of −7.2 and −3.7 dBm for 1.8V DC output, and better than 10 dB return-loss, in 2.4 and 5.8 GHz bands without requiring an external-matching-network.

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Wang, Chua-Chin, Lean Karlo S. Tolentino, Pin-Chuan Chen, et al. "A 40-nm CMOS Piezoelectric Energy Harvesting IC for Wearable Biomedical Applications." Electronics 10, no. 6 (2021): 649. http://dx.doi.org/10.3390/electronics10060649.

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This investigation presents an energy harvesting IC (integrated circuit) for piezoelectric materials as a substitute for battery of a wearable biomedical device. It employs a voltage multiplier as first stage which uses water bucket fountain approach to boost the very low voltage generated by the piezoelectric. The boosted voltage was further improved by the boost DC/DC converter which follows a predefined timing control directed by the digital logic for the said converter to be operated efficiently. TSMC 40-nm CMOS process was used for implementation and fabrication of the energy harvesting IC. The chip’s core has an area of 0.013 mm2. With an output of 1 V which is enough to supply the wearable biomedical devices, it exhibited the highest pump gain and accommodated the lowest piezoelectric generated voltage among recent related works.

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Ahmed, Rekib U., Sheba D. Thabah, Mridul Haque, and Prabir Saha. "Efficient Modulo Multiplier." Electronics ETF 27, no. 1 (2023): 18–24. http://dx.doi.org/10.53314/els2327018a.

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The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulation using Virtex-6 device has been performed to estimate delay, power consumption, and power-delay product (PDP). Moreover, the modulo multipliers are simulated in Cadence RC compiler using 0.18 µm technology to estimate the area. One of the major contributions to the arts of this work is in the partial product reduction stage which utilizes the multi-column 5,5:4 compressor to reduce power and area. The modulo 2n−1 multiplier of operand size 4-bit shows an improvement of 66.34% in terms of area over the best-reported paper. On the other hand, the modulo 2n+1 multiplier of operand size 4-bit shows an improvement of 58.59% terms of in area and the same of operand size 8-bit shows an improvement of 22.72% over the best-reported paper. The proposed algorithms of moduli multiplication are applicable to Booth multiplication of signed numbers.

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Jagadeeswara Rao, E., K. Jayaram Kumar, and Dr T. V. Prasad. "Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors." International Journal of Engineering & Technology 7, no. 4 (2018): 2386. http://dx.doi.org/10.14419/ijet.v7i4.12261.

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Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.

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Tadivaka, Teja Sreenu, M. Kiran Kumar, G. Rami Reddy, Ch Rami Reddy, and Ch Rami Reddy. "Enhanced Luo Converter for Low Component Stress in DC-DC Power Conversion for Fuel Cell Powered BLDC Motor Drive." International Journal of Electrical and Electronics Research 13, no. 1 (2025): 171–77. https://doi.org/10.37391/ijeer.130122.

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Fuel cell powered BLDC motor drive for electric vehicle is the cleaner energy conversion solution with higher efficiency. DC-DC power conversion in this drive plays a significant role in adoptability, efficiency and reliability of the overall drive. This paper presents an enhanced Luo converter for increased voltage gain with additional multiplier stage and reduced capacitor voltage stress owing to reduced clamping voltage. The topology, operational modes, and mathematical analysis of the proposed power conversion are presented. Simulation is carried out in MATLAB/SIMULINK platform which analyzed operational parameters such as output voltage ripple, output voltage regulation, converter components voltage stress, and inductor current ripple. Also, the proposed converter structural advantages are compared to existing converters. The findings on operational and structural parameters resulted in stringent output regulation less than 1 percent for desired output voltage. Also, 41.67 percent reduction is observed for voltage stress across converter capacitors. Thus, an enhanced Luo DC-DC power conversion is designed and validated for fuel cell powered BLDC motor-based EV drive.

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Amiri, Mina, and Adib Abrishamifar. "A High-Linear CMOS Down Conversion Mixer Using Adjusting the Second and Third-Order Harmonic in Transconductance Stage." Journal of Circuits, Systems and Computers 24, no. 01 (2014): 1550002. http://dx.doi.org/10.1142/s0218126615500024.

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In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1 V is applied to the circuit. Simulation results of improved mixer in a 0.18-μm CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.

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Moradisizkoohi, Hadi, Nour Elsayad, and Osama Mohammed. "A Soft-Switched DC/DC Converter Using Integrated Dual Half-Bridge with High Voltage Gain and Low Voltage Stress for DC Microgrid Applications." Inventions 3, no. 3 (2018): 63. http://dx.doi.org/10.3390/inventions3030063.

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In this paper, a soft-switched boost converter including an integrated dual half-bridge circuit with high voltage gain and continuous input current is introduced that can be suitable for the applications requiring a wide voltage gain range, such as for the front-end of the inverter in a DC microgrid to integrate renewable energy sources (RES). In the proposed converter, two half-bridge converters are connected in series at the output stage to enhance the voltage gain. Additionally, the balanced voltage multiplier stage is employed at the output to increase the voltage conversion ratio, as well as distribute the voltage stress across semiconductors; hence, switches with smaller on-resistance RDS(on) can be adopted resulting in an improvement in the efficiency. The converter takes advantage of the clamp circuit not only to confine the voltage stress of switches, but also to achieve the soft-switching, which leads to a reduction in the switching loss as well as the cost. The mentioned features make the proposed converter a proper choice for interfacing RES to the DC-link bus of the inverter. The operation modes, steady-state analysis, and design consideration of the proposed topology have been demonstrated in the paper. A 1-kW laboratory prototype was built using gallium nitride (GaN) transistors and silicon carbide (SiC) diodes to confirm the effectiveness of the proposed topology.

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Chouhan, Shailesh Singh, та Kari Halonen. "A 0.18 $$\upmu$$ μ m CMOS voltage multiplier arrangement for RF energy harvesting". Analog Integrated Circuits and Signal Processing 92, № 3 (2017): 343–53. http://dx.doi.org/10.1007/s10470-017-1001-8.

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Vinodini Bhole. "Augmented SPWM based Hybrid Output Converter for Renewable Energy and Nano-Grid Application." Journal of Electrical Systems 20, no. 3 (2024): 2072–88. http://dx.doi.org/10.52783/jes.4007.

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This study suggests a novel Augmented Sine PWM(ASPWM) based Hybrid Output Converter that can concurrently power AC and DC loads. Two boost converters are used in this configuration, and the AC voltage is the differential voltage tapped between the two source nodes (of the MOSFETs) of the individual converters. This converter plays a different role in providing power to AC and DC loads than conventional boost converter. Conventional boost requires a minimum of two stages to step up output DC voltage and inverter stage to convert DC to AC power. This novel hybrid output converter (HOC) skips all stages of boosting the output voltage and next stage of inverter also. HOC consists of two boost converts pumped by two VM(voltage multiplier) stages to get high voltage DC output. This HOC has two inputs, supplied by renewable like solar PV cells and has two outputs to supply AC and DC loads simultaneously. This dual input HOC integrates two renewable inputs for standalone nano grid application. The principle of operation of HOC is augmented sinusoidal pulse width modulation with AC reference signal is shifted by 1800for individual boost converter and augmented by dc offset. The circuit has been extensively simulated in PSIM’22 Matlab Simulink and an experimental prototype of 110W is tested in the laboratory.

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Krishnaveni, Akkela, and Rajender Boini. "A single switch high gain multilevel boost converter with switched inductor topology for photovoltaic applications." SciEnggJ 17, Supplement2024 (2024): 8–16. http://dx.doi.org/10.54645/202417supdwr-69.

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This paper proposes a new transformer-less single-switch high-gain dc-dc converter for solar power systems. The suggested converter is created by supplementing the conventional boost converter with a switched inductor cell plus a voltage multiplier stage. The converter has several benefits, including a high voltage conversion ratio, reduced voltage stress on semiconducting switches and diodes, a reduction in the need for gate drivers because only one switch is used, as well as constant input current to prolong the lifespan of the photovoltaic cell. The analytical waveforms of the recommended converter can be seen in the continuous conduction mode (CCM). The analysis of voltage stress is done. In the presence of parasitic components, increased voltage gain and efficiency were also obtained.The proposed high-gain converter topology is compared to recently published high-gain converter topologies in terms of performance. Using PSIM, a high-gain dc-dc converter's performance is studied and analysed with regard to its low switching voltage stress. The suggested converter is successful in stepping up 20V to 400V at 160W power capacity, while offering a continuous input source current at 95% efficiency.

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