Relevant bibliographies by topics / 90nm technology

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic '90nm technology'

Author: Grafiati
Published: 4 June 2021
Last updated: 14 February 2022

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Journal articles on the topic "90nm technology"

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Mine, B., M. Kuhn, M. McKeag, J. Brandt, T. Brookshier, B. Davies, and K. Headley. "Microscopy of Interconnects for 90nm Technology." Microscopy and Microanalysis 9, S02 (July 22, 2003): 462–63. http://dx.doi.org/10.1017/s1431927603442311.

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Krishna, B. T., and Shaik mohaseena Salma. "A Flux Controlled Memristor using 90nm Technology." Indian Journal of Signal Processing 1, no. 2 (May 10, 2021): 1–6. http://dx.doi.org/10.35940/ijsp.b1004.051221.

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A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the highfrequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.
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Ganesh, R. "Design of Switched Capacitor Integrators using 90nm Technology." CVR Journal of Science & Technology 7, no. 1 (December 1, 2014): 37–41. http://dx.doi.org/10.32377/cvrjst0706.

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Rajendra Patel, Chiranjit, Vivek Bettadapura Adishesha, Vivek Urankar, and Keshav Vaidyanathan Bharadwaj. "Inverted Gate Vedic Multiplier in 90nm CMOS Technology." American Journal of Electrical and Computer Engineering 4, no. 1 (2020): 10. http://dx.doi.org/10.11648/j.ajece.20200401.12.

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Shukla, Neha, and Jasbir Kaur. "Analysis of Two Stage CMOS Opamp using 90nm Technology." International Journal of Engineering and Technology 9, no. 3S (July 17, 2017): 66–72. http://dx.doi.org/10.21817/ijet/2017/v9i3/170903s013.

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Polzer, A., K. Schneider-Hornstein, J. Dong, P. Kostov, and H. Zimmermann. "Investigation of triple-junction photodetector in 90nm CMOS technology." Procedia Engineering 25 (2011): 864–67. http://dx.doi.org/10.1016/j.proeng.2011.12.212.

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Singh, Rashmi, and Rajesh Mehra. "Low Noise Amplifier using Darlington Pair At 90nm Technology." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 4 (August 1, 2018): 2054. http://dx.doi.org/10.11591/ijece.v8i4.pp2054-2062.

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<p class="Abstract"><span>The demand of low noise amplifier (LNA) has been rising in today’s communication system. LNA is the basic building circuit of the receiver section satellite. The design concept demonstrates the design trade off with NF, gain, power consumption. This paper reports on with analysis of wideband LNA. This paper shows the schematic of LNA by using Darlington pair amplifier. This LNA has been fabricated on 90nm CMOS process. This paper is focused on to make comparison of three stage and single stage LNA. Here, the phase mismatch between these patameters is quantitavely analyzed to study the effect on gain and noise figure (NF). In this paper, single stage LNA has shown the 23 dB measured gain, while the three stages LNA has demonstrated 29 dB measured gain. Here, LNA designed using darlington pair shows low NF of 3.3-4.8 dB, which comparable to other reported single stage LNA designs and appreciably low compared to the three stages LNA. Hence, findings from this paper suggest the use of single stage LNA designed using Darlington pair in transceiver satellite applications.</span></p>
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Harish, Basavoju, and M. S. S. Rukmini. "Ultra high speed full adder for biomedical applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 1 (March 1, 2021): 25. http://dx.doi.org/10.11591/ijres.v10.i1.pp25-31.

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In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.
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Malhotra, Akshay, and Rajesh Mehra. "Area efficient SR flip-flop designed using 90nm CMOS technology." International Journal of Advanced Technology and Engineering Exploration 5, no. 44 (July 21, 2018): 221–26. http://dx.doi.org/10.19101/ijatee.2018.545002.

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Bringas, R., F. Dy, and O. J. Gerasta. "10-bit segmented current steering DAC in 90nm CMOS technology." IOP Conference Series: Materials Science and Engineering 79 (June 10, 2015): 012005. http://dx.doi.org/10.1088/1757-899x/79/1/012005.

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Dissertations / Theses on the topic "90nm technology"

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Shuaib, Muhammad. "Two-Tone PLL for On-Chip Test In 90nm-Technology." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18590.

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In this report the two-tone PLL circuit intended for on-chip test of RF blocks is presented. The primary application is the third order intermodulation test (TOI), vital for RF front-ends. If the spectral analysis can also be completed by DSP available on the chip or on board, it provides a built in self-test (BiST) which can replace costly test instrumentation (ATE). The advantage of the designed two-tone PLL is that it practically prevents the locking effect while keeping the two oscillation frequencies close. Also by careful design the possible intermodulation distortion of the two-tone stimulus can be avoided.

The two-tone PLL has been designed and verified at the system level using Verilog-A models in Cadence TM. Besides, two building blocks of the PLL were implemented at the circuit level in 90nm CMOS technology. The obtained results are promising in terms of a practical two-tone BiST implementation.

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Veerakitti, Paesol. "High Frequency VCO and Frequency Divider in VLSI 90nm Technology." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1278426944.

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Dhillon, Gurbhej Singh. "TUNABLE TIME DELAY ELEMENTS IN CMOS 90nm TECHNOLOGY FOR NOVEL VCO IMPLEMENTATION." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1269608522.

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Hassan, Raza Naqvi Syed. "1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.

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The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.

Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

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Shahzad, Bilal. "System Analysis and Implementation of Delta-Sigma Modulator Topologies with Low Gain Amplifiers in 90nm CMOS." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-52888.

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Data converters are one of the key components in many applications ranging from wireless communication to data acquisitions system, sensors, audio electronics, video display electronics and analog microcontrollers. All of these use some type of data converter to perform the task of signal processing/condition for example in RF transceivers the received analog signal after passing through filters is converted to digital signal for further processing. The use of delta-sigma modulators nowadays are gaining popularity over the other A/D converters because of sampling and noise shaping. Also the architecture of delta sigma modulator is a mixed system, and digital filters are present (to remove noise in case of MASH architecture) so because of these reason many programmable features can be used in the applications employing delta sigma modulator. This thesis presents a type of delta sigma modulator which focuses on using of low gain operational amplifier and hence to operate at low voltage technologies and be more power efficient. Two topologies were presented, one having a single loop architecture but with a very highly aggressive NTF and other using multi-stage architecture with no additional digital filter to achieve the required specifications. The thesis presents the complete system analysis of the topologies, and the non-idealities modeling at system level. Then the transistor level design of the designed topologies was done in Cadence in 90nm CMOS. Each component of the designed modulator was tested individually at circuit level. The complete system was analyzed using the Verilog-A model.
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Preston, Douglas. "Last Two Surface Range Detector for Direct Detection Multisurface Flash Lidar in 90nm CMOS Technology." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright150392243439439.

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Fazli, Yeknami Ali. "Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12260.

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This thesis presents a novel six-transistor SRAM intended for advanced

microprocessor cache application. The objectives are to reduce power

consumption through scaling the supply voltage and to design a SRAM that is fully process-variation-tolerant, utilizing separate read and write access ports as well as exploiting asymmetry. Traditional six-transistor SRAM is designed and its strengths and weaknesses are discussed in detail. Afterwards, a new SRAM technology developed in the division of Electronic Devices, Linköping University is proposed and its capabilities and drawbacks are illustrated deeply. Subsequently, the impact of mismatch and process variation on both standard 6T and proposed asymmetric 6T SRAM cells is investigated. Eventually, the cells are compared regarding the voltage scalability, stability, and tolerability to variations in process parameters. It is shown that the new cell functions in 430mV while maintaining acceptable SNM margin in all process corners. It is also demonstrated that the proposed SRAM is fully process-variation-tolerant.

Additionally, a dual-V t asymmetric 6T cell is introduced having wide SNM margin comparable with that of conventional 6T cell such that it is capable of functioning in 580mV.

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Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.

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Öresjö, Per. "A High Speed Sigma Delta A/D-Converter for a General Purpose RF Front End in 90nm-Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8706.

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In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.

The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.

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Dommaraju, Sunny Raj. "Design and Implementation of a 16-Bit Flexible ROM-less Direct Digital Synthesizer in FPGA and CMOS 90nm Technology." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1374351629.

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Books on the topic "90nm technology"

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Wang, Robert. A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology. 2004.

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Book chapters on the topic "90nm technology"

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Lu, Shibin, Ying Meng, Feifei Wang, and Xianwei Jiang. "A Low-Power Dual-Modulus Prescaler in 90nm CMOS Technology." In Advances in Mechanical and Electronic Engineering, 163–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31528-2_27.

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Sakare, Mahendra, Mohit Singh, and Shalabh Gupta. "A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology." In Progress in VLSI Design and Test, 252–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31494-0_29.

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Sajin, C. S., and T. A. Shahul Hameed. "Simulation and Performance analysis of Cascode amplifiers in 90nm and 45nm Technology." In A Collection of Contemporary Research Articles in Electronics, Communication and Computation, 348. Mantech Publications, 2021. http://dx.doi.org/10.47531/mantech/ecc.2021.53.

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Sarma, Rajkumar, Cherry Bhargava, and Shruti Jain. "PVT Variability Check on UCM Architectures at Extreme Temperature-Process Changes." In AI Techniques for Reliability Prediction for Electronic Components, 238–51. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1464-1.ch013.

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The UCM (universal compressor-based multiplier) architecture promises to provide faster multiplication operation in supply voltage as low as 0.6 V. The basic component of UCM architecture is a universal compressor architecture that replaces the conventional Wallace tree algorithm. To extend the work further, in this chapter, a detailed PVT (process-voltage-temperature) analysis is performed using Cadence Virtuoso 90nm technology. The analysis shows that the delay of the UCM has reduced more significantly than the Wallace tree algorithm at extreme process, voltage, and temperature.
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Kumar, Abhishek. "40-GHz Inductor Less VCO." In AI Techniques for Reliability Prediction for Electronic Components, 288–98. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-1464-1.ch016.

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In a modern communication system, voltage-controlled oscillator (VCO) acts as a basic building block for frequency generation. VCO with LC tank is preferred with passive inductor and varactor in radio frequency. Practical tuning range of VCO is low and unsuitable for wideband application. Switched capacitor and inductor can widen but at cost of chip area and complex system architecture. To overcome it, an equivalent circuit of the inductor is created. In this work, inductor-less VCO is implemented with CMOS 90nm technology that has center frequency 40GHz and frequency tuning range 37.7GHz to 41.9GHz.
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Hodgkinson, Anna K. "Household or Cottage Industries: Modelling Industrial Diversity in New Kingdom Houses and Courtyards." In Technology and Urbanism in Late Bronze Age Egypt. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780198803591.003.0015.

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Both O45.1 at Amarna and IA1 at Gurob, discussed in Chapter 6, can be said to have been purpose-built and to some extent specialized, with the presence of kilns indicating a somewhat focused set of activities. By contrast, the smaller houses, or groups of the same in New Kingdom settlements have been observed to be generally less industrially focused or specialized on all levels. The present chapter therefore discusses a number of case-studies demonstrating artefact diversity in a range of houses, showcasing their variety both in appearance and in functionality. These case-studies include a range of houses in the Main City at Amarna and a comparison of the artefactual evidence they contained of relevant industrial activities in addition to Site J at Malqata. Excavations at Site J in the 1970s have revealed a series of small ovens, the purpose and locations of which will be discussed together with associated objects. This and the artefactual data from the houses at Amarna will provide an insight into the organization of industrial activities on a household-level. In the course of the spatial analysis undertaken for the Main City North (MCN) at Amarna (see Section 2.4), it has become apparent that thirty-four buildings, dispersed throughout this suburb, contained evidence not only of one industrial activity discussed in this book, but of several. The houses, each of which contains evidence of more than one industry, cover a range of varying sizes. While most of these thirty-four houses had a smaller ground area (less than 900m²), some larger ones also contained evidence of multiple industries. Eight of the thirty-four had an area of less than 100m², while a total of sixteen covered between 100 and 900m², the remaining ten houses being larger than 900m² including their courtyards. While most of the larger houses measured between 900 and 3,000m², three houses are even larger than this, with the largest property, R44.2, which measured over 10,000m², belonging to a ‘Steward of Akhenaten’. Table 7.1 demonstrates the combinations of industries queried with the GIS that were in operation in a number of buildings.
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Conference papers on the topic "90nm technology"

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Barbier-Petot, C., S. Bardy, C. Biard, and P. Descamps. "Substrate isolation in 90nm RF-CMOS technology." In 2005 European Microwave Conference. IEEE, 2005. http://dx.doi.org/10.1109/eumc.2005.1608800.

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Singh, Rashmi, and Rajesh Mehra. "Analysis of darlington pair amplifier at 90nm technology." In 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). IEEE, 2016. http://dx.doi.org/10.1109/iceeot.2016.7755385.

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Khatak, Anil, anoj Kumar, and Sanjeev Dhull. "Comparative analysis of comparators in 90nm CMOS Technology." In 2018 International Conference on Power Energy, Environment and Intelligent Control (PEEIC). IEEE, 2018. http://dx.doi.org/10.1109/peeic.2018.8665656.

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Ikeda, Tatsuhiko, Yuuichi Hirano, Toshiaki Iwamatsu, Daniel Chen, Tsutomu Yoshimura, Takashi Ipposhi, Shigeto Maegawa, Masahide Inuishi, and Yuzuru Ohji. "A 90nm-node SOI Technology for RF Applications." In 2004 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2004. http://dx.doi.org/10.7567/ssdm.2004.c-5-3.

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Zhang, Yuan. "Designing to win in sub-90nm mask production." In Photomask Technology 2005, edited by J. Tracy Weed and Patrick M. Martin. SPIE, 2005. http://dx.doi.org/10.1117/12.637610.

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Shukla, Neeraj Kumar, Shilpi Birla, and R. K. Singh. "Synthesis and Modeling of Spiral Inductor at 90nm Technology." In 2009 International Conference on Advances in Recent Technologies in Communication and Computing. IEEE, 2009. http://dx.doi.org/10.1109/artcom.2009.34.

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Ibrahim, Sameh A., and Behzad Razavi. "A 20Gb/s 40mW equalizer in 90nm CMOS technology." In 2010 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2010. http://dx.doi.org/10.1109/isscc.2010.5433999.

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Ren, Saiyu, Steven Billman, and Ray Siferd. "Multiplier-less Digital Down Converter in 90nm CMOS technology." In NAECON 2011 - IEEE National Aerospace and Electronics Conference. IEEE, 2011. http://dx.doi.org/10.1109/naecon.2011.6183123.

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Khatak, Anil, Manoj Kumar, and Sanjeev Dhull. "Power analysis of Flash-ADC in 90nm CMOS Technology." In 2018 International Conference on Sustainable Energy, Electronics, and Computing Systems (SEEMS). IEEE, 2018. http://dx.doi.org/10.1109/seems.2018.8687343.

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Haddad, Nadim, Ernesto Chan, Scott Doyle, Andrew Kelly, Reed Lawrence, David Lawson, Dinu Patel, and Jason Ross. "The path and challenges to 90nm radiation hardened technology." In 2008 European Conference on Radiation and Its Effects on Components and Systems (RADECS). IEEE, 2008. http://dx.doi.org/10.1109/radecs.2008.5782725.

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