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Journal articles on the topic '90nm technology'

Author: Grafiati

Published: 4 June 2021

Last updated: 14 February 2022

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1

Mine, B., M. Kuhn, M. McKeag, J. Brandt, T. Brookshier, B. Davies, and K. Headley. "Microscopy of Interconnects for 90nm Technology." Microscopy and Microanalysis 9, S02 (July 22, 2003): 462–63. http://dx.doi.org/10.1017/s1431927603442311.

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2

Krishna, B. T., and Shaik mohaseena Salma. "A Flux Controlled Memristor using 90nm Technology." Indian Journal of Signal Processing 1, no. 2 (May 10, 2021): 1–6. http://dx.doi.org/10.35940/ijsp.b1004.051221.

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A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the highfrequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

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3

Ganesh, R. "Design of Switched Capacitor Integrators using 90nm Technology." CVR Journal of Science & Technology 7, no. 1 (December 1, 2014): 37–41. http://dx.doi.org/10.32377/cvrjst0706.

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4

Rajendra Patel, Chiranjit, Vivek Bettadapura Adishesha, Vivek Urankar, and Keshav Vaidyanathan Bharadwaj. "Inverted Gate Vedic Multiplier in 90nm CMOS Technology." American Journal of Electrical and Computer Engineering 4, no. 1 (2020): 10. http://dx.doi.org/10.11648/j.ajece.20200401.12.

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5

Shukla, Neha, and Jasbir Kaur. "Analysis of Two Stage CMOS Opamp using 90nm Technology." International Journal of Engineering and Technology 9, no. 3S (July 17, 2017): 66–72. http://dx.doi.org/10.21817/ijet/2017/v9i3/170903s013.

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6

Polzer, A., K. Schneider-Hornstein, J. Dong, P. Kostov, and H. Zimmermann. "Investigation of triple-junction photodetector in 90nm CMOS technology." Procedia Engineering 25 (2011): 864–67. http://dx.doi.org/10.1016/j.proeng.2011.12.212.

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7

Singh, Rashmi, and Rajesh Mehra. "Low Noise Amplifier using Darlington Pair At 90nm Technology." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 4 (August 1, 2018): 2054. http://dx.doi.org/10.11591/ijece.v8i4.pp2054-2062.

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<p class="Abstract"><span>The demand of low noise amplifier (LNA) has been rising in today’s communication system. LNA is the basic building circuit of the receiver section satellite. The design concept demonstrates the design trade off with NF, gain, power consumption. This paper reports on with analysis of wideband LNA. This paper shows the schematic of LNA by using Darlington pair amplifier. This LNA has been fabricated on 90nm CMOS process. This paper is focused on to make comparison of three stage and single stage LNA. Here, the phase mismatch between these patameters is quantitavely analyzed to study the effect on gain and noise figure (NF). In this paper, single stage LNA has shown the 23 dB measured gain, while the three stages LNA has demonstrated 29 dB measured gain. Here, LNA designed using darlington pair shows low NF of 3.3-4.8 dB, which comparable to other reported single stage LNA designs and appreciably low compared to the three stages LNA. Hence, findings from this paper suggest the use of single stage LNA designed using Darlington pair in transceiver satellite applications.</span></p>

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8

Harish, Basavoju, and M. S. S. Rukmini. "Ultra high speed full adder for biomedical applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 1 (March 1, 2021): 25. http://dx.doi.org/10.11591/ijres.v10.i1.pp25-31.

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In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

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9

Malhotra, Akshay, and Rajesh Mehra. "Area efficient SR flip-flop designed using 90nm CMOS technology." International Journal of Advanced Technology and Engineering Exploration 5, no. 44 (July 21, 2018): 221–26. http://dx.doi.org/10.19101/ijatee.2018.545002.

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10

Bringas, R., F. Dy, and O. J. Gerasta. "10-bit segmented current steering DAC in 90nm CMOS technology." IOP Conference Series: Materials Science and Engineering 79 (June 10, 2015): 012005. http://dx.doi.org/10.1088/1757-899x/79/1/012005.

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11

Seidel, Ismael, André Beims Bräscher, Bruno George De Moraes, Marcio Monteiro, and José Luis Güntzel. "Analysis of Pel Decimation and Technology Choices to Reduce Energy on SAD Calculation." Journal of Integrated Circuits and Systems 9, no. 1 (December 28, 2014): 48–59. http://dx.doi.org/10.29292/jics.v9i1.388.

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As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC and VP9, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. First, we analyze the quality costs of pel decimation using a video coding software. Then we present and evaluate two VLSI architectures to compute the SAD of 4x4 pixel blocks: one that can be configured with 1:1, 2:1 or 4:1 sampling ratios and a non-configurable one, to serve as baseline in comparisons. The architectures were synthesized for 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and for a given target throughput. The impacts of both subsampling and LH on delay, power and energy efficiency are analyzed. In a total of 24 syntheses, the 45nm/LH configurable SAD architecture synthesis achieved the highest energy efficiency for target throughput when operating in pel decimation 4:1, spending only 2.05pJ for each 4×4 block. This corresponds to about 13.65 times less energy than the 90nm/nominal configurable architecture operating in full sampling mode and maximum throughput and about 14.77 times less than the 90nm/nominal non-configurable synthesis for target throughput. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when choosing 2:1 and 4:1 subsampling ratios, respectively, in the configurable architecture. Finally, it is shown that the configurable architecture is more energy-efficient than the non-configurable one.

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12

Hasani, Javad Yavand, Mahmoud Kamarei, and Fabien Ndagijimana. "Analytic input matching for millimeter wave LNA in 90nm CMOS technology." IEICE Electronics Express 4, no. 15 (2007): 472–77. http://dx.doi.org/10.1587/elex.4.472.

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13

S Vaghela, Ratansang, and Priyesh P. Ghandhi. "Analysis and Simulation of Dynamic Comparator Using 180nm and 90nm Technology." International Journal of Microelectronics Engineering 2, no. 2 (April 30, 2016): 1–8. http://dx.doi.org/10.5121/ijme.2016.2201.

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14

Kaur, Jasbir, and Neha Shukla. "Analysis of Two Stage Folded Cascode Operational Amplifier in 90nm Technology." IJIREEICE 5, no. 6 (June 15, 2017): 149–56. http://dx.doi.org/10.17148/ijireeice.2017.5626.

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15

S, Saloni, and Dr Neelam Rup Prakash. "Low Power 4*4 Canonical Signed Digit Multiplier using 90nm Technology." IJIREEICE 5, no. 6 (June 15, 2017): 205–10. http://dx.doi.org/10.17148/ijireeice.2017.5635.

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16

Karami, Mohammad Azim, Marek Gersbach, Hyung-June Yoon, and Edoardo Charbon. "A new single-photon avalanche diode in 90nm standard CMOS technology." Optics Express 18, no. 21 (October 5, 2010): 22158. http://dx.doi.org/10.1364/oe.18.022158.

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17

Hai-Feng, Chen, Hao Yue, Ma Xiao-Hua, Zhang Jin-Cheng, Li Kang, Cao Yan-Rong, Zhang Jin-Feng, and Zhou Peng-Ju. "Investigation of the characteristics of GIDL current in 90nm CMOS technology." Chinese Physics 15, no. 3 (March 2006): 645–48. http://dx.doi.org/10.1088/1009-1963/15/3/034.

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18

Lim, K. Y., V. Chan, R. Rengarajan, H. K. Lee, N. Rovedo, E. H. Lim, S. Yang, et al. "A robust 45nm gate-length CMOSFET for 90nm Hi-speed technology." Solid-State Electronics 50, no. 4 (April 2006): 579–86. http://dx.doi.org/10.1016/j.sse.2006.03.031.

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19

Zhou, Dong-Yi, Peng He, Ri-Hui Sun, Yi Yang, Xiao-Chun Kang, Jian-Yong Jiang, and Paul-Chang Lin. "Study on the Solution of via Bottom Void in 90nm Technology." ECS Transactions 44, no. 1 (December 15, 2019): 745–49. http://dx.doi.org/10.1149/1.3694393.

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20

M. S, Pavan ,., M. Nagabushanam, Sushmita Hawaldar, and S. L. Gangadharaiah. "Capacitor-less Low-Dropout Regulator for Analog Sensing using 90nm Technology." International Journal of Circuits, Systems and Signal Processing 15 (August 30, 2021): 1184–96. http://dx.doi.org/10.46300/9106.2021.15.129.

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The capacitor-less-output-low-dropout (CLO-LDO) regulator proposed in this study can manage a wide variety of load currents. To offer temperature independent controlled LDO output, the LDO's 0.844V reference voltage is obtained using BGR, the optimized design is presented that provide full range stability, fast transient response. These benefits allow the proposed LDO regulator to operate over a wide range of operating circumstances, with very high current efficiency 99.99% and low voltage drop 100mV, operating using very low quiescent current of 0.02µA, at the output of regulator. The proposed regulator design is constructed in 90nm CMOS technology, the structure of the regulator is implemented using a Two-stage operational amplifier to obtain large DC gain 50dB to improve supply noise rejection, and a feedback loop, and exhibits better performance in terms of large phase margin 64.516 degrees with no load and 70.63degree full load.

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21

Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

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22

Kalia, Kartik, Khyati Nanda, Arushi Aggarwal, Akshita Goel, and Shivani Malhotra. "Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA." Advanced Materials Research 1098 (April 2015): 37–43. http://dx.doi.org/10.4028/www.scientific.net/amr.1098.37.

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In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

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23

Uddin, Md Jamil, Hadaate Ullah, and Mohammad Arif Sobhan Bhuiyan. "Fully Integrated K-Band Active Bandpass Filter In GPDK 90nm CMOS Technology." Carpathian Journal of Electronic and Computer Engineering 11, no. 1 (September 1, 2018): 3–6. http://dx.doi.org/10.2478/cjece-2018-0001.

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Abstract The bandpass filter is one of the essential blocks of every modern RF transceiver. Performance of the transceiver greatly depends on the performance of the bandpass filter. A bandpass filter designed with passive inductors suffers from some drawbacks like large chip size, low-quality factor, less tenability etc. To prevail over these constraints, an active inductor-based bandpass filter circuit has been designed in GPDK-90nm CMOS technology utilizing cadence virtuoso environment. The simulation result shows that the active inductor-based bandpass filter circuit design achieves a gain of 6.79dB, a bandwidth of 5.05 GHz and a noise figure of 3.10dB. The circuit dissipates only 3.55mW power for its operation from a single 1.5V DC supply. By avoiding bulky inductor in the design helped to attain a very small chip area of 127.704μm2.

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24

Singh, B. J. "Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology." CVR Journal of Science & Technology 7, no. 1 (December 1, 2014): 42–47. http://dx.doi.org/10.32377/cvrjst0607.

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25

Singh, B. J. "Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology." CVR Journal of Science & Technology 7, no. 1 (December 1, 2014): 42–47. http://dx.doi.org/10.32377/cvrjst0707.

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26

Vishwakarma, Ajay, Sweta Sahu, Vijay Vishwakarma, and Richa Soni. "Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology." International Journal of Computer Applications 63, no. 11 (February 15, 2013): 1–6. http://dx.doi.org/10.5120/10507-5381.

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27

Qian, Zhongling, Frank Siegelin, Birgit Tippelt, and Stefan Müller. "Localization and physical analysis of a complex SRAM failure in 90nm technology." Microelectronics Reliability 46, no. 9-11 (September 2006): 1558–62. http://dx.doi.org/10.1016/j.microrel.2006.07.020.

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28

Khatak, Anil, Manoj Kumar, and Sanjeev Dhull. "Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (December 1, 2018): 4922. http://dx.doi.org/10.11591/ijece.v8i6.pp4922-4931.

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To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

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29

PRASAD, M., U. B. MAHADEVASWAMY, and DANDAVATIMATH PRASHANT. "SQUARE ROOT CARRY SELECT ADDER USING MTTSPC D-LATCH IN 90nm TECHNOLOGY." i-manager’s Journal on Electronics Engineering 9, no. 3 (2019): 14. http://dx.doi.org/10.26634/jele.9.3.15267.

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30

Inanlou, Reza, and Mohammad Yavari. "A simple structure for noise-shaping SAR ADC in 90nm CMOS technology." AEU - International Journal of Electronics and Communications 69, no. 8 (August 2015): 1085–93. http://dx.doi.org/10.1016/j.aeue.2015.04.006.

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31

Zhao, Xiao Feng, Dian Zhong Wen, Cui Cui Zhuang, Bing Han, Yue Li, Jing Ya Cao, and Lei Li. "Fabrication and Characteristics of the Nano-Polysilicon Thin Film Transistors." Key Engineering Materials 562-565 (July 2013): 13–17. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.13.

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In this paper, we report the fabrication and characteristics of the top-gated thin film transistors (TFTs) with nanopolysilicon as active layers. The nanopolysilicon thin films were deposited on SiO2 layers by LPCVD and the SiO2 layers were grown on the single silicon substrates. Then the nanopolysilicon thin film transistors with different thin film thicknesses and different channel width length radios were fabricated by CMOS technology, in which the thicknesses of channel layers were 90nm and 120nm, and the channel width length radios were 160μm/160μm, 320μm/160μm and 640μm/160μm, respectively. The experiment results show that drain current is in proportion to channel width length radio. In addition, when the thickness of the nanopolysilicon thin film is 90nm and the channel width length radio is 640μm/160μm, the on/off current radio reaches 106.

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32

Awang Salleh, Dayang Nur Salmi Dharmiza, and Rohana Sapawi. "A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes." Applied Mechanics and Materials 833 (April 2016): 135–39. http://dx.doi.org/10.4028/www.scientific.net/amm.833.135.

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Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

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33

K. M, Rohith Prasad. "IC Layout Design of Carry Lookahead Adder at 90nm Technology using GNU/Electric." International Journal for Research in Applied Science and Engineering Technology 6, no. 5 (May 31, 2018): 1804–8. http://dx.doi.org/10.22214/ijraset.2018.5294.

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34

Zhu, Zhong Ying, Hui Hong, and Shi Liang Li. "A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology." Applied Mechanics and Materials 513-517 (February 2014): 4572–75. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4572.

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A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09mV.

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35

ChandGupta, Dinesh, and Ashish Raman. "Analysis of Leakage Current Reduction Techniques in SRAM Cell in 90nm CMOS Technology." International Journal of Computer Applications 50, no. 19 (July 31, 2012): 18–22. http://dx.doi.org/10.5120/7910-1150.

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36

Vanak, Amin, and Reza Sabbaghi-Nadooshan. "Improvement of Power and Performance in NAND and D-Latch Gates Using CNFET Technology." Journal of Nano Research 33 (June 2015): 126–36. http://dx.doi.org/10.4028/www.scientific.net/jnanor.33.126.

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In this paper, low power and high speed D-latch and nand gates (as sample of combinational and sequential circuits) are designed based on cnfet and cmos technology. The performance of D-latch and nand is compared in two technologies of 65nm and 90nm in cmos and cnfet technology. The circuit designs are simulated using hspice. Finally, the power consumption and delay and pdp as well as rise and fall time are compared in various voltages and frequencies. The results show that cnfetD-latch and nand gates have better delay and power consumption in comparison to cmos technology.

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37

Jang, Seong-Yong, Jong-Kwan Shin, Hyuk-Min Kwon, Sung-Kyu Kwon, Seung-Yong Sung, Sun-Man Hwang, Jae-Hyung Jang, Ga-Won Lee, and Hi-Deok Lee. "Analysis of Quality factor and Effective inductance of Inductor for RF Integrated Circuits in 90nm CMOS Technology." Journal of the Institute of Electronics Engineers of Korea 50, no. 5 (May 25, 2013): 128–33. http://dx.doi.org/10.5573/ieek.2013.50.5.128.

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38

Mirhosseini, S. Hassan, and Ahmad Ayatollahi. "Design a 10-Bit 100MHz pipelined ADC using RB-OTA in 90nm CMOS technology." IEICE Electronics Express 9, no. 8 (2012): 815–21. http://dx.doi.org/10.1587/elex.9.815.

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39

A S, Madhukumar, and M. Nagabhushan. "Design and Implementation of less quiescent current, less dropout LDO Regulator in 90nm Technology." International Journal of Engineering Trends and Technology 23, no. 8 (May 25, 2015): 379–85. http://dx.doi.org/10.14445/22315381/ijett-v23p272.

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40

Kaplon, J., and M. Noy. "Front end electronics for silicon strip detectors in 90nm CMOS technology: advantages and challenges." Journal of Instrumentation 5, no. 11 (November 30, 2010): C11024. http://dx.doi.org/10.1088/1748-0221/5/11/c11024.

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41

Moulahcene, Fateh, Nour-Eddine Bouguechal, Imad Benacer, and Saleh Hanfoug. "Design of CMOS Two-stage Operational Amplifier for ECG Monitoring System Using 90nm Technology." International Journal of Bio-Science and Bio-Technology 6, no. 5 (October 31, 2014): 55–66. http://dx.doi.org/10.14257/ijbsbt.2014.6.5.07.

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42

Sharma, Sandesh, and Vangmayee Sharda. "Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 759. http://dx.doi.org/10.14419/ijet.v7i3.12.16496.

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Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less complex than circuits designed by other techniques.

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43

Kaleeswari, B., and S. Kaja Mohideen. "Design, Implementation and Analysis of 8T SRAM Cell in Memory Array." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 101. http://dx.doi.org/10.14419/ijet.v7i3.1.16808.

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In modern VLSI designs, static random access memory plays a vital role because of its high performance and low power consumption qualities. As technology is scale down, the importance of the power analysis and leakage current of memory design is increasing. This paper describes about the 1 KB size memory design using SRAM. The proposed design of 8T SRAM single cell in implemented in array structure of size 32x32.The design structure reduces the power by 75% by reducing the leakage current. The proposed 8T SRAM cell is implemented and analyzed in 90nm technology using Digital schematic and Micro wind software.

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S.Aswale, P., and S. S. Chopade. "A Low Power 90nm Technology based CMOS Digital Gates with Dual Threshold Transistor Stacking Technique." International Journal of Computer Applications 59, no. 11 (December 18, 2012): 47–52. http://dx.doi.org/10.5120/9596-4215.

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Yadav, Poonam, and Rajesh Mehra. "Implementation of Current Reuse Structure in LNAUsing 90nm VLSI Technology for ISM Radio Frequency System." International Journal of Engineering Trends and Technology 33, no. 5 (March 25, 2016): 223–27. http://dx.doi.org/10.14445/22315381/ijett-v33p244.

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Pierobon, L., S. Bonacini, F. Faccio, and A. Marchioro. "Single-event upset sensitivity of latches in a 90nm dual and triple well CMOS technology." Journal of Instrumentation 6, no. 12 (December 6, 2011): C12011. http://dx.doi.org/10.1088/1748-0221/6/12/c12011.

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Kavali, Krishna, S. Rajendar, and R. Naresh. "Design of Low Power Adaptive Pulse TriggeredFlip-Flop Using Modified Clock Gating Schemeat 90nm Technology." Procedia Materials Science 10 (2015): 323–30. http://dx.doi.org/10.1016/j.mspro.2015.06.063.

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Pirovano, A., F. Pellizzer, I. Tortorelli, A. Riganó, R. Harrigan, M. Magistretti, P. Petruzza, et al. "Phase-change memory technology with self-aligned μTrench cell architecture for 90nm node and beyond." Solid-State Electronics 52, no. 9 (September 2008): 1467–72. http://dx.doi.org/10.1016/j.sse.2008.04.031.

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Pournoori, N., and E. Abiri. "A 0.7-v, 1.9mw integrator based on self-biased digital inverter in 90nm cmos technology." Trakia Journal of Science 12, no. 4 (2014): 449–54. http://dx.doi.org/10.15547/tjs.2014.04.016.

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Liu Fan-Yu, Liu Heng-Zhu, Liu Bi-Wei, Liang Bin, and Chen Jian-Jun. "Effect of doping concentration in p+ deep well on charge sharing in 90nm CMOS technology." Acta Physica Sinica 60, no. 4 (2011): 046106. http://dx.doi.org/10.7498/aps.60.046106.

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