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Journal articles on the topic 'A capacitance-to-voltage converter and a comparator'

Author: Grafiati

Published: 9 September 2021

Last updated: 29 July 2025

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1

WAWRYN, KRZYSZTOF, ROBERT SUSZYNSKI, and BOGDAN STRZESZEWSKI. "A LOW POWER DIGITALLY ERROR CORRECTED 2.5 BIT PER STAGE PIPELINED A/D CONVERTER USING CURRENT-MODE SIGNALS." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 29–43. http://dx.doi.org/10.1142/s0218126611007050.

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This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 μm technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mod

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2

Kulikov, V. A., V. N. Syakterev, and V. V. Syaktereva. "Application of Passive Time-to-Pulse Converter in Temperature Measurement Systems of Moving Objects." Intellekt. Sist. Proizv. 20, no. 4 (2022): 9–19. http://dx.doi.org/10.22213/2410-9304-2022-4-9-19.

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A variant of the implementation of a time-to-pulse converter as part of a human temperature measurement system is considered, in which a first-order circuit forming an information time interval is formed by a resistance temperature device and a capacitor. Initialization and registration of the time for the transient phenomena are carried out by MIS transistor and an integral comparator. Assessment of the differential sensibility of the converter depending on the time constant of the forming circuit for medium-speed keys is provided. The scheme of a multichannel converter is presented, with seq

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3

He, Xinyuan, Weifeng Qiao, Xinpeng Xing та Haigang Feng. "A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor". Journal of Low Power Electronics and Applications 14, № 2 (2024): 32. http://dx.doi.org/10.3390/jlpea14020032.

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A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achi

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4

M., Zahangir, Khan Sheroz, Adam I., Abdul Kadir K., N. Nordin A., and N. Ibrahim S. "A Proposed Resistance-to-Time Converter with Switching Impulse Calibrators for Application in Resistive Bridge Sensors." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 47–50. https://doi.org/10.11591/ijeecs.v11.i1.pp47-50.

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This paper presents a simple resistance-to-time converter. It consists of two voltage comparators, a ramp voltage generator, two logic gates and impulse voltage calibrators. A square-wave generator circuit is suggested in this paper. The design is simple and independent of the OPAMP offset issues. The resulting square-wave is rectified to get its DC equivalent and to a triangular output; the two outputs are applied to a comparator for generating a digital output with a duty cycle proportional to a change in resistance upon which is dependent the DC.

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5

Julie, Roslita Rusli, Shafie Suhaidi, Mohd Sidek Roslina, Abdul Majid Hasmayadi, Z. Wan Hassan W., and Mustafa M.A. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 17, no. 2 (2020): 783–92. https://doi.org/10.11591/ijeecs.v17.i2.pp783-792.

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 1

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6

Liu, K., S. Fang, Y. Wang, and Z. Huang. "Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones." Journal of Physics: Conference Series 2740, no. 1 (2024): 012044. http://dx.doi.org/10.1088/1742-6596/2740/1/012044.

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Abstract A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hi

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7

Priya, Nadendla Bindu, and Muralidharan Jayabhalan. "A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 41–43. http://dx.doi.org/10.35940/ijeat.a1012.1291s519.

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Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5-bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Th

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8

Roslita Rusli, Julie, Suhaidi Shafie, Roslina Mohd Sidek, Hasmayadi Abdul Majid, W. Z. Wan Hassan, and M. A. Mustafa. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science 17, no. 2 (2020): 783. http://dx.doi.org/10.11591/ijeecs.v17.i2.pp783-792.

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The

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9

Gwóźdź, Michał. "Power Electronics Programmable Voltage Source with Reduced Ripple Component of Output Signal Based on Continuous-Time Sigma-Delta Modulator." Energies 14, no. 20 (2021): 6784. http://dx.doi.org/10.3390/en14206784.

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In this work, an idea of a wideband, precision, power electronics programmable voltage source (PVS) is presented. One of the basic elements of the converter, the control section, contains a continuous-time sigma-delta modulator (SDM) with a pair of interconnected complementary comparators, which represents a new approach. In this case, the SDM uses comparators with a dynamic hysteresis loop (DHC) that includes an AC circuit rather than an R-R network. Dynamic hysteresis is a very effective way of eliminating parasitic oscillation during the signal transition at the input of the comparator; it

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10

Faure, Nicolaas, and Saurabh Sinha. "High-speed Cherry Hooper flash analog-to-digital converter." Microelectronics International 34, no. 1 (2017): 22–29. http://dx.doi.org/10.1108/mi-08-2015-0075.

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Purpose The 60 GHz unlicensed band is being utilized for high-speed wireless networks with data rates in the gigabit range. To successfully make use of these high-speed signals in a digital system, a high-speed analog-to-digital converter (ADC) is necessary. This paper aims to present the use of a common collector (CC) input tree and Cherry Hooper (C-H) differential amplifier to enable analog-to-digital conversion at high frequencies. Design/methodology/approach The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain b

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11

Kim, Young-Kyu, Chung-Hee Jang, Dong-Hyun Shin, and Kwang-Hyun Baek. "A Comparator-Less Buck Converter with Fast Transient Response Using a Reactive Ramp Generator." Energies 18, no. 2 (2025): 307. https://doi.org/10.3390/en18020307.

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This paper introduces a voltage-mode DC-DC buck converter designed to address the challenges of high-frequency operation. The proposed comparator-less Reactive Ramp Generator (RRG) topology mitigates the issues associated with comparator delays, achieving a fast load transient response. By eliminating all comparators from the buck converter’s control circuit, we prevent potential delay-induced malfunctions, thereby enhancing overall operational reliability. The rapid response of the RRG, enabled by a short feedback loop, allows for swift output voltage regulation during load transients. Replac

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12

Zahangir, M., Sheroz Khan, I. Adam, K. Abdul Kadir, A. N. Nordin, and S. N. Ibrahim. "A Proposed Resistance-to-Time Converter with Switching Impulse Calibrators for Application in Resistive Bridge Sensors." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 47. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp47-50.

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This paper presents a simple resistance-to-time converter. It consists of two voltage comparators, a ramp voltage generator, two logic gates and impulse voltage calibrators. A square-wave generator circuit is suggested in this paper. The design is simple and independent of the OPAMP offset issues. The resulting square-wave is rectified to get its DC equivalent and to a triangular output; the two outputs are applied to a comparator for generating a digital output with a duty cycle proportional to a change in resistance upon which is dependent the DC.

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13

Grishin, M. V., A. V. Leonov, and A. A. Kucobin. "Metrological support of digital electronic voltage transformers and low-power voltage transformers." Izmeritel`naya Tekhnika, no. 9 (October 17, 2023): 46–52. http://dx.doi.org/10.32446/0368-1025it.2023-9-46-52.

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Metrological support of digital electronic voltage transformers and low-power voltage transformers (sensors) is represented. The methods and reference measuring instruments of the State primary special standard of units of the ratio error and the phase displacement of AC electric voltage of power frequency in the range from to and units of electric capacitance and tangent of loss dissipation factor at AC voltage of power frequency in the range from 1 to 500 kV – GET 175-2023, used for metrological support of the measuring instruments mentioned above. The results of research of GET 175-2023 are

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14

Jung, Inseok, Kyung Ki Kim, and Yong-Bin Kim. "A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC." Journal of Integrated Circuits and Systems 10, no. 3 (2015): 187–200. http://dx.doi.org/10.29292/jics.v10i3.422.

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This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The contro

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15

Wang, Chua-Chin, Tzung-Je Lee, Chi-Chen Li, and Ron Hu. "Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator." Microelectronics Journal 38, no. 2 (2007): 197–202. http://dx.doi.org/10.1016/j.mejo.2006.11.018.

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16

Ishrat, Zahan Mukti, Rahman Khan Ebadur, and Kumar Biswas Koushik. "1.8-V Low Power, High-Resolution, High-Speed Comparator with Low Offset Voltage Implemented in 45nm CMOS Technology." International Journal of Innovative Science and Research Technology 7, no. 12 (2022): 183–87. https://doi.org/10.5281/zenodo.7471024.

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This paper presents the design of a comparator with low power, low offset voltage, high resolution, and rapid speed. The designed comparator is built on 45 𝑛𝑚 flip CMOS technology and runs 4.2 𝐺 samples per second at nominal voltage. It is a custom-made comparator for a highly linear 4-bit Flash A/D Converter (ADC). The outlined design can operate on a nominal supply of 1.8 V. The comparator offset voltage was elevated because of this mismatch. To compensate for the offset voltage, we followed a decent approach to design the circuits. Therefore, the offset voltage is reduced to 250𝜇𝑉. The desi

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17

Harada, Yujiro, Kuniaki Fujimoto, Mitsutoshi Yahara, and Kei Eguchi. "A Study on Flash Type A/D Converter Using Neuron CMOS Inverter." Advanced Materials Research 931-932 (May 2014): 915–19. http://dx.doi.org/10.4028/www.scientific.net/amr.931-932.915.

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In this paper, we propose a flash type A/D (Analog-to-Digital) converter. This circuit uses a neuron CMOS inverter as a judgement component of the voltage level. It is smaller than traditional analog comparators in the power consumption and the layout area. Therefore, the power consumption and the layout area of this circuit can be reduced further compared with the conventional A/D converter using the analog comparator. Furthermore, we could confirm that the proposed circuit has a characteristic of high-speed operation.

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18

Lakshmi N, Dr. Pavithra G, and Dr. T.C.Manjunath. "Design Of Three Stage Comparator Using 90nm Technology." international journal of engineering technology and management sciences 7, no. 6 (2023): 40–43. http://dx.doi.org/10.46647/ijetms.2023.v07i06.008.

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In this paper, the design of three stage comparator using 90nm technology is presented. The comparator is one of the block that limits the speed of the converter, its optimization is crucial and important and design of Analog-to-Digital Converter (ADC),is the speed limiting element in comparator. It describes the schematic design of a three stage CMOS comparator to achieve lower power dissipation and a lower offset voltage, with high-speed operation. Test structure of the comparator are designed using GPDK 90nm. The three-stage comparator makes it possible to use NMOS input pairs in both the r

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19

HUANG, GUANZHONG, and PINGFEN LIN. "A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350017. http://dx.doi.org/10.1142/s0218126613500175.

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A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of fe

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20

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (2022): 716–23. https://doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm complementary metal-oxide semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when

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21

Silpa, Kesav Velagaleti, K. S. Nayanathara, and B. K. Madhavi. "A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system." TELKOMNIKA Telecommunication, Computing, Electronics and Control 19, no. 2 (2021): pp. 547~555. https://doi.org/10.12928/TELKOMNIKA.v19i2.18318.

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In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch

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22

Lee, Chan-Soo, Munkhsuld Gendensuren, Bayarsaikan Dansran, Bierng-Chearl Ahn, and Seong-Gon Choi. "Integrated 0.35-µm CMOS Control Circuits for High-Performance Voltage Mode DC–DC Boost Converter." Electronics 12, no. 1 (2022): 133. http://dx.doi.org/10.3390/electronics12010133.

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The integrated DC–DC converter is appropriate for use in many domains, namely, display, cellular, and portable applications. This paper presents an integrated control circuit for a monolithic voltage mode DC–DC boost converter for display driver applications. The control circuits consist of a transconductance amplifier, a comparator, and an oscillator. The boost converter consists of an inductor, two MOSFET, and an output RC filter. The control circuits are designed for fast transient response and low output ripple. The transconductance amplifier, comparator, and oscillator in the control circ

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Jendernalik, W. "On analog comparators for CMOS digital pixel applications. A comparative study." Bulletin of the Polish Academy of Sciences Technical Sciences 64, no. 2 (2016): 271–78. http://dx.doi.org/10.1515/bpasts-2016-0030.

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Abstract Voltage comparator is the only - apart from the light-to-voltage converter - analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based

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Ahmed, Gulrej, and Rajendra Kumar Baghel. "A Variable Threshold Voltage CMOS Comparator for Flash Analog to Digital Converter." International Journal of Computer Applications 88, no. 7 (2014): 40–43. http://dx.doi.org/10.5120/15367-3874.

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25

Kamal, Nur Zazmera Mustafa, Nabihah Ahmad, Siti Hawa Ruslan, et al. "Design voltage comparator 14-bit for successive approximation analog-to-digital converter." Journal of Physics: Conference Series 1529 (May 2020): 052100. http://dx.doi.org/10.1088/1742-6596/1529/5/052100.

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26

Kulikov, V. A., V. N. Syakterev, V. V. Syaktereva, and D. M. Varlamova. "Multichannel Generator Time-To-Pulse Converter of the Telemetry Temperature Measurement System." Intellekt. Sist. Proizv. 21, no. 2 (2023): 110–20. http://dx.doi.org/10.22213/2410-9304-2023-2-110-120.

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The article considers the multichannel time-to-pulse intermediate converter as a part of telemetric temperature measurement system. The principle of operation is based on the use of aperiodic transient in a first-order circuit formed by resistance temperature device and capacitor. Switching of resistance temperature device in the process of temperature measurements is carried out by MIS keys (metal-insulator-semiconductor) according to the signal from the output of the circuit, and the allocation of the output information interval is carried out by a voltage comparator. The article illustrates

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27

Zghoul, Fadi Nessir, Wafaa Migdadi, and Mamoun Al-Mistarihi. "Optimizing power consumption in novel electrical design for single ended comparator circuit." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 1 (2025): 208–23. https://doi.org/10.11591/ijece.v15i1.pp208-223.

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Contemporary society electronic technology has evolved into a pivotalcomponent across various facets of our lives. Its indispensability isparticularly evident in the advancement of medical, agricultural, industrial,and other sectors. As this technology continues to play a crucial role,optimizing its performance in terms of speed, accuracy, and energyconsumption becomes paramount. This paper introduces a novel electricaldesign for the threshold inverter quantization comparator circuit aiming tomeet the evolving demands of modern electronic applications. The proposeddesign enhances the classic t

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Wahyudi, Muhammad Prihadi Eko, Qoriatul Fitriyah, and Novie Ayub Windarko. "System Design of Three Phases Six Legs DC/DC Converter for Solar Cell." JURNAL INTEGRASI 13, no. 2 (2021): 93–96. http://dx.doi.org/10.30871/ji.v13i2.2024.

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this paper describes the design of full bridge DC to DC converter 3 phase six legs for solar PV. The prototype is built with 5 kHz transformers, 2 lead-acid batteries with each energy storage of 12V, 7.2Ah and 20WP solar PV. Three phase switching is provided by analog op-amp comparator circuit with variable frequency 1 kHz-20 kHz. The controller of the converter use adjustable DC power supply as voltage reference for analog op-amp comparator, works varies from 0-11VDC (0%-50% duty cycle) and controlled manually

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29

Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

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This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversi

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Ninic, Marko, and Radivoje Djuric. "A novel high efficiency CMOS RF/DC power harvester based on constant on/off time buck controller for 60GHz frequency band." Serbian Journal of Electrical Engineering 14, no. 1 (2017): 133–48. http://dx.doi.org/10.2298/sjee1701133n.

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A novel 60 GHz RF/DC power harvesting system is presented. The system consists of RF to DC rectifier and a DC/DC Buck converter based on constant ON/OFF time (COOT) control. The rectifier has a structure of voltage doubler, but employs diodes that have lower parasitics compared to those of the standard MOSFET diodes, resulting in improved power conversion efficiency. The peak efficiency of the rectifier obtained with the extracted parasitics for the output power of 1 mW is about 25%. In order to keep the output voltage of the system to 1.2 V, the COOT control in the Buck converter is used. COO

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Zhu, Zhong Ying, Hui Hong, and Shi Liang Li. "A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology." Applied Mechanics and Materials 513-517 (February 2014): 4572–75. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4572.

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A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09m

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Swilam, Muhammad, Mohamed El-Nozahi, and Emad Hegazi. "Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter." IEEE Transactions on Circuits and Systems II: Express Briefs 63, no. 1 (2016): 114–18. http://dx.doi.org/10.1109/tcsii.2015.2468930.

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Wang, Cheng, Zhanpeng Yang, Xinpeng Xing, Quanzhen Duan, Xinfa Zheng, and Georges Gielen. "A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing." Electronics 12, no. 19 (2023): 4062. http://dx.doi.org/10.3390/electronics12194062.

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This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator

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Chen, Yanbo, Qiong Nie, Chaowei Zhong, et al. "A 24 nW 10-bit 10 kS/s ultra-low-power SAR ADC for biomedical devices." AIP Advances 13, no. 2 (2023): 025351. http://dx.doi.org/10.1063/5.0138835.

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This paper proposed an ultra-low-power successive approximation register analog to digital converter (ADC) for medical implant devices. To reduce power consumption, the novel techniques presented in this paper are a tri-state capacitor unit, a novel switch scheme, and a new low static power comparator. Tri-state capacitor unit reduces down power without the use of middle voltage reference. The proposed switch scheme can complete the most-significant bit 3-bit conversion without any power consumption. The offset of the low static power comparator is only optimized by physical design. This ADC i

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Hu, Xiaohui, Wanyuan Qu, Xu Yang, and Yong Ding. "A Tight Load Regulation Hysteretic Boost Converter with Compact and Energy-Efficient Anti-Phase Emulated Current Control." Electronics 13, no. 23 (2024): 4855. https://doi.org/10.3390/electronics13234855.

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This paper presents a novel, compact, and energy-efficient hysteretic boost converter that employs an anti-phase AC-coupling emulate current control. The proposed scheme utilizes a two-transistor current emulator and a comparator, which allow for fast transient responses and tight closed-loop regulations. This converter was fabricated using a 180 nm CMOS process and was capable of regulating a 5 V output with a 400 mA load capacity from an input voltage range of 2.7 V to 4.5 V. The experimental results demonstrate that the proposed anti-phase AC-coupling emulate current controlling and single

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Sai Lakshmi, Taninki, Avireni Srinivasulu, and Pittala Chandra Shaker. "Implementation of Power Efficient Flash Analogue-to-Digital Converter." Active and Passive Electronic Components 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/723053.

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An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and

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Valaee, Ali, and Mohammad Maymandi-nejad. "An ultra low-power low-voltage switched-comparator successive approximation analog to digital converter." IEICE Electronics Express 6, no. 15 (2009): 1098–104. http://dx.doi.org/10.1587/elex.6.1098.

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Adhithya, M. "An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (2024): 1364–68. http://dx.doi.org/10.22214/ijraset.2024.59057.

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Abstract: Technological innovations in the current century period have motivated professionals to make electronic gadgets smarter. These advancements are progressing at a brisk pace, facilitating faster changes and increase in computing power. Various technologies such as virtual reality, augmented reality, mobile internet, artificial intelligence, cloud computing, biometric devices, 3D printing machines, genomics, quantum computing, block-chain, industrial automation and robotics. In all these technologies, communications with nearby devices play a major role in its effective functioning. The

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Sajja, Amrita, and S. Rooban. "Design of Low Power SAR ADC with Novel Regenerative Comparator." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (December 31, 2023): 166–72. http://dx.doi.org/10.37394/23201.2023.22.19.

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This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded c

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Krishna K, Lokesh, Srinivasulu Reddy D, and Chandrasekhar Rao T. "A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures." International Research Journal of Multidisciplinary Scope 05, no. 01 (2024): 42–49. http://dx.doi.org/10.47857/irjms.2024.v05i01.0133.

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With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture

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Rezapour, Arash, Farbod Setoudeh, and Mohammad Bagher Tavakoli. "Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology." Journal of Applied Engineering Sciences 9, no. 2 (2019): 169–76. http://dx.doi.org/10.2478/jaes-2019-0023.

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Abstract This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the amplifier is not used at the first stage and the buffer is used for data transfer to the second stage, in the second stage an amplifier circuit with accurate gain of 8 that is open loop with a new structure was used to speed up, also the design is such that the first 4 bits are extracted s

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INANLOU, REZA, and MOHAMMAD YAVARI. "A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 02 (2014): 1450026. http://dx.doi.org/10.1142/s0218126614500261.

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In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digita

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Woong Park, Jung, Munkhsuld Gendensuren, Ho-Yong Choi, and Nam-soo Kim. "Integrated high voltage boost converter with LC filter and charge pump." Microelectronics International 31, no. 1 (2013): 54–60. http://dx.doi.org/10.1108/mi-05-2013-0023.

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Purpose – The paper aims to design of dual-mode boost converter with integrated low-voltage control circuit is introduced in this paper. The paper aims to discuss these issues. Design/methodology/approach – The converter is operated either with LC filter or with charge pump circuit by the switch control. The control stage with error amplifier, comparator, and oscillator is designed with the supply voltage of 3.3 V and the operating frequency of 5.5 MHz. The compensator circuit exploits a pole compensation for a stable operation. Findings – The simulation test in 0.35 μm CMOS process shows that

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Zhang, Huaxia, Yuewen Sun, Zijia Chen, and Zhifang Wu. "Design of a Nanosecond Voltage Comparator with PECL Logic for a Photon-Counting Radiation Imaging System Application." Science and Technology of Nuclear Installations 2023 (July 8, 2023): 1–12. http://dx.doi.org/10.1155/2023/6810882.

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In this paper, a nanosecond voltage comparator with PECL logic for a photon-counting radiation imaging system is presented. To realize a high-speed comparison of four gamma detector channels in a limited board space, quad comparators MAX9602 with PECL logic are chosen. Each of the four channels is coupled with a PECL to CMOS converter ICS508, which exports CMOS logic data for later use in an FPGA. Simulated findings for cobalt-60 with intensities ranging from 30 Ci to 300 Ci show little count loss caused by using a comparator and indicate ideal propagation delays at all source intensities. Whi

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Stoyanov, Svilen Hristov. "Researching the change of the operating frequencies in the case of inequality of the output voltages of the comparator within the structure of an integrating measuring strain gauge converter." ANNUAL JOURNAL OF TECHNICAL UNIVERSITY OF VARNA, BULGARIA 1, no. 1 (2017): 97–104. http://dx.doi.org/10.29114/ajtuv.vol1.iss1.45.

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One of the major errors directly influencing the metrological characteristics of the integrating measuring strain gauge converter is the inequality of the output voltages of the comparator. The current paper explores the effect of the voltages variation at the output of the comparator in the case of a bipolar power supply of the converter. The output data is obtained by modeling the equation of conversion in the MATLAB environment. The fore-mentioned problem is investigated assuming up to 20% inequality of the output voltages compared to the supply voltage and a bilateral change of the load on

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Liu, Lianxi, Yanbo Pang, Xufeng Liao, Zhangming Zhu, and Yintang Yang. "A Power-Enhanced Active Rectifier with Offset-Controlled Comparator for Self-Powered PEH Systems." Journal of Circuits, Systems and Computers 27, no. 05 (2018): 1850079. http://dx.doi.org/10.1142/s0218126618500792.

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In this paper, a power-enhanced active rectifier with high precision of current detection for piezoelectric energy harvesting (PEH) system is presented. A traditional two-stage active rectifier is adopted, which includes a first-stage negative voltage converter and an active diode. A comparator with offset control technique is proposed; thus the input-referred offset voltage of the proposed comparator can be less than 1[Formula: see text]mV. The current detected accuracy of the proposed offset-controlled comparator (OCC) is improved by more than 10 times over a traditional comparator. Output o

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Keramida, Evi, George Souliotis, Spyridon Vlassis, and Fotis Plessas. "Buck-Boost Charge Pump Based DC-DC Converter." Journal of Low Power Electronics and Applications 13, no. 2 (2023): 27. http://dx.doi.org/10.3390/jlpea13020027.

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This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating the output voltage, respectively, compared to the input. To achieve each mode, only a switching of the input–output connections is needed without any other modification in the design of the DC-DC converter. The dual-mode configuration aims to merge two different functions into one circuit, minimizing the design time and the area the DC-DC converter occupies on the

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Gevorgyan, Vazgen S. "DRIVER OUTPUT IMPEDANCE CALIBRATION SYSTEM WITH COMPARATOR UNIT OFFSET CANCELLATION." Proceedings of the YSU A: Physical and Mathematical Sciences 55, no. 1 (254) (2021): 81–89. http://dx.doi.org/10.46991/pysu:a/2021.55.1.81.

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In modern integrated circuits, the channel length of the transistors is reduced, and the supply voltages are also reduced. But the threshold voltages of the transistors cannot be reduced so quickly due to the physical properties of the materials used, which decreases the operating range of the transistors and makes noises comparable to them. Therefore, it is necessary to eliminate the influence of noise sources in the circuits, in particular, reflections between the transmission line and the output of the transmitter. A system is proposed for calibrating the output impedance of the transmitter

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Ahmed, Gulrej, and Rajendra Kumar Baghel. "Design of 6-Bit Flash Analog to Digital Converter Using Variable Switching Voltage CMOS Comparator." International Journal of VLSI Design & Communication Systems 5, no. 3 (2014): 25–35. http://dx.doi.org/10.5121/vlsic.2014.5303.

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Rezvanyvardom, Mahdi, and Amin Mirzaei. "Analysis and Design of a New 10-Bit High Accuracy and Resolution TDC by Elimination of Offset Voltage and Parasitic Capacitors Effects." Journal of Circuits, Systems and Computers 28, no. 06 (2019): 1950095. http://dx.doi.org/10.1142/s0218126619500956.

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This paper investigates a time-to-digital converter (TDC) that employs interpolation and time stretching techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution. In the proposed TDC, interpolation is performed based on a dual-slope conversion. The proposed converter eliminates the comparator offset voltage error and the comparator parasitic capacitor error compared with the TDCs that have been proposed previously. The features of the converter consist of the high accuracy and high resolution due to elimination of errors and

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