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Dissertations / Theses on the topic 'A/D-converter'

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Published: 4 June 2021

Last updated: 26 July 2025

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1

Coady, Edmond Patrick. "Pipelined multi-step interpolating A/D converter." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36029.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.<br>Includes bibliographical references (p. 97-98).<br>by Edmond Patrick Coady.<br>M.S.

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2

Chew, Tung Shen. "A 19-bit monolithic charge-balancing A/D converter." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84880.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 93-94).<br>Existing high-resolution ADC topologies are expensive, complicated and vulnerable to switch leakage at high temperature. This thesis introduces the Modified Landsburg ADC, a high-resolution converter optimized for minimum cost and die area. Switch resistance cancellation, charge-injection compensation and auto-zero methods are used to build a simple and robust ADC which will op

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3

Lau, Yanlok Charlotte 1979. "A high-speed cascaded folding and interpolating A/D converter." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/29683.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.<br>Includes bibliographical references (p. 85-86).<br>The folding and interpolating technique has been introduced to CMOS analog-to- digital converter (ADC) in the 1980's. It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then a

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4

Kim, Jintae. "Multi-level design optimizations of pipelined A/D converter." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1790313751&sid=9&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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5

Öresjö, Per. "A High Speed Sigma Delta A/D-Converter for a General Purpose RF Front End in 90nm-Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8706.

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<p>In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.</p><p>The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.</p>

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6

Maňas, Stanislav. "Adaptabilní obrazový A/D převodník." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219829.

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Master's Thesis deals with the complete proposal of light adaptability A/D converter. In the second chapter there are describes types of sensors. Third one describes the most used methods of light adaptability. In the fourth chapter there is describe the adaptability A/D conversion. Chapter 5 describes the block diagram. In the sixth chapter there is the design of all blocks of A/D converter. Finally in the chapter 7 there are construction documents for realization.

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7

Zavari, Rod. "A high-speed CMOS A/D converter employing variable nonuniform quantization." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0024/MQ34143.pdf.

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8

Helble, Heiko. "Development of a CMOS A/D Converter for an Artificial Synapse." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11126491.

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9

Panáček, Jiří. "Měřicí pracoviště pro simulaci a testování převodníků AD a DA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218686.

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The objective of this thesis is a design of a development kit, which is used in laboratories during the lessons of Theory of analog to digital conversion subject. This device is adapted for basic measuring and understanding of digital to analog (D/A) and analog to digital (A/D) converters and contains sigma-delta A/D converter made of basic elements, D/A converter with R-2R resistor net, active low pass frequency filter (Sallen-Key), PWM generator, SAR A/D converter with 16 b resolution, reference voltage source and module for measuring integral and differential nonlinearity of A/D converters.

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10

Ertan, Sevgi 1976. "Comparison of two bandpass delta-sigma A/D converter architectures." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86435.

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11

Li, Jason C. (Jason Chianse). "Integration of an imaging system and A/D converter system." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/43381.

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12

Croughwell, Rosamaria. "A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter." Digital WPI, 2007. https://digitalcommons.wpi.edu/etd-theses/974.

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"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination â€˜splitâ€™ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The â€˜split ADCâ

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Karlsson, Magnus. "Direktsamplande digital transciever." Thesis, Linköping University, Department of Science and Technology, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1658.

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<p>Master thesis work at ITN (Department of Science and Technology) in the areas of A/D-construction and RF-circuit design. Major goal of project were to research suitable possibilities for implementations of direct conversion in transceivers operating in the 160MHz band, theoretic study followed by development of components in the construction environment Cadence. Suitable A/D- converter and other important parts were selected at the end of the theoretic study. Subsampling technique was applied to make A/D sample requirements more realistic to achieve. Besides lowering requirements on A/D-con

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Strážnický, Martin. "Univerzální převodník spojitých analogových signálů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2021. http://www.nusl.cz/ntk/nusl-442420.

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This work deals with the design of a galvanically isolated converter of continuous analog signals and the design of a galvanically separated converter of digital TTL signals to HTL signals. The device is complemented by a STM32 microprocessor, which ensures the connection of analog input and output. The result of the work is the circuit structure of individual units, the results of simulations of important units, complete data for the production of device and measured values of individual units.

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Bečková, Zuzana. "Návrh AD převodníku pro senzorové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242185.

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Diplomová práce obsahuje stručný teoretický základ pro designéra/ku A/D převodníku v technologii CMOS a přehled architektur A/D převodníků používaných v automobilovém průmyslu. Volba vhodné architektury pro konkrétní aplikaci byla zásadním úkolem zpra- covaným v semestrálním projektu předcházejícím tuto práci a je rovněž součástí této práce. Analýza v Matlabu, ze které by mělo vyplynout, je-li třeba zahrnout do architek- tury podblok Sample and Hold, je také součástí práce. Klíčovou částí práce je dokumen- tace návrhu jednotlivých podbloků A/D převodníku – operačního zesilovače, kompará- toru

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Štěpánek, Adam. "Návrh optického převodníku pro EMC." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-241949.

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Master's thesis is focused on designing optical converter for EMC measurement transfering signal through noisy enviroment. First part contains analysis of electromagnetic interference and its coupling and measurement, especially types of probes for interference maesurement. Next part passing through designing of optoelectric and electrooptic converter with digital intensity modulation. Last part is about realization of optical converter.

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Fox, Brian L. "Analysis and Dynamic Range Enhancement of the Analog-to-Digital Interface in Multimode Radio Receivers." Thesis, Virginia Tech, 1997. http://hdl.handle.net/10919/35868.

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The rapidly developing wireless market has spawned a multitude of different standards for cellular, PCS, and wireless data. To allow users the ability to access services conforming to disparate standards, multimode handsets capable of software reconfiguration are needed. These "software radios" are distinguished from their traditional counterparts by their strong reliance on digital channel filtering and demodulation which may be reprogrammed to receive different standards. In these radios, higher dynamic range is required from the analog portion, most notably, the analog-to-digital co

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Sen, Subhajit. "Design of sampling mixer and A/D converter for high IF digitization." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq22237.pdf.

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19

Asibal, Romeo Lim. "Limitations of high speed sigma-delta A/D converter in GaAs technology." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/15445.

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Wu, Lei. "Low-voltage pipeline A/D converter." Thesis, 1999. http://hdl.handle.net/1957/33270.

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Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their own limitations. Multi-threshold process increases cost. Boosted clock will cause life time reliability issues. Switched-opamp slows down the speed of operation. A new low-voltage SC technique without special process and

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21

Chang, Shan-Wen, and 張獻文. "Current-Mode Pipelined A/D Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/88821925942456651374.

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碩士<br>逢甲大學<br>電機工程所<br>91<br>In recent days, the CMOS digital integrated circuits have been successfully utilized in many applications. It is highly relied on the data converters to improve the overall systems performance. In this thesis, a current-mode pipelined A/D converter (IADC) without sample-and-hold circuit is designed and analyzed. In the IADC architecture, each 1-bit pipelined stage consists of current-mirror circuits, one current comparator, and delay elements. This architecture can achieve a very high conversion rate due to the lack of sample/hold circuit. From HSPICE simulation re

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Wu, Wen-Hsiang, and 吳文祥. "Pipelined A/D Converter Design Automation." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/6j64e5.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>97<br>Pipelined A/D converter Design Automation from system to circuit is presented inthis paper. The pipelined A/D converter design flow can be separated into the system and circuit level design. It often adopts Matlab Simulink for the system level design ,makes simulation modules to realize a current system and simulates non-idea effects.Besides, we used simulated annealing algorithm to find the system parameters out and to achieve design optimization.We utilizes circuit simulator like Cadence Spectre for the circuit level design,apples software Neocircuit to de

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Kuo, Chou-Ming, and 郭洲銘. "High speed and Low Power Digitalized A/D Converter and D/A Converter for Pulse Amplitude Modulation System." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/19844815888006200242.

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碩士<br>國立交通大學<br>電控工程研究所<br>98<br>In modern wire-line communication systems, the request for high speed data rate is growing. Pulse amplitude modulation(PAM) technique is a transmission technique which modulates digital data into analog amplitude. As an example of 16PAM, each voltage value represents four digital data. Under the same bandwidth limitation, PAM technique rises data rate as compared to binary transmission. In this thesis, our topic is to design high speed A/D converter and D/A converter for the transmitter(TX) and receiver(RX) for high speed pulse amplitude modulation systems. A b

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LU, ZHI-YU, and 盧志郁. "Successive bit-determination CMOS A/D converter." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/93872490363594438217.

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Shu, Jia-Kang, and 徐嘉康. "An A/D Converter for video application." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/94122454399098734573.

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碩士<br>國立東華大學<br>電機工程研究所<br>89<br>Abstract This paper describes the design of an analog to digital converter。 The ADC is based on the unified architecture。 A new sensing amplifier is introduced to remove pre-amplifier helping to reduce power consumption . It is a 8-bit ， 50Msample/s ADC， the reference voltage is between 1v to 2V The ADC has 15 comparators and a reference voltage generator， is simulated with the technology TSMC 1P4M .35um process 。The power consumption is 16mW 。

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Chang, Teng-Yu, and 張登裕. "Folding and Interpolating A/D Converter Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/73330365472364671679.

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碩士<br>國立清華大學<br>電子工程研究所<br>93<br>In this thesis, an 8-bit folding and interpolating analog-to-digital converter (ADC) that converts at 10 MHz is simulated and implemented in 0.35- m CMOS technology. The digital error correction and the decoder techniques by multiplexer are presented in this thesis. The principle of decoder and error correction technique are also discussed and analyzed in detail. The interpolating technique of preamplifiers reduces the power consumption and area. Also, the digital error correction technique increases the SNDR. As the differential-nonlinearity (DNL) and integral

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Chang, Kwen-Chi, and 張坤智. "The design of pipelined A/D converter." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/05662063408892724725.

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碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>Pipelined ADC is one of the advance high speed high resolution ADCarchitectures. Compared to other architectures used in similiar applications , it consumes lower power. One of its drawbacks is the difficulty of design due to its complexity of circuits.In this dissertation, a 10-bit pipelined ADC has been designed by theUMC 0.5um DPDM process. Simulation results show that it can work properlyat 10MSPS with the maximum error of 0.4LSB. Its power consumption

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Lu, Meng-Che, and 呂孟哲. "A/D Converter System For Biological Measurement." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/13979758481461083501.

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Bai, Tsung-Yi, and 白宗易. "Sliding Mode Analysis of a One-Bit A/D and D/A Converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/33651507085880724109.

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碩士<br>國立中興大學<br>電機工程學系所<br>99<br>The thesis studies the one-bit A/D and D/A converter. At first, we introduce the fundamental sampling and quantization theories. As the converter is nonlinear, we employ the variable structure control (VSC) method as the means for analysis and implementation of the one-bit A/D and D/A converter. The sliding mode is a special system behavior, in which an analog signal can be equivalent to an on-off sequence of a digital signal. Such a special behavior can be applied to the one-bit A/D and D/A converter. We also use the signal processing theory to show that the o

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Chen, I.-Ching, and 陳翊青. "A 1GS/s 6-bit 48mW A/D Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/82767730056775774882.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>95<br>A 1 GS/s 6-bit CMOS two-step ADC using fast-settling method and through timing rearrangement is demonstrated in a standard 0.13-μm CMOS process. The proposed method shortens the slew time of OPAMP in MDAC and the timing arrangement makes the circuits operated more efficient. The prototype circuit exhibits an INL of +0.3/-0.3 LSB and a DNL of +0.49/-0.49 LSB. The SNDR and SFDR achieve 31.3 and 49.2 dB at 1 GS/s for Nyquist input frequency. The ADC consumes 50 mW at 1.2V supply and occupies an active chip area of 0.16 mm2.

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Lo, Chieh-En, and 羅杰恩. "A Flash A/D Converter with Improved TIQ Comparator." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/46194597332126973020.

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碩士<br>國立彰化師範大學<br>積體電路設計研究所<br>99<br>In this thesis, we design a new 6-Bit flash analog to digital converter. It uses the Threshold Invert Quantization (TIQ) technology to replace traditional OPAMP comparator architecture to design a new TIQ comparator architecture, and it limits the current of the TIQ comparator when it is under transition. It could effectively reduce the overall circuit power consumption. The function and performance of the circuit was simulated by HSPICE utilizing TSMC 0.35 μm CMOS HSPICE model, and the power supply voltage is 3.3V. The 6-Bit TIQ flash analog to digital co

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Chen, I.-Ching. "A 1GS/s 6-bit 48mW A/D Converter." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1707200721424400.

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"Fault-tolerant round robin A/D converter system." Research Laboratory of Electronics, Massachusetts Institute of Technology, 1990. http://hdl.handle.net/1721.1/4191.

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Paul E. Beckmann and Bruce R. Musicus.<br>Includes bibliographical references (leaves 54-55).<br>Research supported in part by the Draper Laboratories. DL-H-404158 Research supported in part by a Rockwell Doctoral Fellowship. Research supported in part by the Advanced Research Projects Agency, monitored by the Office of Naval Research. N00014-89-J-1489

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Zheng, Ke Wei. "An efficient A/D converter using electronic neurons." Thesis, 2006. http://spectrum.library.concordia.ca/8714/1/MR14292.pdf.

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Analog to digital converter (ADC) is an important building block for modern electronic design. There exist different type of ADC, such as Integrating ADC; Successive approximation ADC; Flash ADC and so on. Each of them usually focuses on one or more design consideration. For example Flash ADC has high working frequency but it consume more power than other type of ADCs. We are also aware of that human brain works by receiving minute electrical information signals produced by nerve cells known as neurons. A neuron 'fires' (i.e., turns on) when it receives a stimulus of sufficient strength, and

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Lin, Ming-Tze, and 林明澤. "Configurable Dual-mode Low-distortion A/D Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/30256974193361942268.

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碩士<br>國立交通大學<br>電信工程系所<br>96<br>With the rapid growth in demand for multi-function device such as cellular phone and MP3 player, multi-function has become more and more important today. In today’s device application, digital circuits dominate the whole chip function. However, the analog-to-digital converter (ADC) is indispensable. The Sigma-delta modulation, associated with oversampling and noise shaping, is a well-known technique used in high-accuracy A/D converters. It is almost insensitive to component matching and variation and is suitable for today’s VLSI design. Concerning the two sigma-

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Chuang, Chao-Hsun, and 莊肇勳. "The Delta-Sigma D/A converter of FPGA." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/23097676004884092553.

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碩士<br>南台科技大學<br>電子工程系<br>99<br>The technique of low bandwidth, high resolution over-sampling interpolation delta-sigma modulator has been used extensively in digital to analog converter. The purpose of this thesis is to design a Delta-Sigma digital to analog converter which can be applied to voice signal. The architecture of this system is made up with an FIR filter and a 2nd order Delta-Sigma Modulator. This system focuses on the voice band signal with 10-bit digital data format, 20Hz to 3.4kHz frequency range, 8kHz input sampling rate and 32X over-sampling rate. The output is one digital bit

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Rengachari, Thirumalai. "A 10 bit algorithmic A/D converter for a biosensor." Thesis, 2004. http://hdl.handle.net/1957/28871.

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This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter needs only one op-amp, 4 comparators and 3 capacitors. Power reduction techniques are discussed with respect to the biosensor and the ADC. The ADC is designed for fabrication in a CMOS 0.18μm process.<br>Graduation date: 2004

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莊英傑. "A Nonlinear A/D Converter Design for CMOS Image Sensor." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/01548886882305031377.

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碩士<br>國立清華大學<br>電機工程學系<br>90<br>Advantage of CMOS image sensor such as high integration and low power makes this kind of image sensor have its position. But tradeoff between dynamic range and output swing is undesirable. In this thesis, a nonlinear A/D converter design for CMOS image sensor is described and designed with a 0.35 um 1P4M process. The nonlinear transfer function of the proposed A/D converter changes the resolution distribution of the output data, thereby improving the overall sensor’s resolution in low illumination and overcoming the effect of the sharp break point in the pixel c

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Teo, Yong-Tee, and 張永智. "A 14-bit High Speed Sigma-Delta D/A converter." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/49884866444282339476.

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碩士<br>國立成功大學<br>電機工程學系<br>88<br>In this thesis, an investigation of the design, analysis, and implementation of high-speed, high-resolution digital-to-analog (D/A) converter in standard CMOS technology is presented. A high speed sigma-delta D/A converter is divided into a digital part and an analog part. In order to reduce arithmetic complexity, half band interpolation FIR filter and multilper-free fourth-order multibit sigma-delta modulator with oversampling ratio of 12 are designed in digital part. The 4-bit output of this modulator is converted to analog signal by us

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Jiang, He-Tai, and 蔣和泰. "Design and Analysis of a 0.35um CMOS A/D Converter." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/19184932648429640664.

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碩士<br>國立交通大學<br>電子工程系<br>88<br>This thesis describes a 3.3V, 8-bit, 25Ms/s A/D converter. The input voltage range of this ADC is from 0V to 1V, and the reference voltages are 0V and 1V. The ADC is designed with the TSMC 1P4M 0.35um process. In the simulation result of HSPICE, it has achieved a resolution of 8-bit and the speed of 25Ms/s. The ADC is completely implement in a singal chip with the area about 1500x1600 micro-meter squares. The A/D converter is implement by the two-step architecture. The structure can be designed without either the high gain or a large output swing opera

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Wu, Yan-Huei, and 吳彥輝. "A Low Power All digital Parallel Architecture A/D Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/84162410019332805395.

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碩士<br>明新科技大學<br>電子工程研究所<br>102<br>In this thesis, a lowpower all digital parallel architecture analog-to-digital converter (ADC) using inverter matrix comparators are presented. The ADC circuit is composed of a clamp circuit, a sample hold circuit, a parallel inverter matrix comparator, and an encoder.In order to obtain simple configure of ADC, the traditional flash ADC usedoperational amplifiercomparators and the resistances are replaced by the parallelarchitecture of inverter matrix comparators. Therefore, the simple, rapid, and lowpower ADC is designed. Simulation results show that the ADCi

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Tzeng, Ruei-Shiuan, and 曾瑞鉉. "A Sigma-Delta Modulation Based BIST for A/D Converter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/c865bb.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>90<br>In this thesis, two built-in self test (BIST) methodologies have been developed to measure the four parameters of the A/D converters: offset error, gain error, integral nonlinearity error, and differential nonlinearity error. The first methodology can be used to test the A/D converter in a system-on-a-chip (SOC). A sigma-delta modulation based signal generator is designed to concurrently produce analog and digital sinusoidal signals on chip. By the sinusoidal histogram technique, the parameters can be extracted by the approximated equations. This structure h

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Cheng, Wei-Chih, and 鄭偉志. "A 1.2V High-Speed Single-Channel Pipelined A/D Converter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/14568343538106911897.

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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>The pipelined ADCs with the digital calibrations have been researched in recently years. In this thesis, a gain-error self-calibration technique is presented to allow low-gain operation amplifiers (opamps) to use in high-precision pipelined ADCs. The proposed technique reduces gain error by using a calibration capacitor array. It adjusts the feedback factor; therefore, the closed-loop gain is calibrated. In the circuit design, 39.1dB open-loop gain opamps can be used for a 10-bit pipelined ADC. Only 192 clock cycles are required for the proposed foreground self-

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Chen, Hong-Lin, and 陳泓霖. "A high-speed 6b Dynamic Folding Flash A/D Converter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/20908213357851215493.

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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>Communication in the unlicensed frequency band around 60GHz requires a very fast ADC with low resolution (4-7 bits). Flash ADC offers the highest sampling rate, which is adapted in these high speed applications such as radio astronomy, optical communication, magnetic and optical read channels, and ultra-wideband wireless receivers. In this paper, we propose a high-speed Dynamic Folding Flash A/D Converter. Use of folding the traditional flash analog to digital converter comparator required substantially reduce the number, it can reduce the power, dynamic power c

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Huang, Chun-Teng, and 黃俊騰. "Design of the Current-Mode Pipelined A/D Converter." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/44646987443123168743.

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碩士<br>國立中興大學<br>電機工程學系<br>88<br>In recent days, the CMOS digital integrated circuits have been successfully utilized in many applications. It is highly relied on the data converters to improve the overall systems performance. This thesis describes the design of a 10-bit, 50-MS/s CMOS current-mode pipelined analog to digital converter (ADC), which is suitable for high-speed applications, such as HDTV, video, communication, and medical imaging systems. The proposed ADC is based on an enhanced architecture, which adopts the parallelism way to improve conversion rate. Furthermore, using current mo

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Lan, Gen-Chyi, and 藍根琪. "Design and Implementation of CMOS SAR A/D Converter." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/92376047485746687979.

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Cheng, Chi-Jung, and 鄭棋榮. "Design of 16-b Current-Mode D/A Converter." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/07473999272200488803.

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碩士<br>義守大學<br>電子工程學系<br>92<br>A current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead is proposed in this thesis. This design takes advantage of the weighted-current-steering approach and the R-2R-ladder approach. The weighted-current-steering approach is used to implement the most-significant-bit stage while the R-R-ladder approach that is modified form the R-2R approach is used to implement the least-significant-bit stage. This converter was designed with a TSMC 0.18-m 1P6M CMOS process. The HSPICE simulation results show that this des

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呂啟彰. "The study of two-step flash A/D converter." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/98111192725799888374.

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Chen, Tsung-Huan, and 陳宗煥. "Successive Approximation Architecture for Low-Power A/D Converter." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10379417291187109746.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>97<br>Two successive approximation analog-to-digital converters are presented in this thesis. In the first architecture, a converter that meets the specification of HDTV system is implemented. We use simple boot-strapped technique in sample-and-hold to ensure the quality of sampled signal is above specification while still has sufficient bandwidth. Besides, both PMOS and NMOS are adopted in the input differential pairs of the comparator to guarantee the input signal range could reach rail-to-rail. The experimental results of the first converter, an 8-bit 54 MS/s S

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Li-Lung, Kao, and 高立龍. "An Improved Dual Mode, Dual Slope A/D Converter." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/75977393965652088566.

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碩士<br>國立交通大學<br>電子工程系所<br>96<br>This paper presents an integration improved dual-mode dual slope ADC. Based on this architecture, a new synchronous rectification circuit is proposed. Instead of full wave rectifier, an improved synchronous rectifier is implemented. To realize the simplified architecture, we use only one comparator, one OP, and switches. The advantage is that it could not only support wider bandwidth for AC signal measurements from 60 Hz to 100.2 kHz, but also provide DC signals’ digitization. It could be realized by even fewer chip area where by this dual-mode dual-slope ADC is

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