Relevant bibliographies by topics / Accelerated Processing Unit

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Accelerated Processing Unit'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Accelerated Processing Unit"

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Carpenter, Joel. "Graphics processing unit–accelerated holography by simulated annealing." Optical Engineering 49, no. 9 (2010): 095801. http://dx.doi.org/10.1117/1.3484950.

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Kang, Hoonjong, Fahri Yaraş, and Levent Onural. "Graphics processing unit accelerated computation of digital holograms." Applied Optics 48, no. 34 (2009): H137. http://dx.doi.org/10.1364/ao.48.00h137.

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Chapuis, Guillaume, Olivier Filangi, Jean-Michel Elsen, Dominique Lavenier, and Pascale Le Roy. "Graphics Processing Unit–Accelerated Quantitative Trait Loci Detection." Journal of Computational Biology 20, no. 9 (2013): 672–86. http://dx.doi.org/10.1089/cmb.2012.0136.

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Shaojing Li, Boris Livshitz, and Vitaliy Lomakin. "Graphics Processing Unit Accelerated $O(N)$ Micromagnetic Solver." IEEE Transactions on Magnetics 46, no. 6 (2010): 2373–75. http://dx.doi.org/10.1109/tmag.2010.2043504.

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Sunny Joseph, Ajai, and Elizabeth Isaac. "GPU Accelerated real-time Melanoma Detection." International Journal of Engineering & Technology 7, no. 3 (2018): 1208. http://dx.doi.org/10.14419/ijet.v7i3.13169.

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Melanoma is recognized as one of the most dangerous type of skin cancer. A novel method to detect melanoma in real time with the help of Graphical Processing Unit (GPU) is proposed. Existing systems can process medical images and perform a diagnosis based on Image Processing technique and Artificial Intelligence. They are also able to perform video processing with the help of large hardware resources at the backend. This incurs significantly higher costs and space and are complex by both software and hardware. Graphical Processing Units have high processing capabilities compared to a Central Processing Unit of a system. Various approaches were used for implementing real time detection of Melanoma. The results and analysis based on various approaches and the best approach based on our study is discussed in this work. A performance analysis for the approaches on the basis of CPU and GPU environment is also discussed. The proposed system will perform real-time analysis of live medical video data and performs diagnosis. The system when implemented yielded an accuracy of 90.133% which is comparable to existing systems.
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Said, Issam, Pierre Fortin, Jean–Luc Lamotte, and Henri Calandra. "Leveraging the accelerated processing units for seismic imaging: A performance and power efficiency comparison against CPUs and GPUs." International Journal of High Performance Computing Applications 32, no. 6 (2017): 819–37. http://dx.doi.org/10.1177/1094342017696562.

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Oil and gas companies rely on high performance computing to process seismic imaging algorithms such as reverse time migration. Graphics processing units are used to accelerate reverse time migration, but these deployments suffer from limitations such as the lack of high graphics processing unit memory capacity, frequent CPU-GPU communications that may be bottlenecked by the PCI bus transfer rate, and high power consumptions. Recently, AMD has launched the Accelerated Processing Unit (APU): a processor that merges a CPU and a graphics processing unit on the same die featuring a unified CPU-GPU memory. In this paper, we explore how efficiently may the APU be applicable to reverse time migration. Using OpenCL (along with MPI and OpenMP), a CPU/APU/GPU comparative study is conducted on a single node for the 3D acoustic reverse time migration, and then extended on up to 16 nodes. We show the relevance of overlapping the I/O and MPI communications with the computations for the APU and graphics processing unit clusters, that performance results of APUs range between those of CPUs and those of graphics processing units, and that the APU power efficiency is greater than or equal to the graphics processing unit one.
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Barca, Giuseppe M. J., Jorge L. Galvez-Vallejo, David L. Poole, Alistair P. Rendell, and Mark S. Gordon. "High-Performance, Graphics Processing Unit-Accelerated Fock Build Algorithm." Journal of Chemical Theory and Computation 16, no. 12 (2020): 7232–38. http://dx.doi.org/10.1021/acs.jctc.0c00768.

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Ni, Xiaolong, Zhi Liu, Chunyi Chen, et al. "Graphic processing unit accelerated real-time partially coherent beam generator." Optics and Lasers in Engineering 82 (July 2016): 62–69. http://dx.doi.org/10.1016/j.optlaseng.2016.02.005.

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Bouvier, Dan, Brad Cohen, Walter Fry, Sreekanth Godey, and Michael Mantor. "Kabini: An AMD Accelerated Processing Unit System on A Chip." IEEE Micro 34, no. 2 (2014): 22–33. http://dx.doi.org/10.1109/mm.2014.3.

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Gajic, Dusan, and Radomir Stankovic. "GPU accelerated computation of fast spectral transforms." Facta universitatis - series: Electronics and Energetics 24, no. 3 (2011): 483–99. http://dx.doi.org/10.2298/fuee1103483g.

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This paper discusses techniques for accelerated computation of several fast spectral transforms on graphics processing units (GPUs) using the Open Computing Language (OpenCL). We present a reformulation of fast algorithms which takes into account peculiar properties of transforms to make them suitable for the GPU implementation. A special attention is paid to the organization of computations, memory transfer reductions, impact of integer and Boolean arithmetic, different structure of algorithms, etc. Performance of the GPU implementations is compared with the classical C/C++ implementations for the central processing unit (CPU). Experiments confirm that, even though the spectral transforms considered involve only simple arithmetic, significant speedups are achieved by implementing the algorithms in OpenCL and performing them on the GPU.
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Dissertations / Theses on the topic "Accelerated Processing Unit"

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Tunbridge, Ian William. "Graphics processing unit accelerated coarse-grained protein-protein docking." Doctoral thesis, University of Cape Town, 2011. http://hdl.handle.net/11427/11670.

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Includes abstract.<br>Includes bibliographical references (leaves [187]-202).<br>In this work, we describe a Graphics processing unit (GPU) implementation of the Kim-Hummer coarse-grained model for protein docking simulations, using a Replica Exchange Monte-Carlo (REMC) method. Our highly parallel implementation vastly increases the size- and time scales accessible to molecular simulation. We describe in detail the complex process of migrating the algorithm to a GPU as well as the effect of various GPU approaches and optimisations on algorithm speed-up.
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Henderson, Drake Hall. "Accelerated partial window imaging in an integrated vision unit." Thesis, Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/16630.

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Dressler, Sven. "Simulation of Fibre Pull-out Using a Graphics Processing Unit Accelerated Discrete Element Model." Diss., University of Pretoria, 2020. http://hdl.handle.net/2263/75931.

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The combination of brittle material with ductile fibres can produce competent composites. The fibres transmit tensile forces across cracks that form in the brittle matrix at relatively low tensile strains. The fibre reinforcing, therefore, acts to both increase the maximum stress a structural section can support and improve the post maximum stress behaviour from brittle to ductile failure. An essential aspect of defining the effectiveness of fibre reinforcing is resolving the behaviour of the interface between the fibre and the matrix as the load being transmitted between the matrix and fibre increases. The interface behaviour for simple fibres is understood analytically, and several models exist that can predict the stresses in the interface. Numerical models using finite element methods (FEM) have been used to investigate this problem in a more general way. FEM, being inherently a description of a continuum, does not elegantly describe the debonding process that occurs during the debonding of fibres from the surrounding matrix. Discrete Element Methods (DEM) describe continuous and discontinuous materials as the interaction between multiple independent particles and are well suited for modelling fracture and evolving contacts. For this study two different DEM contact models are compared to investigate the model complexity that is required to describe fibre/matrix interface stresses and debonding accurately. A simple model (a linear spring model that only transmits normal and tangential forces) and a more complex model (parallel bonds which transmit normal and tangential forces, moments, and torsion) were used. Two stages of fibre pull-out were modelled independently using a GPU accelerated DEM simulator developed by the author: a fully bonded stage and the de-bonding stage. It was found that both models were able to simulate all stages when compared to analytical solutions. No improvement to the model behaviour was evident from using a complex contact model; for this reason, a simpler, faster contact model should be used to analyse this problem. The DEM code is written relying heavily on the Numba module which allows the compilation of Python syntax for execution on a GPU. Non-reversible bond damage is simulated, and each bond must, therefore, be stored and bond damage updated at each time step. The implementation of collision detection, particle force determination and equation of motion integration written for execution on GPU are discussed. The data structure and memory use are described. The method used to apply boundary conditions is described. The performance of the developed code is investigated by comparison with similar codes, using Numpy and Numba Python modules, written for serial execution on CPU only. It was found that the developed code was 1000 times faster than the Numpy+Python implementation and 4 times faster than the Numba+Python implementation for force determination and equation of motion integration. Collision detection was 900 times faster compared to Numpy+Python but performed slower compared to Numba+Python.<br>Dissertation (MEng)--University of Pretoria, 2020.<br>Mechanical and Aeronautical Engineering<br>MEng<br>Unrestricted
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Ting, Samuel T. "An Efficient Framework for Compressed Sensing Reconstruction of Highly Accelerated Dynamic Cardiac MRI." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1452164320.

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Kelly, Jesse. "Numerical solution of the two-phase incompressible navier-stokes equations using a gpu-accelerated meshless method." Honors in the Major Thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/1277.

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This item is only available in print in the UCF Libraries. If this is your Honors Thesis, you can help us make it available online for use by researchers around the world by following the instructions on the distribution consent form at http://library.ucf.edu/Systems/DigitalInitiatives/DigitalCollections/InternetDistributionConsentAgreementForm.pdf You may also contact the project coordinator, Kerri Bottorff, at kerri.bottorff@ucf.edu for more information.<br>Bachelors<br>Engineering and Computer Science<br>Mechanical Engineering
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Zhao, Kaiyong. "GPU accelerated sequence alignment /Zhao Kaiyong." HKBU Institutional Repository, 2016. https://repository.hkbu.edu.hk/etd_oa/378.

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DNA sequence alignment is a fundamental task in gene information processing, which is about searching the location of a string (usually based on newly collected DNA data) in the existing huge DNA sequence databases. Due to the huge amount of newly generated DNA data and the complexity of approximate string match, sequence alignment becomes a time-consuming process. Hence how to reduce the alignment time becomes a significant research problem. Some algorithms of string alignment based on HASH comparison, suffix array and BWT, which have been proposed for DNA sequence alignment. Although these algorithms have reached the speed of O(N), they still cannot meet the increasing demand if they are running on traditional CPUs. Recently, GPUs have been widely accepted as an efficient accelerator for many scientific and commercial applications. A typical GPU has thousands of processing cores which can speed up repetitive computations significantly as compared to multi-core CPUs. However, sequence alignment is one kind of computation procedure with intensive data access, i.e., it is memory-bounded. The access to GPU memory and IO has more significant influence in performance when compared to the computing capabilities of GPU cores. By analyzing GPU memory and IO characteristics, this thesis produces novel parallel algorithms for DNA sequence alignment applications. This thesis consists of six parts. The first two parts explain some basic knowledge of DNA sequence alignment and GPU computing. The third part investigates the performance of data access on different types of GPU memory. The fourth part describes a parallel method to accelerate short-read sequence alignment based on BWT algorithm. The fifth part proposes the parallel algorithm for accelerating BLASTN, one of the most popular sequence alignment software. It shows how multi-threaded control and multiple GPU cards can accelerate the BLASTN algorithm significantly. The sixth part concludes the whole thesis. To summarize, through analyzing the layout of GPU memory and comparing data under the mode of multithread access, this thesis analyzes and concludes a perfect optimization method to achieve sequence alignment on GPU. The outcomes can help practitioners in bioinformatics to improve their working efficiency by significantly reducing the sequence alignment time.
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Zhang, Chenggang, and 张呈刚. "Run-time loop parallelization with efficient dependency checking on GPU-accelerated platforms." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47167658.

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General-Purpose computing on Graphics Processing Units (GPGPU) has attracted a lot of attention recently. Exciting results have been reported in using GPUs to accelerate applications in various domains such as scientific simulations, data mining, bio-informatics and computational finance. However, up to now GPUs can only accelerate data-parallel loops with statically analyzable parallelism. Loops with dynamic parallelism (e.g., with array accesses through subscripted subscripts), an important pattern in many general-purpose applications, cannot be parallelized on GPUs using existing technologies. Run-time loop parallelization using Thread Level Speculation (TLS) has been proposed in the literatures to parallelize loops with statically un-analyzable dependencies. However, most of the existing TLS systems are designed for multiprocessor/multi-core CPUs. GPUs have fundamental differences with CPUs in both hardware architecture and execution model, making the previous TLS designs not work or inefficient when ported to GPUs. This thesis presents GPUTLS, a runtime system designed to support speculative loop parallelization on GPUs. The design of GPU-TLS addresses several key problems encountered when adapting TLS to GPUs: (1) To reduce the possibility of mis-speculation, deferred-update memory versioning scheme is adopted to avoid mis-speculations caused by inter-iteration WAR and WAW dependencies. A technique named intra-warp value forwarding is proposed to respect some inter-iteration RAW dependencies, which further reduces the mis-speculation possibility. (2) An incremental speculative execution scheme is designed to exploit partial parallelism within loops. This avoids excessive re-executions and reduces the mis-speculation penalty. (3) The dependency checking among thousands of speculative GPU threads poses large overhead and can easily become the performance bottleneck. To lower the overhead, we design several e_cient dependency checking schemes named PRW+BDC, SW, SR, SRW+EDC, and SRW+LDC respectively. (4) We devise a novel parallel commit scheme to avoid the overhead incurred by the serial commit phase in most existing TLS designs. We have carried out extensive experiments on two platforms with different NVIDIA GPUs, using both a synthetic loop that can simulate loops with different characteristics and several loops from real-life applications. Testing results show that the proposed intra-warp value forwarding and eager dependency checking techniques can improve the performance for almost all kinds of loop patterns. We observe that compared with other dependency checking schemes, SR and SW can achieve better performance in most cases. It is also shown that the proposed parallel commit scheme is especially useful for loops with large write set size and small number of inter-iteration WAW dependencies. Overall, GPU-TLS can achieve speedups ranging from 5 to 105 for loops with dynamic parallelism.<br>published_or_final_version<br>Computer Science<br>Master<br>Master of Philosophy
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Karri, Venkata Praveen. "Effective and Accelerated Informative Frame Filtering in Colonoscopy Videos Using Graphic Processing Units." Thesis, University of North Texas, 2010. https://digital.library.unt.edu/ark:/67531/metadc31536/.

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Colonoscopy is an endoscopic technique that allows a physician to inspect the mucosa of the human colon. Previous methods and software solutions to detect informative frames in a colonoscopy video (a process called informative frame filtering or IFF) have been hugely ineffective in (1) covering the proper definition of an informative frame in the broadest sense and (2) striking an optimal balance between accuracy and speed of classification in both real-time and non real-time medical procedures. In my thesis, I propose a more effective method and faster software solutions for IFF which is more effective due to the introduction of a heuristic algorithm (derived from experimental analysis of typical colon features) for classification. It contributed to a 5-10% boost in various performance metrics for IFF. The software modules are faster due to the incorporation of sophisticated parallel-processing oriented coding techniques on modern microprocessors. Two IFF modules were created, one for post-procedure and the other for real-time. Code optimizations through NVIDIA CUDA for GPU processing and/or CPU multi-threading concepts embedded in two significant microprocessor design philosophies (multi-core design and many-core design) resulted a 5-fold acceleration for the post-procedure module and a 40-fold acceleration for the real-time module. Some innovative software modules, which are still in testing phase, have been recently created to exploit the power of multiple GPUs together.
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Cheng, Wei-Hung. "MRI-Based Images Segmentation for GPU Accelerated Fuzzy Methods on Graphics Processing Units by CUDA." Kent State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=kent154349822159698.

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Lee, Junghee. "Many-core architecture for programmable hardware accelerator." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50319.

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As the further development of single-core architectures faces seemingly insurmountable physical and technological limitations, computer designers have turned their attention to alternative approaches. One such promising alternative is the use of several smaller cores working in unison as a programmable hardware accelerator. It is clear that the vast – and, as yet, largely untapped – potential of hardware accelerators is coming to the forefront of computer architecture. There are many challenges that must be addressed for the programmable hardware accelerator to be realized in practice. In this thesis, load-balancing, on-chip communication, and an execution model are studied. Imbalanced distribution of workloads across the processing elements constitutes wasteful use of resources, which results in degrading the performance of the system. In this thesis, a hardware-based load-balancing technique is proposed, which is demonstrated to be more scalable than state-of-the-art loadbalancing techniques. To facilitate efficient communication among ever increasing number of cores, a scalable communication network is imperative. Packet switching networks-on-chip (NoC) is considered as a viable candidate for scalable communication fabric. The size of flit, which is a unit of flow control in NoC, is one of important design parameters that determine latency, throughput and cost of NoC routers. How to determine an optimal flit size is studied in this thesis and a novel router architecture is proposed, which overcomes a problem related with the flit size. This thesis also includes a new execution model and its supporting architecture. An event-driven model that is an extension of hardware description language is employed as an execution model. The dynamic scheduling and module-level prefetching for supporting the event-driven execution model are evaluated.
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Book chapters on the topic "Accelerated Processing Unit"

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Lin, Yih-Chuan, and Shang-Che Wu. "An Accelerated H.264/AVC Encoder on Graphic Processing Unit for UAV Videos." In Computational Modeling of Objects Presented in Images. Fundamentals, Methods, and Applications. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54609-4_19.

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Li, Xiang, A. Grant Schissler, Rui Wu, Lee Barford, and Frederick C. Harris. "A Graphical Processing Unit Accelerated NORmal to Anything Algorithm for High Dimensional Multivariate Simulation." In 16th International Conference on Information Technology-New Generations (ITNG 2019). Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-14070-0_46.

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Mesicek, Jakub, Jan Zdarsky, Rafael Dolezal, Ondrej Krejcar, and Kamil Kuca. "Simulations of Light Propagation and Thermal Response in Biological Tissues Accelerated by Graphics Processing Unit." In Computational Collective Intelligence. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-45246-3_23.

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Tang, Wenwu. "Accelerating Agent-Based Modeling Using Graphics Processing Units." In Modern Accelerator Technologies for Geographic Information Science. Springer US, 2013. http://dx.doi.org/10.1007/978-1-4614-8745-6_9.

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Freytag, Gabriel, Philippe Olivier Alexandre Navaux, João Vicente Ferreira Lima, Lucas Mello Schnorr, and Paolo Rech. "Non-uniform Domain Decomposition for Heterogeneous Accelerated Processing Units." In High Performance Computing for Computational Science – VECPAR 2018. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-15996-2_8.

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Schütt, Ole, Peter Messmer, Jürg Hutter, and Joost VandeVondele. "GPU-Accelerated Sparse Matrix-Matrix Multiplication for Linear Scaling Density Functional Theory." In Electronic Structure Calculations on Graphics Processing Units. John Wiley & Sons, Ltd, 2016. http://dx.doi.org/10.1002/9781118670712.ch8.

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Reinders, James, Ben Ashbaugh, James Brodman, Michael Kinsner, John Pennycook, and Xinmin Tian. "Programming for GPUs." In Data Parallel C++. Apress, 2020. http://dx.doi.org/10.1007/978-1-4842-5574-2_15.

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Abstract Over the last few decades, Graphics Processing Units (GPUs) have evolved from specialized hardware devices capable of drawing images on a screen to general-purpose devices capable of executing complex parallel kernels. Nowadays, nearly every computer includes a GPU alongside a traditional CPU, and many programs may be accelerated by offloading part of a parallel algorithm from the CPU to the GPU.
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Andrade, Xavier, and Alán Aspuru-Guzik. "Application of Graphics Processing Units to Accelerate Real-Space Density Functional Theory and Time-Dependent Density Functional Theory Calculations." In Electronic Structure Calculations on Graphics Processing Units. John Wiley & Sons, Ltd, 2016. http://dx.doi.org/10.1002/9781118670712.ch10.

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Trefftz, Christian, Joseph Szakas, Igor Majdandzic, and Gregory Wolffe. "Accelerated Discovery of Discrete M-Clusters/Outliers on the Raster Plane Using Graphical Processing Units." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-01970-8_94.

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Bhargavi, K., and Sathish Babu B. "GPU Computation and Platforms." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8853-7.ch007.

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The GPUs (Graphics Processing Unit) were mainly used to speed up computation intensive high performance computing applications. There are several tools and technologies available to perform general purpose computationally intensive application. This chapter primarily discusses about GPU parallelism, applications, probable challenges and also highlights some of the GPU computing platforms, which includes CUDA, OpenCL (Open Computing Language), OpenMPC (Open MP extended for CUDA), MPI (Message Passing Interface), OpenACC (Open Accelerator), DirectCompute, and C++ AMP (C++ Accelerated Massive Parallelism). Each of these platforms is discussed briefly along with their advantages and disadvantages.
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Conference papers on the topic "Accelerated Processing Unit"

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Jia, Bin, Kui Liu, Khanh Pham, Erik Blasch, and Genshe Chen. "Accelerated space object tracking via graphic processing unit." In SPIE Defense + Security, edited by Khanh D. Pham and Genshe Chen. SPIE, 2016. http://dx.doi.org/10.1117/12.2224966.

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Delorme, Michael C., Tarek S. Abdelrahman, and Chengyan Zhao. "Parallel Radix Sort on the AMD Fusion Accelerated Processing Unit." In 2013 42nd International Conference on Parallel Processing (ICPP). IEEE, 2013. http://dx.doi.org/10.1109/icpp.2013.43.

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Lu, Tao, and Lu Peng. "BPU: A Blockchain Processing Unit for Accelerated Smart Contract Execution." In 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020. http://dx.doi.org/10.1109/dac18072.2020.9218512.

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Youness, Hassan, Mohamed Moness, Omar Shaaban, and Aziza I. Hussein. "Accelerated Processing Unit (APU) potential: N-body simulation case study." In 2016 11th International Conference on Computer Engineering & Systems (ICCES). IEEE, 2016. http://dx.doi.org/10.1109/icces.2016.7821983.

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Nguyen, Quang, Vinh Dang, and Ozlem Kilic. "Graphics processing unit accelerated Fast Multipole Method - Fast Fourier Transform." In 2013 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting. IEEE, 2013. http://dx.doi.org/10.1109/aps.2013.6711599.

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"On the efficiency of the Accelerated Processing Unit for scientific computing." In 2016 Spring Simulation Multi-Conference. Society for Modeling and Simulation International (SCS), 2016. http://dx.doi.org/10.22360/springsim.2016.hpc.040.

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Maroosi, Ali, and Ravie Muniyandi. "Accelerated P systems with active membranes on a graphics processing unit." In 2014 Asian Conference on Membrane Computing (ACMC). IEEE, 2014. http://dx.doi.org/10.1109/acmc.2014.7065803.

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Ashbach, Jason A., Xiande Wang, and Douglas H. Werner. "The finite element boundary integral method accelerated using a graphics processing unit." In 2013 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting. IEEE, 2013. http://dx.doi.org/10.1109/aps.2013.6711116.

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Huang, Yong, Xiao Lin, and Xiaodi Tan. "Graphics processing unit accelerated numerical model for collinear holographic data storage system." In SPIE OPTO, edited by Hans I. Bjelkhagen and V. Michael Bove. SPIE, 2017. http://dx.doi.org/10.1117/12.2251280.

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"EFFECTIVE AND ACCELERATED INFORMATIVE FRAME FILTERING IN COLONOSCOPY VIDEOS USING GRAPHICS PROCESSING UNIT." In International Conference on Bio-inspired Systems and Signal Processing. SciTePress - Science and and Technology Publications, 2011. http://dx.doi.org/10.5220/0003123401190124.

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