Academic literature on the topic 'Active clamp forward converter'

In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog CMOS process, and is fabricated at MOSIS. The design procedures of the ASIC chip are explained, and experimental results are presented. Part II of the thesis focuses on the numerical investigation of several integratable lateral power devices. Lateral power devices are used in power IC designs because of their compatibility with analog & digital IC process. To obtain devices with high current density, large safe operating area, fast response and low cost is highly desirable for power ICs. In Part II of this thesis, several lateral power devices are discussed and simulated, including lateral IGBT, lateral MCT and double gate lateral MCTs. It is shown that lateral IGBT and lateral MCTs are good candidates for power IC applications.<br>Master of Science

This thesis presents an active clamp forward converter for use in the Energy Harvesting From Exercise Machines project. Ideally, this converter will find use as the centerpiece in a process that links elliptical trainers to the California grid. This active clamp forward converter boasts a 14V-60V input voltage range and 150W power rating, which closely match the output voltage and power levels from the elliptical trainer. The isolated topology outputs 51V, higher than previous, non-isolated attempts, which allows the elliptical trainers to interact with a central grid-tied inverter instead of many small ones. The final converter operated at greater than 86% efficiency over most of the elliptical trainer’s input range, and produced very little noise, making it a solid choice for this implementation.

In this thesis<br>analysis, design and implementation of a DC-DC converter with active clamp forward topology is presented. The main objective of this thesis is generating a rectified sinusoidal voltage at the output of the converter. This is accomplished by changing the reference signal of the converter. The converter output is applied to an inverter circuit in order to obtain sinusoidal waveform. The zero crossing points of the converter is detected and the inverter drive signals are generated in order to obtain sinusoidal waveform from the output of the converter. Next, the operation of the DC-DC converter and sinusoidal output inverter coupled performance is investigated with resistive and inductive loads to find out how the proposed topology performs. The design is implemented with an experimental set-up and steady state and dynamic performance of the designed power supply is tested. Finally an evaluation of how better performance can be obtained from this kind of arrangement to obtain a sinusoidal output inverted is thoroughly discussed

The bi-directional dc/dc converter is a very popular and effective tool for alternative energy applications. One way it can be utilized is to charge and discharge batteries used in residential solar energy systems. In the day, excess power from the PV panels is used to charge the batteries. During the night, the charged batteries will power the dc bus for loads in the house such as home appliances. The dual active bridge (DAB) converter is very useful because of its high power capability and efficiency. Its symmetry is effective in transferring power in both directions. However, the DAB converter has drawbacks in the start-up stage. These drawbacks in boost mode include high in-rush current during start-up, and the fact that the high side voltage cannot be lower than the low side voltage. A popular existing method to alleviate this problem is the use of an active clamp and a flyback transformer in the circuit topology to charge the high side before the converter is switched into normal boost operation. The active clamp not only helps eliminate the transient spike caused by the transformer leakage, but also continues to be used during steady state. However, this method introduces a new current spike occurring when the converter transitions from start-up mode to boost mode. To alleviate this new setback, an additional transitional stage is proposed to significantly reduce the current spike without the use of any additional components. The converter is current-fed on the low side, and voltage-fed on the high side. A simple phase shift control is used in buck mode and PWM control is used during the boost mode for both the start-up mode and the normal boost operation. This thesis discusses the performance results of a 48-400 V dc/dc converter with 1000 W power output.<br>Master of Science

This work deals with theory of switched power sources. There is description of the ways for connection and their practice purposes. In the next parts there are defined requirements on input supply circuit for these sources, especially for the form of output current. There are mentioned the basic connecting methods of PFC circuits and these methods modify the output current to meet the requirements of specification ČSN EN 61000- 3- 2. In the next parts there are shown simulations of PFC circuits made by Pspice application. Further is the basic description of sources construction for the sources which were used for testing and measuring. The final part deals with evaluation of the measuring on the chosen computer’s source. It compares between the manufacturer’s solutions and PFC circuit made by ourselves.

碩士<br>國立臺灣科技大學<br>電子工程系<br>102<br>This thesis presents a single-stage AC-to-DC power converter, which consists of a boost-type power factor corrector (PFC) and a two-transformer active-clamp forward converter. The PFC stage adopts the voltage-follower control under discontinuous conduction mode. It helps reduce the volume of the boost inductor. The current control loop is not required to reduce the circuit design complexity. By utilizing separate transformers, the proposed converter features zero-voltage switching and good line regulation over a wide range of the input voltage. The output power can be shared by two transformers to reduce their volumes and the stresses of components at secondary side. This allows high power density design. The operating principle of this single-stage power converter has been analyzed, described and discussed in detail. The simulaton softwares, Mathcade and PSIM, are applied for circuit design. The experimental results with an input voltage of 115 Vac and an output of 19 V/140 W reveal a maximum efficiency of 85% and a maximum power factor of 0.99.

碩士<br>國立勤益科技大學<br>電子工程系<br>102<br>As the power transfer becomes more and more widely applied, the customers’ demands for the power efficiency, size and reliability becomes higher accordingly; however, the conventional forward diode rectifying converter can hardly meet the demands. 　　This paper adopts the active clamp structure to combine with auxiliary switches and clamper capacitance, which can effectively restrain the voltage transient and minimize the damages caused by switch changeover, as well as improve the converting efficiency. The capacity elements can operate a wider range of input voltage. In practice, the Pulse Width Modulation controller is used for the research on efficiency improvement of forward converter. From the experimental results, the methods proposed in the study have realized the improvement results.

碩士<br>國立臺灣科技大學<br>電子工程系<br>95<br>This thesis describes application of the active-clamp technique to achieve soft-switching for forward converters. For forward converters, the power switch causes high switching loss as the result of high current and high voltage generated during turn-on and turn-off periods. Generally, high switch loss hinders the improvement of efficiency and power density . In order to reduce switching loss, a resonant inductor is added in the primary side of the forward converter to form a resonant tank with the clamped capacitor. As the result, zero voltage switching (ZVS) for the main power switch can then be achieved to reduce the switching loss. In this thesis, the state-space averaging technique is used to describe the state equation. K factor is applied to design compensator and to greatly enhance the stability of the system so as to meet the requirements. Finally, IsSpice is conducted to simulate the dynamics of the converter. Based on the simulated result, a 120W forward converter with voltage clamp is built to verify with the theoretical analysis.

碩士<br>國立臺灣科技大學<br>電機工程系<br>97<br>A novel low input-current ripple topology named Active-Clamp Forward Converter with Current Ripple Reduction (ACFRR) is proposed in this thesis. In addition to having lower input current ripple and more than 50% duty cycle operation, the fundamental component intensity of the ACFRR’s input current waveform can be reduced by designing the circuit with its embedded filter. To demonstrate ACFRR’s feasibility, the operational principle, simulation and experimental results of the proposed converter operated at 150 kHz switching frequency, 36-75V input and 5V/30A output are presented and its highest efficiency is 84.88%. Moreover, the conversion efficiency of the ACFRR can be further improved by applying the synchronous rectification. According to the experimental results, the highest efficiency, 86.69% of the synchronous rectification ACFRR is achieved.

碩士<br>國立成功大學<br>電機工程學系碩博士班<br>93<br>This thesis mainly studies and implements two two-stage AC/DC power converters. The front-stage is a power factor correction circuit and the second-stage is a soft-switching DC/DC converter with synchronous rectifier. The DC/DC converter applies active clamp forward converter and asymmetrical half-bridge converter individually. These two circuits have similar zero-voltage-switching operating features, and the main circuit has the same number of components. A comparison between the two topologies is made in this thesis. The power consumption at no load condition can be reduced by disabling the power factor correction circuit and synchronous rectifier. In addition, the pulse skip scheme is used to reduce the losses of the converter at no load condition. Experimental results show that both these two prototypes can achieve 87% efficiency and 0.95 power factor at DC 12V/8A output condition.