Dissertations / Theses on the topic 'Active Front End Converters'

The dissertation presents a generalized average-current-mode control technique (GACMC), which is an extension of the average-current-mode control (ACMC) for single-phase ac-dc boost converters with power factor correction (PFC). Traditional ACMC is generalized in a sense that it offers improved performance in the form of significant reduction of the current control loop bandwidth requirement for a given line frequency in unidirectional and bidirectional boost PFC converters, and additional functionality in the form of reactive power control capability in bidirectional converters. These features allow using a relatively low switching frequency and slow-switching power devices such as insulated-gate bipolar transistors (IGBTs) in boost PFC converters, including those designed for higher ac line frequencies such as in aircraft power systems (360â 800 Hz). In bidirectional boost PFC converters, including multilevel topologies, the GACMC offers a capability to supply a prescribed amount of reactive power (with leading or lagging current) independently of the dc load power, which allows the converter to be used as a static reactive power compensator in the power system.

A closed-loop dynamic model for the current control loop of the boost PFC converter with the ACMC has been developed. The model explains the structure of the converter input admittance, the current phase lead phenomenon, and lays the groundwork for development of the GACMC. The leading phase admittance cancellation (LPAC) principle has been proposed to completely eliminate the current phase lead phenomenon and, consequently, the zero-crossing distortion in unidirectional converters. The LPAC technique has been adapted for active compensation of the input filter capacitor current in bidirectional boost PFC converters.

The dynamic model of the current control loop for bidirectional boost PFC converters was augmented to include a reactive power controller. The proposed control strategy enables the converter to process reactive power and, thus, be used as a reactive power compensator, independently of the converter operation as an ac-dc converter.

Multiple realizations of the reactive power controller have been identified and examined in a systematic way, along with their merits and limitations, including susceptibility to the ac line noise. Frequency response characteristics of reactive elements emulated by means of these realizations have been described.

Theoretical principles and practical solutions developed in this dissertation have been experimentally verified using unidirectional and bidirectional converter prototypes. Experimental results demonstrated validity of the theory and proposed practical implementations of the GACMC.
Ph. D.

University of Central Florida College of Engineering Thesis
Evolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding IGHz. New high performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/us slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response.
Ph.D.
Doctorate;
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering and Computer Science
124 p.
xii, 124 leaves, bound : ill. ; 28 cm.

The next generation High Energy Physics experiments require the development of novel radiation sensor technologies adequate to cover very large areas and suitable for extreme radiation conditions. In this field, thanks to its incomparable properties, silicon is still nowadays the dominant semiconductor used to build tracking detectors for ionizing particles. In several experiments all around the world, it is used to cover very large areas with the intent of tracking and identifying the crossing particles generated during the experiments. Different topologies of silicon sensors can be used for these applications but those commonly used for high rate environments are pixel sensors. This research activity focuses mainly on two particular types of these sensors: hybrid pixel sensors and monolithic active pixel sensors (MAPS). Modern detectors use intensively hybrid sensors due to their excellent properties. This technology indeed allows to develop sensor and electronics separately allowing a very effective optimization of each part of the device increasing in this way its versatility and allowing to meet most of the requirements of the new experiments. The hybrid technology is fast and also suitable for working in high radiation environments thanks to the use of high electrical fields for the charge collection. However, the production cost of those devices is much higher than other sensors because two different devices are required and also due to the additional cost for the bump bonding used to interconnect sensor and readout ASIC. On the other hand, monolithic sensors are based on the implementation of sensor and readout electronics in the same silicon wafer. Therefore this technology is much cheaper than the hybrid solution and allows to reduce significantly contribution of the detector to the material budget. However, traditional MAPS have some limitations in terms of speed, extension of the depletion volume, signal to noise ratio and radiation tolerance which make those devices unsuitable for the extreme environment of the new experiments. In this context, this work presents the development of a full depleted monolithic pixel sensor with a thickness of 300 μm which aims to overcome the main limitations of the conventional monolithics. The proposed device has properties similar to the hybrid solution but benefits of the low production cost typical of monolithics. The development of the device has been carried out by the collaboration between the University of Trento, INFN of Padova and INFN of Torino. In addition, thanks to the close collaboration with the experts of a silicon foundry, it was possible a tailored fabrication of the devices. Two ASICs of 2 mm × 2 mm have been developed in a customized double-sided CMOS technology with transistors of 1.2 V and 6 metal layers. The devices have been submitted to the foundry for fabrication on April 2016 and have been delivered for the testing phase on May 2017. A patent for the device has been granted in 2017. In the first part of this work, the state of the art of monolithics is given where hybrid and monolithics are compared. Then, the novel sensor is described in detail with the support of simulations to motivate important solutions adopted to reach the full depletion and to implement PMOS transistors avoiding the competitive charge collection. Some studies to highlight the huge limitations on design MAPS without access to the process data are presented to introduce the custom process used for the development of the device. The first ASIC is a test chip designed to contain test devices used to study important properties of the sensor like depletion and punch-through voltage. All the devices implemented in this ASIC are described in detail motivating the design solutions adopted. The second ASIC is the complete monolithic sensor called MATISSE (Monolithic AcTIve pixel SenSor Electronics) made by a matrix array of 24 × 24 pixels readout with the snapshot shutter technique. Each pixel is 50 μm×50 μm and is based on the same novel sensor. The chip is described in detail with the support of simulation results to motivate some strategies adopted during the design. Special emphasis is placed on the strategy used to design the readout chain with a wide output swing, low noise and excellent linearity with the use of high threshold transistors. Last but not least, in the last chapter the results collected during the characterization of the two prototypes for different wafers are presented. The data acquisition system developed is described and the electrical tests and measurements with active sources and lasers are reported. The measurements performed on the test structures show unwanted trapped charge in the backside oxide. The phenomenon is described putting special attention on an irradiation campaign performed in the test diodes to confirm and quantify this effect. All the results presented in this work aim to prove the device full depletion and the excellent properties of the embedded electronics implemented in these first prototypes.

The spread of renewable energy sources and electric vehicles is increasing thanks to the greater awareness of the climate problems due to the large and long-lasting use of the non-renewable energy sources. The integration of renewable energy sources to the power grid, however, poses significant technical challenges, since it drastically changes its topology and nature. In fact, while the traditional power generation system is centralized, the renewable energy is distributed and intermittent. In this scenario, power converters play a central role. Power converters are the technology that enables the interconnection of different players to the electric power system. In this work, a control system for grid-connected converters has been developed. The main focus is on the current control. The most renowned current controllers, such resonant and repetitive regulators, have been studied and tested in laboratory in order to compare the performance in terms of harmonic compensation and burden of the processor. The problem of the saturation of a multi-frequency current controller has been investigated and different saturation algorithms have been proposed. The power converters have, however, wide use and the same of the method, developed for grid-connected converters can be applied to electrical motor drives with open-end windings. If a floating capacitor bridge is connected to the secondary side of the open-end stator windings, it can supply the reactive power needed by the motor and completely exploit its current capability of the power source. This feature allows the drive to obtain higher torque at higher speed, increasing therefore the output power over all the flux-weakening speed range. The floating bridge, operating as harmonic compensator, allows the inverter connected to the primary energy source to work in overmodulation and even six-step modulation, in order to further boost the performance of the drive, without compromising the quality of the phase current.

The trend in isolated DC/DC bus converters is to increase the output power in the same brick form factors that have been used in the past. Traditional intermediate bus converters (IBCs) use silicon power metal oxide semiconductor field effect transistors (MOSFETs), which recently have reached the limit in terms of turn on resistance (RDSON) and switching frequency. In order to make the IBCs smaller, the switching frequency needs to be pushed higher, which will in turn shrink the magnetics, lowering the converter size, but increase the switching related losses, lowering the overall efficiency of the converter. Wide-bandgap semiconductor devices are becoming more popular in commercial products and gallium nitride (GaN) devices are able to push the switching frequency higher without sacrificing efficiency. GaN devices can shrink the size of the converter and provide better efficiency than its silicon counterpart provides. A survey of current IBCs was conducted in order to find a design point for efficiency and power density. A two-stage converter topology was explored, with a multiphase buck converter as the front end, followed by an LLC resonant converter. The multiphase buck converter provides regulation, while the LLC provides isolation. With the buck converter providing regulation, the switching frequency of the entire converter will be constant. A constant switching frequency allows for better electromagnetic interference (EMI) mitigation. This work includes the details to design and implement a hard-switched multiphase buck converter with planar magnetics using GaN devices. The efficiency includes both the buck efficiency and the overall efficiency of the two-stage converter including the LLC. The buck converter operates with 40V - 60V input, nominally 48V, and outputs 36V at 1 kW, which is the input to the LLC regulating 36V – 12V. Both open and closed loop was measured for the buck and the full converter. EMI performance was not measured or addressed in this work.
Master of Science

Front-end converters with power factor correction (PFC) capability are widely used in distributed power systems (DPSs). Most of the front-end converters are implemented using a two-stage approach, which consists of a PFC stage followed by a DC/DC converter. The purpose of the front-end converter is to regulate the DC output voltage, supply all the load converters connected to the distributed bus, guarantee current sharing, and charge a bank of batteries to provide backup energy when the power grid breaks down. One of the main concerns of the power supply industry is to obtain a front-end converter with a low-cost PFC stage, while still complying with required harmonic standards, especially for high-power three-phase applications. Having this statement in mind, the main objective of this dissertation is to study front-end converters for DPS applications with PFC to meet harmonic standards, while still maintaining low cost and performance indices. To realize the many aforementioned objectives, this dissertation is divided into two main parts: (1) two-stage front-end converters suitable for telecom applications, and (2) single-stage low-cost AC/DC converters suitable for mainframe computers and server applications. The use of discontinuous conduction mode (DCM) boost rectifiers is extensively explored to achieve simplicity, while reducing the cost for DPS applications. Interleaving of DCM boost rectifiers is also explored as an alternative approach to further reduce the system cost by reducing the filtering requirements. All the solutions discussed are implemented for 3kW applications, while 6kW is obtained by interleaving two converters.
Ph. D.

The research presented in this thesis leverages silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology to develop microwave front-end electronics for active phased-array antennas. The highly integrated electronics will reduce costs and improve the feasibility of snow measurements from airborne and space-borne platforms. Chapter 1 presents the motivation of this research, focusing on the technological needs of snow measurement missions. The fundamentals and benefits of SiGe HBTs and phased-array antennas for these missions are discussed as well. Chapter 2 discusses SiGe power amplifier design considerations for radar systems. Basic power amplifier design concepts, power limitations in SiGe HBTs, and techniques for increasing the output power of SiGe HBT PAs are reviewed. Chapter 3 presents the design and characterization of a robust medium power X-band SiGe power amplifier for integration into a SiGe transmit/receive module. The PA design process applies the concepts presented in Chapter 2. A detailed investigation into measurement-to-simulation discrepancies is outlined as well. Chapter 4 discusses the development and characterization of a single-chip X-band SiGe T/R module for integration into a very thin, lightweight active phased array antenna panel. The system-on-package antenna combines the high performance and integration potential of SiGe technologies with advanced substrates and packaging techniques to develop a high performance scalable antenna panel using relatively low-cost materials and silicon-based electronics. The antenna panel presented in this chapter will enable airborne SCLP measurements and advance the technology towards an eventual space-based SCLP measurement instrument that will satisfy a critical Earth science need. Finally, Chapter 5 provides concluding remarks and discusses future research directions.

Thesis (Sc. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992.
Includes bibliographical references (leaves 181-184).
by Loveday Haachitaba Mweene.
Sc.D.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Dr. Chang-Ho Lee, Committee Member ; Dr . Kevin T Kornegay, Committee Member ; Dr. Emmanouil M Tentzeris, Committee Member ; Dr. Joy Laskar, Committee Chair ; Dr. Oliver Brand, Committee Member.

One of the requirements for the next generation of power supplies for distributed power systems (DPSs) is to achieve high power density with high efficiency. In the traditional front-end converter based on the two-stage approach for high-power three-phase DPSs, the DC-link voltage coming from the power factor correction (PFC) stage penalizes the second-stage DC/DC converter. This DC/DC converter not only has to meet the characteristics demanded by the load, but also must process energy with high efficiency, high reliability, high power density and low cost. To meet these requirements, approaches such as the series connection of converters and converters that reduce the voltage stress across the main devices have been proposed. In order to improve the characteristics of these solutions, this dissertation proposes high-efficiency, high-density DC/DC converters for high-power high-voltage applications. In the first part of the dissertation, a DC/DC converter based on a three-level structure and operated with pulse width modulation (PWM) phase-shift control is proposed. This new way to operate the three-level DC/DC converter allows soft-switching operation for the main devices. Zero-voltage switching (ZVS) and zero-voltage and zero-current switching (ZVZCS) soft-switching techniques are studied, analyzed and compared in order to improve the characteristics of the proposed converter. This results in a series of ZVS and ZVZCS three-level DC/DC converters for high-power high-voltage applications. In all cases, results from 6kW prototypes operating at 100 kHz are presented. In addition, with the ultimate goal of improving the power density of the DC/DC converter, a study of several resonant DC/DC converters that can operate at higher switching frequencies is presented. From this study, a three-element ZVS three-level resonant converter for applications with wide input voltage and load variations is proposed. Experimental results at 745 kHz obtained without penalizing the efficiency of the PWM approaches are presented. The second part of the dissertation proposes a quasi-integrated AC/DC three-phase converter that aims to reduce the complexity and cost of the traditional two-stage front-end converter. This converter improves the complexity/low-efficiency tradeoff characteristics evident in the two-stage approach and previous integrated converters. The principle of operation for the converter is analyzed and verified on a 3kW experimental prototype.
Ph. D.

As wireless devices and radar systems become more ubiquitous, there is a growing need for wideband multi-standard RF-SOCs. To enable the advantages of multi-standard systems, reconfigurable RF front ends are needed. Because of the large number of RF signals in wideband systems, tunability and linearity become important parameters. Prior work has shown tunable LC filters to be advantageous in the microwave regime. A balanced-to-unbalanced (balun) transformation circuit is required to support the differential nature of a tunable LC filter. An active balun that also performs as a transconductor to drive the LC tank would relax the design requirement for the LNA and remove a passive balun that would have to precede the LNA. This thesis discusses the linearization of active baluns and presents a comparison between two 4 to 7 GHz tunable BPF designs with active baluns implemented in 0.18 SiGe BiCMOS technology. Fourth order filtering is achieved by subtracting two order LC-tanks. This approach allows 3- dB bandwidth to be tunable from 10% to 20%. In each design, a linearized input active balun is employed to drive the LC-tanks from a single-ended input while preserving noise figure and IIP3 performance. Two different linearization techniques are applied for the balun designs. Simulated NF ranges from 7.5 to 13 dB and IIP3 averages about 5 dBm with the peak value of 21 dBm.
Master of Science
As wireless devices and radar systems become more ubiquitous, there is a growing need for Radio Frequency (RF) integrated circuits that can support multiple frequency bands and standards. Because of the large number of RF signals, robust tunability and power handling of the electronics become important parameters. Power handling is important because the amplifier and the filter can generate distortions if the power going through them becomes too high. Prior work has shown integrated tunable inductor-capacitor (LC) resonance based filters to be advantageous in the microwave frequency regime compared to integrated switched capacitor based filters. A balancedto-unbalanced (balun) conversion of the RF signals is needed to support the differential nature of the LC resonators. This thesis discusses transistor-based balun designs that can be integrated into front-end LC filter chips. The goal is to reduce distortion in the filter under the present of large number of RF signals and to keep noise of the circuit in reasonable range. The designs are implemented in 0.18 SiGe BiCMOS integrated circuit technology and simulated in commercial computer aided design software; predicted performance is competitive with the state of the art. The fabricated chips will be characterized in future work.

This dissertation presents a comprehensive design and analysis framework for system-on-a-chip analog-to-digital conversion design. The design encompasses a broad class of systems, which take advantage of system-on-a-chip complexity. This class is exemplified by an interferometric photodetector array based bio-optoelectronic sensor that is built and tested as part of the reported work. While there have been many discussions of the technical details of individual analog-to-digital converter (ADC) schemes in the literature, the importance of the analog front-end as a pre-processor for a data converter and the generalized analysis including converter encoding and decoding functions have not previously been investigated thoroughly, and these are key elements in the choice of converter designs for low-noise systems such as bio-optoelectronic sensors. Frequency domain analog front-end models of ADCs are developed to enable the architectural modeling of ADCs. The proposed models can be used for ADC statistically worst-case performance estimation, with stationary random process assumptions on input signals. These models prove able to reveal the architectural advantages of a specific analog-to-digital converter schemes quantitatively, allowing meaningful comparisons between converter designs. The modeling of analog-to-digital converters as communication channels and the ADC functional analysis as encoders and decoders are developed. This work shows that analog-to-digital converters can be categorized as either a decoder-centered design or an encoder-centered design. This perspective helps to show the advantages of nonlinear decoding schemes for oversampling noise-shaping data converters, and a new nonlinear decoding algorithm is suggested to explore the optimum solution of the decoding problem. A case study of decoder-centered and encoder-centered data converter designs is presented by applying the proposed theoretical framework. The robustness and flexibility of the resulting analog-to-digital converters are demonstrated and compared. The electrical and optical sensitivity measurements of a fabricated oversampling noise shaping analog-to-digital converter circuit are provided, and a sensor system-on-a-chip using these ADCs with integrated interferometric waveguides for bio-optoelectronic sensing is demonstrated.

Afin de réaliser un appareil innovant pour la mesure de gaz polluants, la société SVS@CAP s’est associée avec le laboratoire de physique corpusculaire en 2009 pour la création du projet EREBUS. Ce projet a pour but la réalisation d’un ensemble de dispositifs sans fil permettant d’effectuer une surveillance de la concentration de gaz polluants. L’autonomie et la compacité d’un tel dispositif étant essentielles, la problématique principale porte sur la réduction de la consommation. A partir d’une première étude menée sur les différentes technologies existantes, les capteurs électrochimiques ont été identifiés comme les moins consommateurs d’énergie. Pour chacun des gaz cibles, un modèle électrique du capteur associé a été déterminé. A partir de ces modèles, une architecture dédiée et épurée a pu être déduite. Pour atteindre et même dépasser les objectifs de consommation, les efforts ont aussi été portés sur un dimensionnement avec la méthode gm/id. La réalisation de cette électronique intégrée a permis d’atteindre une consommation de l’ordre du μW pour chaque voie de mesure. Enfin, pour compléter la chaîne de lecture, plusieurs architectures de convertisseurs ont été étudiées et réalisées pour fonctionner à des fréquences déchantillonnage proches du Hz. Les consommations obtenues pour les convertisseurs sont limitées avec comme ordre de grandeur la centaine de nW
In order to realize an innovative product for pollutants in the atmosphere, SVS@CAP company started in 2009 the EUREBUS project in collaboration with the "Laboratoire de Physique Corpusculaire". The aim of this project is to design a wireless equipement to measure gas concentrations. The key issues of this project are concerning the autonomy as well as the small size of the product. In consequence an integrated and low power electronics remains essential. From a first study of the existing technologies to detect gaz concentrations, electrochemical sensors were selected because of their low power consumption. For each of the target gas, an electrical model was determined. From those models, a specific architecture was designed. A special effort was made on the energy consumption thanks to the use of the gm/id methodology which was necessary to achieve and exceed the specifications. The final order of the power consumption of the front-end developped and realized is around the μW. Finally, in order to complete the chain of acquisition, some architectures of analog to digital converter were studied, developped and realized with sample frequencies close to the Hz. The power consumptions of the converters developped are limited to the order of the hundreds of nW

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo.
The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

In this thesis the design, control, stability, input power quality, and motor drive performance of ac motor drives with front end three phase diode rectifiers utilizing low capacitance dc bus capacitor are investigated. Detailed computer simulations of conventional motor drives with diode rectifier front end utilizing high capacitance dc bus capacitor and the drives with low capacitance dc bus capacitor are conducted and the performances are compared. Performance evaluation of various active control methods found in previous studies aiming to provide the dc bus stability of drives with low capacitance dc bus capacitor are done at various load levels and types. Design recommendations are provided for the drives utilizing low capacitance dc bus capacitor.

L’évolution des différentes générations de systèmes de télécommunications cellulaires a entraîné une complexité du frontal des terminaux mobiles caractérisés notamment par la multiplication des chaînes RF qui le constituent. Chaque chaîne est dédiée à un standard, ce qui n’est pas optimale ni du point de vue du coût, ni de l’encombrement. Afin d’optimiser les performances et la consommation du transmetteur radiofréquence, l’approche retenue dans cette thèse consiste à concevoir de façon globale différents blocs afin de partager les contraintes. Dans cette thèse, l’approche globale de la co-conception est organisée en deux sous études. Celles-ci sont destinées à terme à être intégrées dans un même frontal RF entièrement configurable.La première étude aborde la problématique de la conception conjointe entre une antenne et un amplificateur de puissance (PA) qui sont traditionnellement conçus séparément. Nous avons tout d’abord déterminé les spécifications de l’antenne permettant de maximiser le transfert d’énergie entre ces deux blocs. Ensuite, nous avons conçu l’antenne en partageant les contraintes d’impédance à la fois dans la bande utile et aux harmoniques entre cette dernière et le PA afin de relâcher les spécifications sur le réseau d’adaptation d’impédance. Cette approche permet de maintenir la linéarité du PA à des niveaux de puissances supérieures par rapport au cas où l’antenne est adaptée sur 50 Ω.La seconde étude s’intéresse à la conception conjointe d’antennes et de composants agiles. Nous avons réparti l’effort de miniaturisation et les pertes ohmiques associées entre la structure d’antenne et le composant agile (capacité commutable numériquement). Les développements présentés se sont appuyés sur des simulations électromagnétiques, des modélisations, des caractérisations système (linéarité et temps de commutation) et des mesures en rayonnement (efficacité) de prototypes d’antennes miniatures dans les bandes basses 4G. Nos études ont abouti à la conception d’une antenne fente reconfigurable fonctionnant sur la bande instantanée maximale autorisée par la 4G. Pour une intégration sur smartphone, l’élément rayonnant n’occupe que 18 x 3 mm2 de surface soit λ_0/30×λ_0/180 à 560 MHz. La fréquence de résonance de l’antenne varie entre 560 MHz et 1.03 GHz et l’efficacité totale varie entre 50% et 4%. Un banc de mesure de la linéarité a été implémenté afin d’évaluer la linéarité des antennes agiles. La spécification de linéarité exigée par le standard est maintenu jusqu’à une puissance de 22 dBm
The recent development of cellular communication standards has led to an increasing RF front-end complexity due to the ever increasing number of RF needed paths. Each RF path is dedicated to a frequency bands group which might not be optimal for cost and occupied space area. Consequently, in order to optimize the RF performances and energy consumption, the approach used in this thesis is to share the constraints between the PA and the antenna of the front-end: this is called co-design. In this thesis, the considered co-design approach is twofold and in near future both results should be simultaneously considered and integrated into one fully reconfigurable RF front-end design.The first study addresses the co-design of an antenna and its associated power amplifier (PA), which are traditionally designed separately. We first determine the antenna impedance specifications to maximize the tradeoff between the energy transfer and PA linearity. Then, we propose to remove the impedance matching network between antenna and PA, while demonstrating that a low impedance antenna can maintain the RF performances. Contrarily to the classical approach where the antenna is matched to 50 Ω, the proposed co-design shows the possibility to keep the linearity of the PA even for high power levels (> 20 dBm).The second study focuses on the co-design of an antenna and tunable components. We are sharing the miniaturization effort and the resistive losses between the antenna structure and the tunable capacitor (DTC). The achieved developments are based on electromagnetic simulations, modeling, system characterization (linearity and switching time) and radiation measurements (efficiency) of miniature reconfigurable antenna prototypes in the 4G low bands. The considered studies have led to the design of a frequency reconfigurable antenna addressing the maximum instantaneous available bandwidth authorized by 4G. The radiator occupies only 18 x 3 mm2 (λ0/30 x λ0/180 at 560 MHz), and thus it is extremely suitable for a possible integration onto smartphones. The antenna resonance frequency is tuned between 560 MHz and 1030 MHz and the total efficiency varies between 50% and 4%. For the first time, the impact of SOI DTC implemented on the antenna radiating structure on linearity is measured with a dedicated test bench. The linearity specified by 4G is maintained up to 22 dBm of transmitted power

This research investigates the key characteristics of design leaders in the context of New Product Development (NPD) at the Fuzzy Front End (FFE) or early stage of this process. It particularly focuses on how design leaders communicate design to non-designers. It is often observed that designers struggle to communicate design to non-designers. Previous research has identified design leaders as competent design communicators. However, the definition and key characteristics of design leaders remain unclear. By reviewing the literature on leadership studies, design leadership and project leadership, it is evident that no single universal definition of leadership exists. The most common definition is that leaders apply their knowledge and skills to conduct activities and use their traits to influence other people’s actions. Leadership requires different characteristics for different tasks. To understand the characteristics of design leaders, triangulated research was employed at a real-life NPD project involving young designers and non-designers at early stages of NPD as part of the first study. All participants (N=32) were directly observed, interviewed in semi-structured interviews and administered with assistive questionnaires to compare design and non-design participants’ leadership and communication styles. The second study was in-depth, focusing on UK design leaders (N=11) through semi-structured interviews and based on deficiencies in leadership and communicating design, identified from the first study and the literature review. Comparative studies indicate that designers and design leaders vary their attitudes towards non-designers, motivation and communication style. This study highlights the key characteristics of design leaders: an epiphany by experiencing the entire NPD process, interest in the benefits of NPD stakeholders, a good understanding of design competency, reflectively flexible working attitude and strong, active listening. Thus, a conceptual model was formulated and evaluated, able to guide designers who wish to become design leaders and help to enhance design communication and relationships with non-designers.

ITER experiment will be built at Cadarache (France) and its main goal will be to prove the viability of fusion as an energy source. In a fusion reactor, the plasma (an ionized gas of Deuterium and Tritium) has to be heated up to temperatures of millions of Celsius degrees in order to sustain the fusion reaction. No materials are able to withstand these temperatures; therefore the plasma is kept away from the walls of the reactor vacuum vessel by means of appropriate magnetic fields, produced by the currents flowing in the superconducting coils, which interact with the charged particles of the plasma. Besides the ohmic heating, two additional sources are foreseen in ITER, based on radiofrequency electromagnetic waves and neutral beam injection. Two Neutral Beam Injectors (NBIs) will heat the plasma; each of them is based on five 200 kV stages in series accelerating negative ions of deuterium or hydrogen, which are neutralized and injected in ITER plasma. The high energy (1 MeV) and beam power (16.7 MW) make this design very complex, close to the state of the art of the components. The ac/dc conversion system necessary to supply the superconducting coils of the magnet system and the auxiliary systems (as the NBIs) may consume a total active and reactive power respectively up to 500 MW and 900 Mvar. In the past years many studies have been carried out on the ITER power supply system and its impact on the electrical network (called Pulsed Power Electrical Network PPEN). Several methods have been considered to improve the power factor, based both on Q reduction and compensation techniques. As for the first, sequential and asymmetric controls, with internal bypass or external freewheeling have been evaluated. Concerning the compensation approach, the current reference design is based on Static Var Compensation System with nominal power of 750 Mvar based on Thyristor Controlled Reactor (TCR) + Tuned Filter (as fixed capacitor). Nevertheless, studies are still in progress aimed to further improvements. This PhD thesis aims to investigate two topics related to the impact on the PPEN of the ITER power supply system with a novel approach. The former concerns the study of the stability of the PPEN and mainly aims to investigate interaction phenomena among the ac/dc conversion and Q compensation and filtering systems, due in particular to the relatively high power ratings and operating scenarios with significant power transients during the plasma pulses. It is not an easy task: the overall system is very complex, the numerical simulation of its operation via programs capable of reproducing the instantaneous current and voltage profiles requires very long calculation time and most of all it does not provide any sensitivity data concerning the stability of the whole power system. Therefore I have followed an analytical approach. The study took the starting points from the methods developed for the HVDC applications, which however can not be directly applied to the ITER case; therefore I have developed specific analytical models. The former model is a Quasi Static Model, which aims to evaluate the strength of the electrical network feeding the ITER power supply system by sensitivity analysis. I have derived the equations of the model by the power flow equations as a function of some relevant parameters in order to carry out sensitivity analysis. This model allows the calculation of some indexes as the Critical Short Circuit Ratio (CSCR) and Voltage Sensitivity Factor (VSF). No critical conditions have been found. The latter is a Dynamic Model; it is based on the state space formulation and it aims to investigate the dynamic stability of the whole system, including also the control system. Nevertheless the ac/dc conversion and the TCR systems are non-linear and discrete, thus difficult to be modelled; therefore, taking the starting point from the methods described in literature, I have approximated the discrete phenomena by continuous transfer functions, and I have worked out the linearization around an equilibrium point such that the small signal analysis approach can be used. I have adopted a modular approach, developing an analytical Dynamic Model for each subsystem (Tuned Filters, TCR and ac/dc conversion system). Then I have built numerical models of the subsystems with a program (PSIM) capable to reproduce the instantaneous waveforms for the validation of the analytical Dynamic Models (run in Matlab Simulink program, state space tool) in frequency and time domain by a comparison between the simulation results. Finally I have built the Dynamic Model of the whole system and validated by comparison with the PSIM one. From the results of the frequency analysis, the dynamic model is accurate for frequency range less than 50 Hz, but it may be used to obtain some insight about the system stability also for frequency range up to 100 Hz. Some unstable operating conditions have been discovered, and the cause has been identified due to resonance between the tuned filters and the grid. It is highlighted that this model may be easily implemented with more detail to the whole ITER power supply system and it can be a very useful and fast tool to aid the design of the power supply system and set the parameters of the control system. As the second topic of my PhD thesis, I have studied the feasibility of adopting a more advanced technology based on the Active Front End approach for the design of the main ac/dc conversion system (called AGPS) of the NBI power supply (56 MW, 88 MVar) to improve its impact in ITER PPEN in terms of current harmonic and reactive power minimization. After giving a short description of the AGPS reference design, based on thyristor technology, the conceptual design of the AFE alternative topology that I have developed for the input ac/dc rectifier is illustrated; its feasibility, and the advantages and drawbacks with respect to the thyristor solution are evaluated and discussed. The results obtained by the analysis show that the AFE solution is feasible and it significantly improves the impact of the AGPS on the Pulsed Power Electrical Network of ITER with respect to thyristor one. The modifications of the present design parameters to allow the full compliance with the requirements of the technical specifications with the implementation of the AFE solution are also proposed and discussed. This thesis is organized as follows. In the Chapter 1 a brief introduction to the fusion research framework is given. The ITER power supply system is described in the chapter 2. The first part of the PhD thesis related to the development of the analytical model starts in the chapter 3, with the description of the simplified equivalent scheme of the ITER Power Supply. The Quasi-Static and Dynamic Models are described in chapter 4 and 5 respectively, and in the chapter 6 are given the conclusions related to this part. The second part of the PhD thesis related to Study of Active-Front-End design for the Acceleration Grid Power Supply of ITER Neutral Beam Injector start in the chapter 7, describing the reference design of the AGPS based on thyristor solution. Then an overview of the AFE converter topologies and control systems is given and their application to AGPS is discussed in the chapter 8. In chapter 9 the conceptual design of the AGPS based on AFE approach is described in detail. In the chapter 10 the AFE and thyristor solution are compared in terms of impact on the PPEN (reactive power and ac current harmonic)
L’esperimento ITER sarà costruito a Cadarache (Francia) e il suo obiettivo principale sarà quello di dimostrare la fattibilità tecnologica di produzione di grandi quantità d’energia attraverso la fusione in un plasma di deuterio e trizio In un reattore a fusione, il plasma (un gas ionizzato di deuterio e trizio) deve essere riscaldato fino a temperature di milioni di gradi Celsius al fine di sostenere la reazione di fusione. Non vi sono materiali in grado di resistere a tali temperature, per cui il plasma è tenuto lontano dalle pareti della camera da vuoto del reattore per mezzo di opportuni campi magnetici, prodotto dalle correnti nelle bobine superconduttrici, che interagiscono con gli ioni del plasma. Oltre al riscaldamento ohmico, altri due sistemi di riscaldamento sono previsti nel progetto di ITER, basati sulle onde elettromagnetiche a radiofrequenza e iniezione di neutri. Due iniettori di fasci di neutri (Neutral Beam Injectors NBIs) saranno utilizzati per scaldare il plasma; ciascuno è composto da un sistema di griglie che formano cinque stadi di accelerazione da 200 kV ciascuno, che accelerano gli ioni negativi di deuterio o idrogeno, che vengono poi neutralizzati e iniettati nel plasma di ITER. L'alta energia (1 MeV) e la potenza del fascio (16,7 MW) rendono questo progetto molto complesso, vicino alla stato dell'arte dei componenti. Il sistema di conversione ac/dc necessario per alimentare le bobine superconduttrici del sistema di magneti e dei sistemi ausiliari (come i NBIs) può consumare complessivamente una potenza attiva e reattiva rispettivamente fino a 500 MW e 900 Mvar. Negli ultimi anni molti studi sono stati effettuati sul sistema di alimentazione ITER e sul suo impatto sulla rete elettrica (chiamata Pulsed Power Electrica Networ PPEN). Diverse tecniche sono state considerate per migliorare il fattore di potenza dei sistemi di conversione ac/dc a tiristori di ITER. Per quanto riguarda la riduzione dell’assorbimento sono state studiate tecniche quali il controllo sequenziale ed asimmetrico, con bypass interno o con freewheeling esterno. Per quanto riguarda invece la compensazione, l’attuale progetto di riferimento è basato sulla tecnologia Static Var Compensator (SVC) con potenza nominale di 750 Mvar, composto da Thyristor Controlled Reactor (TCR) + Filtri per le armonche di corrente (che hanno la funzione di fornire potenza reattiva). Tuttavia, gli studi sono ancora in corso con l'obiettivo di ulteriori miglioramenti. Questa tesi di dottorato studia due aspetti legati all'impatto sulla rete PPEN del sistema di alimentazione di ITER, con un approccio diverso rispetto a quelli già effettuati. Il primo riguarda lo studio della stabilità della rete elettrica PPEN e principalmente si propone di studiare i fenomeni di interazione tra i sistemi di conversione ac/dc e di compensazione della reattiva, dovuti in particolare all’elevato consumo di potenza durante gli scenari di funzionamento di ITER. Non è un compito facile: il sistema di alimenatzione di ITER è molto complesso, le simulazioni numeriche del suo funzionamento attraverso programmi in grado di riprodurre i profili istantanei di tensione e corrente richiede tempi di calcolo molto lunghi e soprattutto non forniscono alcuna sensibilità riguardo la stabilità del sistema. Ho quindi applicato un approccio analitico e, considerando i metodi sviluppati per le applicazioni HVDC che però non possono essere direttamente applicati al caso ITER, ho sviluppato specifici modelli analitici. Il primo modello è il “Quasi-Static Model”, che ha lo scopo di valutare l’adeguatezza della rete elettrica del sistema di alimentazione di ITER attraverso un’analisi di sensibilità. Ho ricavato le equazioni del modello dalle equazioni ai flussi di potenza in funzione di alcuni parametri rilevanti per l’analisi di sensibilità. Con questo modello ho potuto calcolare alcuni indici come il rapporto critico cortocircuito (Critical Short Circuit Ratio) e il fattore di sensibilità di tensione (Voltage Sensitivity Factor). Nessuna condizione criticha è stata trovata. Il secondo è un modello dinamico (chiamato Dynamic Model), ed è basato sulla formulazione alle variabili di stato e si propone di indagare la stabilità dinamica di tutto il sistema, tra cui anche il sistema di controllo. Tuttavia il sistema di conversione ac/dc e i TCR sono componenti non lineari e discreti, e sono difficili da modellare; considerando i metodi descritti in bibliografia, ho approssimato i fenomeni discreti con funzioni di trasferimento continue, e ho eseguito la linearizzazione attorno ad un punto di equilibrio, utilizzando così l’approccio ai piccoli segnali. Ho adottato un approccio modulare, sviluppando cioè un modello dinamico per ogni sottosistema (i filtri delle armoniche di corrente, i TCR e il sistema di conversione ac/dc). Poi ho costruito modelli numerici dei sottosistemi, con un programma (PSIM) in grado di riprodurre le forme d'onda istantanee per la validazione dei modelli dinamici (implementato con il programma Matlab Simulink, state space tool) attraverso il confronto dei risultati nel dominio della frequenza e del tempo. Infine ho costruito il modello dinamico di tutto il sistema e validato con il modello equivalente in PSIM. Dai risultati delle analisi in frequenza, il modello dinamico è accurato per frequenze inferiori a 50 Hz, ma può essere utilizzato per ottenere qualche informazione circa la stabilità del sistema anche per frequenze fino a 100 Hz. Alcune condizioni di funzionamento instabili sono state individuate e sono dovute alla risonanza tra i filtri e la griglia. Questo modello può essere facilmente implementato con maggiori dettagli per l'intero sistema di alimentazione ITER e può essere uno strumento molto utile e veloce per aiutare la progettazione del sistema di alimentazione e impostare i parametri del sistema di controllo. Come secondo argomento della mia tesi di dottorato, ho studiato la fattibilità tecnologica di utilizzare una tecnologia più avanzata basata su un approccio di rettificazione attiva (Active Front End AFE) per la progettazione del principale sistema di conversione ac/dc (chiamato Acceleration Grid Power Supply AGPS) del sistema di alimentazione del NBI (56 MW , 88 MVAr) per migliorare il suo impatto in sulla rete PPEN in termini di minimizzazione della potenza reattiva e delle armoniche di corrente. In questa parte della tesi, dopo una breve descrizione del progetto di riferimento dell’AGPS basato sulla tecnologia a tiristori, ho descritto il progetto concettuale del sistema di rettificazione dell’AGPS basato sulla soluzione alternativa AFE che ho sviluppato; la sua fattibilità ed i vantaggi e gli svantaggi rispetto alla soluzione tiristori sono stati valutati e discussi. I risultati ottenuti dalle analisi mostrano che la soluzione AFE è fattibile e migliora significativamente l'impatto della AGPS sulla rete PPEN di ITER rispetto a quella a tiristori. Inoltre sono state proposte e discusse alcune modifiche di alcuni parametri del progetto di riferimento per consentire la piena conformità con i requisiti delle specifiche tecniche con l'implementazione della soluzione AFE. Questa tesi è organizzata come segue. Nel capitolo 1, una breve introduzione descrive la ricerca sulla fusione. Il sistema di alimentazione di ITER è descritto nel capitolo 2. La prima parte della tesi di dottorato relativa allo sviluppo dei modelli analitici inizia nel capitolo 3, con la descrizione dello schema equivalente semplificato del sistema di alimentazione ITER. I modelli quasi-statico e dinamico sono descritti rispettivamente nei capitoli 4 e 5, e nel capitolo 6 sono presenti le conclusioni relative a questa parte. La seconda parte della tesi di dottorato relativa allo studio di una soluzione di rettifficazione attiva applicata al sistema d’alimentazione dell griglie (AGPS) dell’iniettore di fasci di neutri inizia nel capitolo 7, che descrive il progetto di riferimento della AGPS basato sulla soluzione tiristori. Poi sono descritte diverse soluzioni AFE e dei sistemi di controllo trovati in bibliografia, e la loro applicazione alla AGPS è discussa nel capitolo 8. Nel capitolo 9 il progetto concettuale della AGPS basato sull’approccio AFE è descritto in dettaglio. Nel capitolo 10 la soluzioni AFE e tiristori sono confrontati in termini di impatto sulla rete PPEN (potenza reattiva e armoniche di corrente)

碩士
國立清華大學
電機工程學系
94
Due to the growing application of power electronics loads, a significant amount of voltage and current harmonics are injected into the power system and the quality of electric power is degraded as a result. To address this issue, various industry standards, such as IEEE 519-1992, IEC 61000-3-2 are introduced to regulate the voltage and current harmonic distortions. For motor drives applications, more and more active front-end converters have been adopted to replace the conventional diode rectifier front-ends to meet these requirements. In addition to its unity power factor operation, the active front-end converter also has the advantage of bi-directional power flow to allow energy regeneration from the DC side to the unity. In this thesis, an active front-end converter prototype is designed and implemented in the laboratory. A closed-loop control method is developed and verified using this prototype. A dynamic model of the active front-end converter is also developed to identity its transient and steady state behavior. Laboratory test results are presented to validate the performance of the control design and the accuracy of the dynamic modeling.

碩士
長庚大學
電機工程學研究所
97
Power consumption has been increasing at an unprecedented rate due to industrial extension. Inverter based distributed generation system is a promising solution to rapid growing demand of electricity with premium and quality features. Conventional grid-connected inverter may suffer from switching EMI noise and/or a low-frequency transformer, in terms of both weight and volume. This paper presents a power flow control strategy for a hybrid active front-end converter. The proposed hybrid active front-end converter is composed of a tuned capacitor and a voltage source converter in series connection. Since the series capacitor can sustain the fundamental voltage, the converter can operate with a reduced dc voltage without a low-frequency coupling transformer. By adjusting output voltage vector of the converter, therefore, the maximum real power or the maximum reactive power between the dc side and ac side can be controlled to accomplish dc voltage regulation and grid voltage supporting, respectively. Operational principles and design considerations of the proposed hybrid active front-end converter are detailed. Computer simulations and experimental results, based on TI TMS320F28335, are provided to verify the effectiveness and feasibility of the proposed method.

IGBT based power converters acts as front end in the present day Adjustable Speed Drive (ASD). This offers many advantages and makes regenerative action possible. PWM rectifier operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Due to fast turn-ON and turn-OFF time of IGBT, the inverter output voltage dv/dt is high during switching transients and voltage waveform is rich in harmonics. As a result, in applications involving long cable the motor terminal voltage during the switching transient is as high as twice the applied voltage. This voltage stress reduces the life of insulation in motors. The high dv/dt output voltage applied at the motor terminal excites the parasitic capacitive coupling resulting in increased ground currents and causes Electric Discharge Machining (EDM) which reduces the life of motor bearings. The common mode voltage due to PWM rectifier and the inverter appear at the motor terminals exacerbating these problems. The common mode voltage due to PWM inverter with PWM rectifier is analyzed. An integrated approach for filter design is proposed wherein the adverse effects due to common mode voltage of both AFE converter and the inverter is addressed. The proposed topology addresses the problems of common mode voltage, common mode current and voltage doubling due to ASD. The design procedure for proposed filter topology is discussed with experimental results that validate the effectiveness of the filter. Inclusion of such higher order filter in the converter topology leads to problems such as resonance. Passive methods are investigated for damping the line resonance due to LCL filter and common mode resonance due to common mode filter. The need for active damping technique for resonance due to common mode filter is presented. State space based damping technique is proposed to effectively damp the resonance due to line filter and the common mode filter. Experimental results are presented that validate the effectiveness of active damping both on the line basis (differential mode) and line to ground basis (common mode) of the filter.

IGBT based power converters acts as front end in the present day Adjustable Speed Drive (ASD). This offers many advantages and makes regenerative action possible. PWM rectifier operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Due to fast turn-ON and turn-OFF time of IGBT, the inverter output voltage dv/dt is high during switching transients and voltage waveform is rich in harmonics. As a result, in applications involving long cable the motor terminal voltage during the switching transient is as high as twice the applied voltage. This voltage stress reduces the life of insulation in motors. The high dv/dt output voltage applied at the motor terminal excites the parasitic capacitive coupling resulting in increased ground currents and causes Electric Discharge Machining (EDM) which reduces the life of motor bearings. The common mode voltage due to PWM rectifier and the inverter appear at the motor terminals exacerbating these problems. The common mode voltage due to PWM inverter with PWM rectifier is analyzed. An integrated approach for filter design is proposed wherein the adverse effects due to common mode voltage of both AFE converter and the inverter is addressed. The proposed topology addresses the problems of common mode voltage, common mode current and voltage doubling due to ASD. The design procedure for proposed filter topology is discussed with experimental results that validate the effectiveness of the filter. Inclusion of such higher order filter in the converter topology leads to problems such as resonance. Passive methods are investigated for damping the line resonance due to LCL filter and common mode resonance due to common mode filter. The need for active damping technique for resonance due to common mode filter is presented. State space based damping technique is proposed to effectively damp the resonance due to line filter and the common mode filter. Experimental results are presented that validate the effectiveness of active damping both on the line basis (differential mode) and line to ground basis (common mode) of the filter.

碩士
中華大學
電機工程學系
104
Active Front End converter (AFE) having a controllable DC voltage, controllable power factor, bidirectional power flow control and low harmonic distortion of the phase current, it can achieve requirements of IEEE 519- 1992, IEC 6100-3-2 and other industry specifications to avoid voltage and current drops leaving the power quality when the power system contain non-linear loads. The architecture of multi-level inverter reduce the total harmonic distortion for achieve a higher quality of the power system effectively. So the architecture has gradually replace the traditional diode bridge rectifiers applied to the motor drive on. Because consideration of traditional inverters size and the design of filter tend to increase its switching frequency to reduce the size of its inductor, but in hard switching system, it’s also resulting in increased switching loss. This paper uses a cascade H-bridge multi-level active front-end converter architecture with different low carrier ratio (nine times, fifteen times, twenty times), to discuss the total harmonic distortion and harmonics component. The low-carrier ratio modulation method is proposed in this context, and it compare with the traditional Sinusoidal Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM).

碩士
國立中山大學
電機工程學系研究所
103
The thesis proposed a resonant current controller in stationary-frame for LLCL-based active front end converter where the LLCL filter can provide switching harmonic current suppression and the grid side inductance decrease. The proposed harmonic current controller suppression harmonic current caused by grid. When the grid unbalanced, the thesis proposed command generator produces three phase current command based on the three phase positive-sequence components of the grid voltage, so the current command can be three-phase balanced. This will prevent grid-side current from triggering the protection relay because of the single-phase over current induced by unbalanced. The data required to operate the proposed control strategy are converter side current, LLCL filter voltage and dc bus voltage. This approach conduct harmonic- and negative-sequence current suppression under distorted and unbalance grid voltage without phase locked loop operation、positive/negative sequence frame transformation nor coupling network. This is the significant advantage to decrease the computing effort and control complexity. The theoretical is validated by means of experimental results from laboratory platform of the proposed active front end converter.

碩士
國立中山大學
電機工程學系研究所
98
Thanks to development of power semiconductor devices and integrated circuits, active front-end converters with controllability of bidirectional power flow have become popular and viable in industrial applications. This thesis proposes an improved resonant current control for the active front-end converter with LCL filter. The proposed control consists of a band-pass filter tuned at fundamental frequency and various band-rejected filters resonant at harmonic frequencies to provide fundamental current tracking capability as well as enhance harmonic current rejection. Based on this algorithm, the active front-end converter can control dc voltage with unity power factor by sensing converter output current, LCL filter voltage and dc voltage. This approach also conducts harmonic current rejection under distorted line voltage with no phase-locked-loop used, which is the significant advantage in terms of phase lag of frame transformation and computing effort of digital signal processing. Current tracking performance and harmonic rejection capability of the proposed method are verified based on frequency-domain analysis. Computer simulations and experimental results are also implemented to validate effectiveness.

博士
國立清華大學
電機工程學系
97
In variable speed drive systems, diode rectifiers or thyristor rectifiers are usually used as the AC/DC front-end. The advantages of the conventional rectifier include low cost, simplicity, and high reliability. However, these rectifiers draw significant harmonic current from the utility grid and lack regeneration capability. Industry standards, such as IEEE-519 and IEC-61000-3-2, are adopted to address these issues. Recently, Insulated Gate Bipolar Transistor based active front-end (AFE) converter systems are widely utilized by industries thanks to the advantages of bi-directional power flow, unity power factor, low harmonic distortion of the line current and small filter size. This dissertation presents a synchronous reference frame based model for AFE converter and discusses in detail how the control design affects the disturbance rejection capability and robustness. While achieving high-power factor operation and regeneration capability, however, AFE converters cost much more than diode rectifier front-ends. Therefore this dissertation proposes an auxiliary converter (AXC) for the diode rectifier front-end system. The AXC and diode rectifier are connected in parallel on the AC side. Both are also connected on the DC side via diodes. The AXC system operates as a shunt active filter to compensate for current harmonics of the diode rectifier, and provides regeneration capability. Thus it can accomplish the functionalities of an AFE converter, but with only 0.3-0.5 pu of converter rating. The simulation results and experimental results are used to validate the performance of the AFE and AXC converter system. Keywords: active filter, active front-end converter, auxiliary converter

Inductors are extensively used in the design of radio-frequency circuits. In the last decade, the integration of passive components, especially inductors on silicon chips, has led to the widespread development and implementation of Radio Frequency Integrated Circuits (RFICs) in CMOS technologies. However, on-chip passive inductors occupy a large silicon chip area and hardly scale down with technology scaling. Therefore, on-chip passive inductors become formidable obstacles to the realization of highly dense RFICs to be integrated with other highly dense digital circuits on a single chip using a common fabrication process. In recent years, researchers have focused on replacing passive inductors with transistor-only active circuits, namely active inductors. Active inductors can be realized with only a few transistors, which scale down with technology scaling. Therefore, they occupy a fraction of the chip area of their passive counterparts, and can be implemented densely in CMOS processes. Unlike passive inductors, bias dependent operations of active inductors allow for the tuning of their inductance and quality factor Q, and in turn, tuning the performance parameters of RFICs. This thesis focuses on the design and development of passive inductorless CMOS RFICs for ultra-wideband (UWB) receiver front-ends using active inductors. A new Q-enhanced and a new bandwidth-extended tunable active inductors are designed. Using the Q-enhanced active inductor, two tunable UWB low-noise amplifiers (LNAs) (two-stage and three-stage UWB LNAs), a UWB mixer and a wideband local-oscillator (LO) driver are designed. Active inductors are utilized to develop a novel wideband active shunt-peaking technique that decreases high-frequency losses to yield a flat gain over a wide bandwidth. A tunable multiband-UWB front-end integrating a two-stage UWB LNA, and a pair of UWB mixers driven by a pair of wideband LO drivers, is fabricated in a 90nm digital CMOS process. The passive inductorless two-stage UWB LNA, three-stage UWB LNA and UWB front-end occupy chip areas of only 0.0114mm2, 0.0227mm2, and 0.1485mm2, respectively. The active CMOS UWB front-end exhibits a measured flat gain of 22.5dB over 2.5-8.8 GHz bandwidth, and its tunability allows for varying the gain and bandwidth.
Integrated Circuits and Systems

碩士
國立臺灣大學
電機工程學系研究所
86
Active inductors have the advantages of smaller area, easier implementation, tunable and stabler center frequency over spiral inductors or bonding wires for the LC-tank in RF circuits. This paper presents a 900MHz CMOS RF front-end circuit composing of a wide-center-frequency-tuning-range LNA using active inductor and Gilbert type downconversion mixer. The front-end circuit can output 10MHz 28mV IF band signal with a RF input 830MHz 10uV sinusoidal signal and two LO input 840MHz 500mV sinusoidal signals. The LNA has a 39.7dB gain with 829.3MHz center frequency, and the center frequency tuning range is from 700MHz to 880MHz where the gain is all above 20dB. The noise figure of LNA is 1.82dB, and P1dB is -25.8dBm.

碩士
國立中央大學
電機工程研究所碩士在職專班
98
The work in this thesis focuses on Ka-band active array antenna and Ku-band RF receiver front-end circuits. The active array antenna uses Rogers RO5880 substrate to integrate the low noise amplifier (LNA) and power amplifier (PA), then assemble them to the metal housing. The LNA and PA were designed and fabricated in tsmc 0.18 ?m CMOS technology. The designed circuits include 28 GHz common source wideband LNA, Ku-band CPW LNA with transformer feedback technique. A 27.1 GHz transformer feedback voltage control oscillator is also designed and demonstrated. The active antenna array design includes Wilkinson power divider, angled-dipole antenna, angled-dipole antenna array and active antenna array which integrate previous mentioned LNA and PA. The thesis further addresses Ka-band RF receiver front-end circuits. The 28 GHz common source wideband LNA was implemented using inductive source degenerated topology. The LNA achieved a gain of 12.6 dB, a 3-dB bandwidth of 8 GHz and the input /output return losses of more than 8.3 dB , a noise figure of 4.87 ~ 6.55 dB between 22 ~ 30 GHz. The Ka-band CPW LNA using transformer feedback technique achieved a gain of 15.11 dB, input return losses of more than 12 dB, output return loss of more than 7 dB, a noise figure of 5.87 dB. The 27.1 GHz transformer feedback voltage controlled oscillator utilized the transformer to lower the phase noise. This VCO obtained a tuning range of 700 MHz, an output power of -17dBm, and the phase noise of -93.27 dBc/Hz at 1 MHz offset.

碩士
國立中央大學
電機工程研究所
100
This study investigates the systematic method in designing highly integrated active band-pass filters. The target is to integrate the SPDT (Single Pole Double Throw) RF switch, LNA (Low noise amplifier), balun and band-pass filter into a single circuit. By this integrated design we can improve the mismatch loss of conventional RF front end system, and schieve the goal of miniaturization and improve the level of integration in system design. Two design approaches are proposed to achieve the above design goal. The first one is based on the integration of bandpass filter and SPDT RF switch using the multicoupled line structure, and combined the active loaded which can provide the negative resistance to compensate the insertion loss. The proposed active load is based on a common-source structure with an R–L–C series feedback, which is different from the conventional types in the oscillator design methods. It does not use a common-gate series feedback structure or any additional drain- or source-to-gate parallel feedback paths that may degrade the noise performance. Therefore, the noise figure can be improved by the proposed topology. The second design is based on the insertion loss method for filter design to achieve the complex impedance matching of the LNA input, such that the amplifier can have a band-pass response. As for output matching of LNA we use the multicoupled line structure to achieve the single-to-balanced bandpass filter response. Then, by integrating the SPDT switch function using coupled-lines, we can integrated the SPDT switch, band-pass filter, LNA, and balun in a single circuit. The proposed design methods are validated using hybrid and integrated microwave circuits. The proposed methods are simple and are capable of integrating multiple functional blocks in a single circuit, which is helpful in minimizing the circuit size, improving the system performance, and also reducing the complexity of design process for RF front-end designs.

碩士
國立暨南國際大學
電機工程學系
93
In this thesis, study of RF active device and RF passive device, respectively. And three kinds of RF Front-end amplifier essential to the wireless transceiver are expounded; they are low noise amplifier, ultra wideband low noise amplifier and wideband amplifier, respectively. The RF device part is study of source-to-body spacing on 4-terminal RF MOS; other is RF passive device is study of variable inductance inductor with MOS switches. The RF amplifier (1/3) is on the design of low noise amplifiers. We use a M-field Coupling-Enhanced small area planar spiral inductor to save layout area, improve circuit performance and implementation of concurrent dual-band low noise amplifier. The RF amplifier (2/3) is on the design of an ultra wideband low noise amplifier. We use an inductive peaking method to improve flat gain for 3.1~10.6 GHz Ultra wideband LNA. The RF amplifier (3/3) is on the design of a wideband amplifier. We use an inductive peaking with MOS switch to study inductive peaking effect on variable bandwidth wideband amplifier.

Thesis (M.S.) -- University of Tennessee, Knoxville, 2005.
Title from title page screen (viewed on July 6, 2005). Thesis advisor: Leon M. Tolbert. Document formatted into pages (xiii, 120 p. : ill. (some col.)). Vita. Includes bibliographical references (p. 115-119).

碩士
國立成功大學
電腦與通信工程研究所
101
Two quasi-circulators and a active balun using TSMC 90 nm CMOS process for communication front-end system applications are proposed. First, a broadband and high isolation active quasi-circulator MMIC is introduced. The quasi-circulator cascaded two buffer stages to expand the bandwidth and improve the isolation from port 2 to port 1 and from port 3 to port 2. The leakage signal from port 1 to port 3 can be reduced effectively by the phase cancellation technique. As the measured results show, the proposed quasi-circulator possesses an insertion loss less than 8 dB and all isolations on 5-33 GHz are better than 20 dB. Afterward, a Ka to W band CMOS quasi-circulator combined Lange coupler and transistors to achieve high isolation and broad bandwidth by phase cancellation technique. Based on the simulation, very wideband operation from 26 to 120 GHz can be obtained. The measured data shows that better than 40 dB isolation between the port 1 and port 3 with 94 GHz (26-120 GHz) operational bandwidth. While that for port 2 to port 1 and port 3 to port 2 is better than 30 and 35 dB, respectively. The insertion loss of port 1 to port 2 is 7-10 dB, and that of port 2 to port 3 is 6-10 dB. Due to the measurement system limitation, the overall measured bandwidth of the proposed quasi-circulator was implemented in the range of DC-67 GHz, therefore, the measured insertion losses is about 6-9 dB and isolations are better than 20 dB from 26-67 GHz. Finally, a high gain and high P1dB active balun with low power consumption was proposed. The proposed circuit consisted of differential stage and current-reuse LNA to achieve high insertion gain and reduce the DC power consumption. Moreover, the proposed active balun used single differential stage can avoid to decreasing the P1dB, and cascaded a gate inductor with differential stage to enhance the operation bandwidth. Base on the simulated results, the proposed active balun exhibits good insertion gain of 12-15 dB and low gain/phase error are less than 1.5 dB/4 degree with high P1dB of 2.3 dBm in 6-25 GHz operation bandwidth.

Dissertação de mestrado em Engenharia Eletrónica Industrial e de Computadores
Hoje em dia, devido à utilização massiva de cargas não lineares pelos consumidores em geral, tem aumentado progressivamente o conteúdo harmónico nas formas de onda das correntes, que, por sua vez, provocam quedas de tensão nas impedâncias das linhas, contribuindo para o aumento do conteúdo harmónico das tensões na rede elétrica. Como resultado, cada vez mais a rede elétrica apresenta baixos índices de qualidade de energia elétrica. O projeto em que esta dissertação está enquadrada consiste no desenvolvimento de um condicionador da qualidade de energia unificado (unified power quality conditioner - UPQC) trifásico com interface, através do barramento cc, a uma fonte de energia renovável e a um sistema de armazenamento de energia. O UPQC desenvolvido consiste na junção de um condicionador ativo série (CAS), um condicionador ativo paralelo (CAP) e um conversor cc-cc com interface com a fonte de energia renovável e o sistema de armazenamento de energia e o barramento cc. Assim, o CAS é responsável por garantir tensões sinusoidais e equilibradas às cargas, o CAP é responsável por garantir correntes sinusoidais e equilibradas na rede elétrica e o conversor cc-cc tem como funcionalidade carregar ou descarregar as baterias e extrair a máxima potência da fonte de energia renovável. Com o desenvolvimento deste UPQC é possível melhorar a qualidade da energia elétrica, beneficiando tanto o utilizador final como o fornecedor de energia e todo o sistema de transporte. Assim, o âmbito desta dissertação é apenas referente ao desenvolvimento do conversor cc-ca para o CAP do UPQC. No âmbito desta dissertação, e de acordo com o enquadramento do projeto, este conversor é responsável por garantir correntes sinusoidais e equilibradas na rede elétrica, manter a tensão do barramento cc regulada e manter um fluxo bidirecional de energia com a rede elétrica de acordo com a operação do conversor cc-cc (fonte de energia renovável e sistema de armazenamento de energia).
Nowadays, due to the massive use of nonlinear loads by consumers in general, it has progressively increased the harmonics content in the waveforms of the currents, causesing voltage drops in the line impedances, contributing for increasing the harmonic content of the voltages in the electrical grid. As a result, each more, the electric grid presents low indices of power quality. The project where this dissertation is framed consists in the development of a three-phase unified power quality conditioner (UPQC) with interface, through the dc-link, to a renewable energy source and to an energy storage system (batteries). The developed UPQC consists is the combination of a series active conditioner (CAS), a parallel active conditioner (CAP) and a dc-dc converter for the interface between the CAS, the CAP, the renewable energy source and energy storage system. Therefore, the CAS is responsible for ensuring sinusoidal and balanced voltages to the loads, the CAP is responsible for ensuring sinusoidal and balanced currents to the electrical grid, and the dc-dc converter has the function of charging or discharging the batteries and extracting the maximum power from the renewable energy source. With the development of this UPQC, it is possible to increase the quality on the electrical grid side, benefiting: the end-user, the electricity supplier and the entire transportation system. Thus, the purpose of this dissertation is only related with the development of the dc-ac converter applied in the CAP of the UPQC. In the context of this work, and according to the project structure, this converter is responsible for ensuring sinusoidal and balanced currents from the electrical grid, maintaining a regulated dc-link voltage, as well as maintaining a bidirectional power flow according to the operation of the dc-dc converter (used to interface the renewable energy source and energy storage system).
FCT – Fundação para a Ciência e Tecnologia pelo suporte financeiro concedido através do Projeto 0302836 NORTE-01-0145-FEDER-030283 e ERDF–COMPETE 2020 Programme, SAICTPAC/0004/2015–POCI–01–0145–FEDER–016434

碩士
國立雲林科技大學
電機工程系
103
In computer science, front-end and rear-end respectively stand for the beginning and the end of processes, that is, the direct communications with users and the outputs of results. In this thesis, the adaptive mechanism is titled “front-end” because it basically makes judgments and corrections on input ends, and the results are then used for further noise control. We have proposed a modified system based on the adaptive concepts from DF-FLANN (decision-feedback functional link artificial neural network) and ODF-FLANN (optimized DF-FLANN) structures. The system not only deals with input signals on both linear and nonlinear considerations, but also includes a noise reduction mechanism for suppressing noise peaks at the start. For the above reasons, we call this proposed system a front-end advanced adaptive DF-FLANN (FAADF-FLANN). The purpose of this thesis is to improve the data types of DF-FLANN architecture. Specifically, we have shortened its computation time, and added the noise reduction mechanism of the second channel so that the noise peaks can be lessened. The final goal is then to make adaptive learning more accurate. From experiment results, we observe that the processing time of FAADF-FLANN on 1000 input noise samples is about 40 seconds faster than DF-FLANN. As the mounted of data increases, the time difference also increases substantially. For example, the time difference can be up to 600 seconds when 20000 data samples are processed. Another advantage is that the secondary channel output values shrinks to within 2 to 4 times of the original noise amplitude, while for DF-FLANN it is about 6 times. Most important of all, adaptive learning associated with front-end judgment mechanism makes FAADF-FLANN not only work well at different settings of μ values, but also achieve better learning and convergence conditions. From these results, we conclude that FAADF have obvious advantages over DF-FLANN.

博士
國立成功大學
微電子工程研究所碩博士班
99
Wireless telecommunications research has experienced a remarkable renaissance in the last decade. Low cost, low power and a compact-size are the essential requirements for modern RF frond-end systems. To accomplish a successful design that meets all of these requirements, circuit design techniques and advanced process technology are necessary. In the RF frond-end system, low-noise amplifiers, baun, and oscillators are essential components. LNA is used to amplify RF input signals, and its performance must be kept sufficiently high to minimize the requirements for circuits’ parameters from the following stages. In research on LNA, the design, fabrication, and measured performance of LNAs operating at the S-band and UWB will be presented. In this dissertation, 2.4 GHz high linearity LNA with Image-rejection is proposed. The active filter is used for high selection of image band and reducing the chip size. The linearity of 2.4-GHz Image-Rejection LNA is improved by employing derivative superposition (DS) technique with PMOS auxiliary stage and rejecting the gm3 for high input third-order intercept point (IIP3). Then an UWB LNA using active shunt-feedback technique has been proposed. By employing active shunt-feedback technique, the UWB LNA achieves wideband input matching characteristic and uses fewer devices to reduce the chip size. The output matching of the proposed UWB LNA uses a center-tapped inductor for second-order matching design. An ultra-wideband active balun using standard 0.18 μm CMOS process has been presented in chapter 4. The measurement shows that the active balun using parallel common-gate and common-source generates a 50 Ω real part and achieves wideband input matching from 3.1 GHz to 10.6 GHz. The phase behaviors are dominated by CS and CG. The amplitude imbalances are dominated by the bias and size of CG and CS and amplitude imbalances is less than 0.5 dB. In order to solve the issue of the active balun which is the high power consumption, the current-reused structure is used. Finally, in chapter 5, CMOS second-order LC VCOs are designed and discussed. Two ways to design the LC tank with a high Q passive center-tapped inductor and an active inductor for IEEE 802.11a/b/g applications. A 5.37 GHz second harmonic suppressed cross-coupled CMOS VCO using circuit is presented firstly. Following, a high performance 2.33 GHz cross-coupled CMOS VCO using active filtering circuit is presented. Measured results demonstrate that low phase noise has been achieved by second harmonic suppression of cross-coupled CMOS VCO. The large-signal simulation results prove that the second harmonic signal distorts to the fundamental signal.

Direct Power Control (DPC) is a good alternative to conventional Voltage Oriented Control (VOC) for three-phase active rectifiers. It has several features such as it does not require PI (current) controllers, direct control of active and reactive powers, faster dynamics and decoupled control. In this thesis work, DPC techniques have been extensively studied, investigated, modified and proposed to achieve better power quality performance in terms of reduction in power ripples and THD content. The primary objective of this work is to introduce new DPC techniques to enhance the power quality performance without influencing its features. In this work Algorithm based DPC (A-DPC), Nearest Vector Selection based DPC (NVS-DPC), Virtual flux Deadbeat Predictive DPC (DB-DPC) and Zero Direct Power Control (ZDPC) with Fractional order PI (DC-bus voltage) controller optimized by Teaching learning-based Optimization (TLBO) technique is introduced and enhanced power quality performance is obtained. All the techniques performance is well tested and verified in simulation as well as in experiments. The proposed techniques are following the IEEE standards 519-1992 of power quality.

In this thesis, based on the indoor channel measurements and ray-tracing modeling for the indoor mm-wave wireless communications, the challenges of the design of the radio in this band is studied. Considering the recently developed standards such as IEEE 802.15.3c, ECMA and WiGig at 60 GHz, the link budget of the system design for different classes of operation is done and the requirement for the antenna and other RF sections are extracted. Based on radiation characteristics of mm-wave and the fundamental limits of low-cost Silicon technology, it is shown that phased-array is the ultimate solution for the radio and physical layer of the mobile millimeter wave multi-Gb/s wireless networks. Different phased-array configurations are studied and a low-cost single-receiver array architecture with RF phase-shifting is proposed. A systematic approach to the analysis of the overall noise-figure of the proposed architecture is presented and the component technical requirements are derived for the system level specifications. The proposed on-chip antennas and antenna-in-packages for various applications are designed and verified by the measurement results. The design of patch antennas on the low-cost RT/Duroid substrate and the slot antennas on the IPD technologies as well as the compact on-chip slot DRA antenna are explained in the antenna design section. The design of reflective-type phase shifters in CMOS and MEMS technologies is explained. Finally, the design details of two developed 60 GHz integrated phased-arrays in CMOS technology are discussed. Front-end circuit blocks such as LNA, continuous passive reflective-type phase shifters, power combiner and variable gain amplifiers are investigated, designed and developed for a 60 GHz phased-array radio in CMOS technology. In the first design, the two-element CMOS phased-array front-ends based on passive phase shifting architecture is proposed and developed. In the second phased-array, the recently developed on-chip dielectric resonator antenna in our group in lower frequency is scaled and integrated with the front-end.

Multilevel converters are becoming more and more popular, overcoming some key limitations of conventional two-level structures in handling medium voltages and high voltage gradients. Today they provide the ground for the realization of high efficiency energy conversion systems for medium voltage applications, such as pumps, compressors, extruders, fans, grinding mills, rolling mills, conveyors, crushers, blast furnace blowers, gas turbine starters, mixers, mine hoists, reactive power compensation, marine propulsion, wind energy conversion, and railway traction. A detailed overview of multilevel converters is provided in Chapter 1, while, the state of the art of Open-end Winding Systems is described in Chapter 2. The last systems can be considered as special multilevel inverter structures, tailored around an electrical machine fed from both the ends of the stator, or primary, winding. Overvoltage phenomena generated in industrial motor drives at motor terminals by long feeding cables are investigated in Chapter 3 and an Open-end Winding configuration approach is presented to actively mitigate them. Moreover, an adaptive algorithm is described to make independent the active overvoltage mitigation from system parameters. The main contribution of this work is the development of a new multilevel inverter topology, the Asymmetrical Hybrid Multilevel Inverter (AHMLI), which is introduced in Chapter 4. According to the AHMLI structure, an open-end winding machine (motor, generator or transformer) is supplied on one end by a main multilevel converter, fully managing the active power stream, and, on the other end by an auxiliary two level inverter. This acts as an active power filter, suitably shaping the electrical machine phase current. A mathematical analysis of the proposed structure is first provided, followed by an exhaustive comparison between AHMLI and conventional multilevel structures, emphasizing advantages in terms of efficiency and output current THD. Voltage and current control systems, optimally coping with key characteristics of the AHMLI structure are carried out and an original input capacitors voltage equalization technique is also presented. The application of the AHMLI concept to industrial induction motor drives is then evaluated by simulation and experimental test. A possible exploitation of the AHMLI approach in the realization of photovoltaic and wind plants, as well as STATCOM devices is also assessed. Moreover, a high efficiency three phase rectifier for high speed generation systems exploiting the AHMLI configuration is carried out. Finally, the application of the AHMLI approach to Multiple Motor Drive systems is proposed in Chapter 5. Two new topologies are presented, namely: Open-end Winding Multi Motor Single Converter (MMSC) and Open-end Winding Multi Motor Multi Converter (MMMC). Both configurations exploit the AHMLI structure but the MMMC exploits a five-leg two level inverter to independently control the stator currents of two induction motors.

Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW􀀀1, using 1.2 V supply. The two LNA approaches proposed in this thesis are validated by simulation and by measurement results, and are included in a receiver front-end for biomedical applications (ISM and WMTS), as an example; however, they have a wider range of applications.

Η πληθώρα των εφαρμογών που μπορεί να εξυπηρετήσει η τεχνολογία Υπερευρείας Ζώνης (UWB), από τα ασύρματα προσωπικά δίκτυα υψηλών ταχυτήτων, μέχρι τα ασύρματα δίκτυα αισθητήρων με δυνατότητες ακριβούς εντοπισμού θέσης, και τα ασύρματα δίκτυα ιατρικών αισθητήρων, έχει προκαλέσει έντονο ερευνητικό ενδιαφέρον γύρω από τις υλοποιήσεις UWB συστημάτων. Η ασυνήθιστα μεγάλη περιοχή συχνοτήτων που έχει ανατεθεί στο UWB, από τα 3.1-10.6 GHz, επιτρέπει την επίτευξη υψηλών ταχυτήτων με απλά σχήματα διαμόρφωσης, ωστόσο, λόγω της διαμοίρασης του φάσματος με τις υφιστάμενες τεχνολογίες ασύρματης δικτύωσης, οι UWB εκπομπές πρέπει να περιορίζονται σε ισχύ κάτω από το κατώφλι των -41.3 dBm/MHz, ικανοποιώντας πολύ αυστηρές μάσκες εκπομπής που εισάγουν έντονες προκλήσεις στη σχεδίαση των πομπών. Η υλοποίηση αναδιατάξιμων UWB πομπών σε σύγχρονες CMOS τεχνολογίες, με υψηλή φασματική ευελιξία, ταχύτητα και ποιότητα διαμόρφωσης, καθώς και με χαμηλή κατανάλωση, αποτέλεσε το αντικείμενο της συγκεκριμένης διατριβής. Υιοθετώντας την αρχιτεκτονική Multi-Band Impulse-Radio (MB-IR) σε συνδυασμό με την τεχνική Direct Sequence BPSK, η έρευνα προσανατολίστηκε προς την ανάπτυξη καινοτόμων μονάδων βασικής ζώνης, με στόχο την ενεργειακά αποδοτική αντιστροφή Γκαουσιανών μορφοποιημένων παλμών υψηλής ποιότητας φάσματος και διάρκειας μικρότερης ακόμα και από 1 nsec. Προς αυτή την κατεύθυνση, αναπτύχθηκε μια καινοτόμα γεννήτρια Γκαουσιανών παλμών με πολύ χαμηλούς πλευρικούς λοβούς στο φάσμα, τυπικά κάτω από -40 dB, ώστε να υποστηρίζονται οι αυστηρότερες μάσκες εκπομπής ή και μελλοντικές. Η σχεδίασης της προτεινόμενης γεννήτριας είχε ως κριτήριο την ευέλικτη ρύθμιση της διάρκειας των παραγόμενων παλμών, και αξιοποίησε τη χαρακτηριστική μεταφοράς τάσης ενός ωμικά φορτωμένου, ασύμμετρου CMOS αντιστροφέα. Η γεννήτρια βασίζεται κυρίως σε ψηφιακά κυκλώματα πολύ χαμηλής τάσης και, σε σύγκριση με τις υφιστάμενες υλοποιήσεις, παρουσιάζει σημαντικό προβάδισμα στον τομέα της ταχύτητας, καθώς και στο πλάτος εξόδου, η μεγάλη τιμή του οποίου χαλαρώνει σημαντικά τη σχεδίαση του RF front end. Η γεννήτρια μελετήθηκε διεξοδικά, διεξήχθη ανάλυση κλιμάκωσης, έγινε εξαγωγή σχεδιαστικών εξισώσεων και αναπτύχθηκαν εργαλεία λογισμικού για την αυτοματοποιημένη σχεδίασή της. Για περαιτέρω αύξηση της ταχύτητας των παλμικών σημάτων εφαρμόσθηκε ειδική σχεδίαση, η οποία αντιπραγματεύεται την ταχύτητα με το επίπεδο των λοβών του φάσματος. Για την αποδοτική BSPK διαμόρφωση των Γκαουσιανών παλμών αναπτύχθηκε ειδική τοπολογία “Μεταγωγής Σήματος Πυροδότησης Πλήρους Ισορροπίας με Up-Conversion”. Η τοπολογία αυτή, σε αντίθεση με τις ανταγωνιστικές τοπολογίες, αποφεύγει την αντιστροφή του παλμού με αναλογικά κυκλώματα υψηλής κατανάλωσης, αλλά και την αναλογική μεταγωγή, καθώς η διαμόρφωση λαμβάνει χώρα πριν από την παραγωγή των παλμών. Παράλληλα, επιτυγχάνονται υψηλοί ρυθμοί, καθώς και υψηλή ποιότητα διαμόρφωσης λόγω των ισορροπημένων μονοπατιών της τοπολογίας. Η γεννήτρια μαζί με το διαμορφωτή αποτελούν τις καινοτόμες παρεμβάσεις στη μονάδα Βασικής Ζώνης του προτεινόμενου πομπού. Για την ολοκλήρωση της λειτουργικότητας του πομπού, αναπτύχθηκε ένα RF front end, το οποίο αποτελείται από έναν διπλά ισορροπημένο μίκτη, έναν LO buffer, ένα μετατροπέα διαφορικού σήματος σε απλό, και έναν ενισχυτή ισχύος, ο οποίος είναι προσαρμοσμένος στα 50 Ohms, χωρίς να απαιτεί κανένα εξωτερικό στοιχείο. Το RF front end ολοκληρώθηκε μαζί με τη μονάδα βασικής ζώνης, και ο ολοκληρωμένος πομπός κατασκευάστηκε σε τεχνολογία CMOS 130 nm. Το ολοκληρωμένο προσαρτήθηκε στην RF πλακέτα συστήματος με την τεχνική Chip on Board. Για την επιτυχία του συστήματος με την πρώτη προσπάθεια έγινε συσχεδίαση σε επίπεδο IC-Package-PCB, δίνοντας ιδιαίτερη έμφαση στα ζητήματα Signal/Power Integrity. Ο πομπός παρουσίασε την υψηλότερη ταχύτητα από τις ανταγωνιστικές MB-IR UWB υλοποιήσεις, ίση με 1.5 Gbps, με αντίστοιχη ενεργειακή αποδοτικότητα 21 pJoule/bit και μέτρο διανυσματικού σφάλματος 5.5%. Ο πομπός βελτίωσε τους πλευρικούς λοβούς στο φάσμα περισσότερο από 10 dB, ενώ η διατριβή, εκμεταλλευόμενη την αναδιαταξιμότητα του πομπού, παρουσιάζει, επιπλέον, τις πρώτες μετρήσεις σε ταχύτητες εκατοντάδων Mbps για ικανοποίηση της χαμηλής ζώνης της πρόσφατα θεσμοθετημένης, και εξαιρετικά αυστηρής, ευρωπαϊκής μάσκας εκπομπής.
The multitude of applications that Ultra-Wideband (UWB) technology can serve, from high-speed Wireless Personal Area Networks, to Wireless Sensor Networks with precision Geolocation abilities, and Wireless Medical Networks, has attracted intense research interest in the implementation of UWB systems. The unusually wide range of frequencies assigned to UWB, from 3.1-10.6 GHz, allows UWB systems employing low order modulation schemes to enjoy high throughput at low power consumption. However, since UWB shares the spectrum with existing wireless networking technologies, UWB emissions must be limited to a power spectral density below the threshold of -41.3 dBm/MHz, satisfying very stringent emission masks and introducing great challenges in the design of UWB transmitters. The subject of this thesis is the design of low power, fully integrated, reconfigurable CMOS UWB transmitters, with high spectral flexibility, high speed and high modulation quality. Adopting the Multi-Band Impulse-Radio architecture, in conjunction with the Direct Sequence BPSK modulation, the research focused on the development of a baseband unit, able to precisely invert Gaussian shaped, subnanosecond pulses. The key contributions of this thesis are a CMOS Gaussian Pulse Generator and a BSPK modulation topology, which jointly constitute the proposed baseband unit. The Pulse Generator (PG) is based on non-linear shaping, so as to facilitate the configurability of the output pulse duration, and exploits the voltage transfer characteristic of a Resistive Loaded Asymmetrical CMOS Inverter, which results in spectral sidelobes typically better than -40 dB. The PG incorporates mostly-digital low voltage circuits, while the MOSFET devices that undertake the pulse shaping avoid exclusive operation in weak inversion, in contrast to previous implementations. Consequently, the proposed CMOS PG is able to support higher throughput, as well as higher output amplitude, which relaxes considerably the design of the RF front end. This thesis presents a systematic design procedure and a scaling analysis of the non-linear pulse shaper. Moreover, in order to further increase the speed, a special PRF boost technique is proposed, which trades off speed and spectral efficiency for the spectral sidelobes level. Regarding the BPSK modulator, this work introduces the “Trigger Switching Fully Balanced Up-Conversion” topology, which avoids the use of power-hungry and distortion-prone analog circuits for the accurate inversion of the subnanosecond shaped pulses, as well as avoids the application of analog waveform switching to the baseband pulses, since the baseband modulation takes place before the generation of the pulses. The digital nature of the switching lends itself to high data rates, while the balanced paths of the topology ensure high modulation quality with minimal design effort. Wafer probing measurements confirmed the high performance of the baseband unit. The functionality of the transmitter was completed by the development of an RF front end which consists of a double balanced mixer, an LO buffer, a differential to single-ended (DtoSE) converter, and a power amplifier which is ready to drive a 50 Ohms load without requiring any off-chip components. The integrated transmitter, which incorporates the proposed baseband unit and the RF front end, was fabricated in 130 nm CMOS technology. The transmitter RFIC was directly attached to the system RF PCB using the Chip-on-Board packaging option. The First-Pass success of the system was ensured by paying particular attention to Signal/Power Integrity issues and following an IC-Package-PCB co-design procedure. The transmitter was measured up to 1.5 Gbps, which, to the author’s knowledge, was the highest speed amongst the competitive Multi-Band Impulse-Radio UWB implementations in the literature. The corresponding energy efficiency was 21 pJoule/bit and the Error Vector Magnitude (EVM) 5.5%, while the proposed transmitter improved the spectral sidelobes by over 10 dB. Exploiting the reconfigurability of the transmitter, this thesis presents the first measurements at multi-Mbps speeds that completely meet the final version of the European spectrum emission mask.