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Relevant bibliographies by topics / Adaptive Voltage Over-Scaling

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Journal articles
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Academic literature on the topic 'Adaptive Voltage Over-Scaling'

Author: Grafiati

Published: 14 March 2023

Last updated: 31 July 2025

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Journal articles on the topic "Adaptive Voltage Over-Scaling"

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Rizzo, Roberto G., Andrea Calimera, and Jun Zhou. "Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling." Integration 63 (September 2018): 220–31. http://dx.doi.org/10.1016/j.vlsi.2018.04.008.

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Rizzo, Roberto Giorgio, and Andrea Calimera. "Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection." Journal of Low Power Electronics and Applications 9, no. 2 (2019): 17. http://dx.doi.org/10.3390/jlpea9020017.

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Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that

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YEH, CHANG-CHING, KUEI-CHUNG CHANG, TIEN-FU CHEN, and CHINGWEI YEH. "ADAPTIVE PIPELINE VOLTAGE SCALING IN HIGH PERFORMANCE MICROPROCESSOR." Journal of Circuits, Systems and Computers 19, no. 08 (2010): 1817–34. http://dx.doi.org/10.1142/s0218126610007146.

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Deep pipeline has traditionally been widely used in high performance microprocessor. To allow continuous program execution, branch prediction provides a necessary method of speculatively executing instructions without compromising performance. However, branch misprediction penalty significantly impacts the performance of the deep pipeline processor. This study presents a new Adaptive Pipeline Voltage Scaling (APVS) technique to reduce branch misprediction penalty. For a likely mispredicted branch entering the processor, APVS begins increasing voltage and merging deep pipeline whereby shorter p

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KIROLOS, SAMI, and YEHIA MASSOUD. "DYNAMIC VOLTAGE SCALING CONTINUOUS ADAPTIVE-SIZE CELL DESIGN TECHNIQUE." Journal of Circuits, Systems and Computers 17, no. 05 (2008): 871–83. http://dx.doi.org/10.1142/s0218126608004630.

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In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply a

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Rizzo, Roberto G., Andrea Calimera, and Jun Zhou. "Corrigendum to“Approximate error detection-correction for efficient adaptive voltage Over-Scaling”[Integration 63 (2018) 220–231]." Integration 70 (January 2020): 159. http://dx.doi.org/10.1016/j.vlsi.2019.11.011.

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Abdullah, Md Anas, Mohamed B. Elamien, and M. Jamal Deen. "A 0.4 V CMOS Current-Controlled Tunable Ring Oscillator for Low-Power IoT and Biomedical Applications." Electronics 14, no. 11 (2025): 2209. https://doi.org/10.3390/electronics14112209.

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This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (IBIAS) modulation from 30–130 nA, while a four-stage configuration spans 388

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Lee, Kyongsu, and Jae-Yoon Sim. "An Implantable Bio-Signal Sensor SoC with Low-Standby-Power 8K-Bit SRAM for Continuous Long-Term Monitoring." Electronics 12, no. 10 (2023): 2317. http://dx.doi.org/10.3390/electronics12102317.

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Individualized treatment of chronic diseases opens up great opportunities for implantable biosensor systems capable of tracking vital signals over long periods of time. To this end, low-power techniques in standby mode and the efficient utilization of storage space will be important issues for the implementation of such rechargeable implants with a built-in memory. This paper presents key circuit techniques, including a leakage-current-based clock generator that eliminates the need for an internal reference clock source, a low-standby-power 8Kbit SRAM with negative wordline and dynamic supply

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Saleem, Omer, Muhammad Kazim, and Jamshed Iqbal. "Robust Position Control of VTOL UAVs Using a Linear Quadratic Rate-Varying Integral Tracker: Design and Validation." Drones 9, no. 1 (2025): 73. https://doi.org/10.3390/drones9010073.

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This article presents an optimal tracking controller retrofitted with a nonlinear adaptive integral compensator, specifically designed to ensure robust and accurate positioning of Vertical Take-Off and Landing (VTOL) Unmanned Aerial Vehicles (UAVs) that utilize contra-rotating motorized propellers for differential thrust generation. The baseline position controller is synthesized by employing a fixed-gain Linear Quadratic Integral (LQI) tracking controller that stabilizes position by tracking both state variations and pitch-axis tracking error integral, which adjusts the voltage to control eac

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Giannakopoulos, Georgios, Khushbu Mehboob Shaikh, and Abayomi Adegbenro. "VHDL-Based Low-Power Modem Design Using QPSK and IIR Filters on Xilinx FPGA." February 11, 2025. https://doi.org/10.20944/preprints202502.0761.v1.

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This paper presents a low-power modem realized using Quadrature Phase Shift Keying (QPSK) modulation and Infinite Impulse Response (IIR) filters on a Xilinx FPGA. The architecture, designed for low-power wireless communication in mobile handsets, IoT, and battery-powered applications, incorporates 16−bit fixed-point IIR filters with power consumption of 40 mW. Adaptive voltage scaling reduces energy by another 15%, and clock gating and Dynamic Voltage Scaling (DVS) reduce total power consumption by up to 30%. Hardware-in-the-Loop (HIL) Bit Error Rate (BER) testing and in-situ power measu

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Chafi, Safia Amina, and Mohammed Kamal Benhaoua. "Energy Harvesting Deadline Monotonic Approach for Real-time Energy Autonomous Systems." Scalable Computing: Practice and Experience 25, no. 6 (2024). http://dx.doi.org/10.12694/scpe.v25i6.2670.

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This paper presents an innovative scheduling algorithm designed specifically for real-time energy harvesting systems, with a primary focus on minimizing energy consumption and extending the battery's lifespan. The algorithm employs a fixed priority assignment which is the deadline monotonic policy, we have chosen it for its optimality and superior performance compared to other fixed priority scheduling methods. To achieve a balance between energy efficiency and system performance, we incorporated a DVFS (Dynamic Voltage and Frequency Scaling) technique into the algorithm. This adaptive approac

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Dissertations / Theses on the topic "Adaptive Voltage Over-Scaling"

1

RIZZO, ROBERTO GIORGIO. "Energy-Accuracy Scaling in Digital ICs: Static and Adaptive Design Methods and Tools." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2743228.

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Conference papers on the topic "Adaptive Voltage Over-Scaling"

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Krause, P. K., and I. Polian. "Adaptive voltage over-scaling for resilient applications." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763153.

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Rizzo, Roberto Giorgio, and Andrea Calimera. "Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling." In 2017 New Generation of CAS (NGCAS). IEEE, 2017. http://dx.doi.org/10.1109/ngcas.2017.75.

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Groo, LoriAnne, Howard Chung, Ayoub Yari Boroujeni, Anahita Emami, Marwan Al-Haik, and Michael Philen. "Characterization of ZnO Piezoelectric Nanowires in Energy Harvesting for Fiber-Reinforced Composites." In ASME 2015 Conference on Smart Materials, Adaptive Structures and Intelligent Systems. American Society of Mechanical Engineers, 2015. http://dx.doi.org/10.1115/smasis2015-9008.

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Structural health monitoring can enhance reliability, increase safety, and decrease maintenance costs by detecting damage at an early stage. By taking advantage of the electromechanical coupling, piezoelectric materials have the potential to harvest energy from ambient vibration sources to provide low-power electricity for self-powered electronic devices. In comparison with other piezoelectric transducers, zinc oxide (ZnO) nanowires carry the added advantages of structural flexibility, lower cost, compactness, and lighter weight. In this study, the energy harvesting capabilities of nanoscale Z

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