Relevant bibliographies by topics / Adaptive voltage scaling

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Adaptive voltage scaling'

Author: Grafiati
Published: 4 June 2021
Last updated: 11 June 2025

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Journal articles on the topic "Adaptive voltage scaling"

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Elgebaly, M., and M. Sachdev. "Variation-Aware Adaptive Voltage Scaling System." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 5 (2007): 560–71. http://dx.doi.org/10.1109/tvlsi.2007.896909.

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De Vos, Julien, Denis Flandre, and David Bol. "Pushing Adaptive Voltage Scaling Fully on Chip." Journal of Low Power Electronics 8, no. 1 (2012): 95–112. http://dx.doi.org/10.1166/jolpe.2012.1175.

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YEH, CHANG-CHING, KUEI-CHUNG CHANG, TIEN-FU CHEN, and CHINGWEI YEH. "ADAPTIVE PIPELINE VOLTAGE SCALING IN HIGH PERFORMANCE MICROPROCESSOR." Journal of Circuits, Systems and Computers 19, no. 08 (2010): 1817–34. http://dx.doi.org/10.1142/s0218126610007146.

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Deep pipeline has traditionally been widely used in high performance microprocessor. To allow continuous program execution, branch prediction provides a necessary method of speculatively executing instructions without compromising performance. However, branch misprediction penalty significantly impacts the performance of the deep pipeline processor. This study presents a new Adaptive Pipeline Voltage Scaling (APVS) technique to reduce branch misprediction penalty. For a likely mispredicted branch entering the processor, APVS begins increasing voltage and merging deep pipeline whereby shorter pipeline length permits less branch misprediction penalty. Once the branch is resolved, the merged stages are split and the supply voltage is reduced again. With dedicated shorter pipeline length within each branch misprediction, APVS achieves great performance improvement. The evaluation of APVS in a 13-stage superscalar processor with benchmarks from SPEC2000 applications shows a performance improvement (between 3–12%, average 8%) over baseline processor that does not exploit APVS.
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KIROLOS, SAMI, and YEHIA MASSOUD. "DYNAMIC VOLTAGE SCALING CONTINUOUS ADAPTIVE-SIZE CELL DESIGN TECHNIQUE." Journal of Circuits, Systems and Computers 17, no. 05 (2008): 871–83. http://dx.doi.org/10.1142/s0218126608004630.

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In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.
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Sung-Yong Bang, Kwanhu Bang, Sungroh Yoon, and Eui-Young Chung. "Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, no. 9 (2009): 1334–47. http://dx.doi.org/10.1109/tcad.2009.2024706.

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Luo, Ping, Dongjun Wang, and Xuanlin Peng. "An Adaptive Voltage Scaling Buck Converter with Preset Circuit." Chinese Journal of Electronics 28, no. 2 (2019): 229–36. http://dx.doi.org/10.1049/cje.2019.01.007.

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WOLPERT, DAVID, and PAUL AMPADU. "ADAPTIVE DELAY CORRECTION FOR RUNTIME VARIATION IN DYNAMIC VOLTAGE SCALING SYSTEMS." Journal of Circuits, Systems and Computers 17, no. 06 (2008): 1111–28. http://dx.doi.org/10.1142/s0218126608004861.

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Temperature and voltage fluctuations affect delay sensitivity differently, as supply voltage is reduced. These differences make runtime variations particularly difficult to manage in dynamic voltage scaling systems, which adjust supply voltage in accordance with the required operating frequency. To include process variation in current table-lookup methods, a worst-case process is typically assumed. We propose a new method that takes process variation into account and reduces the excessive runtime variation guardbands. Our approach uses a ring oscillator to generate baseline frequencies, and employs a guardband lookup table to offset this baseline. The new method ensures robust operation and reduces power consumption by up to 20% compared with a method that assumes worst-case process variation in filling a lookup table.
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Rizzo, Roberto G., Andrea Calimera, and Jun Zhou. "Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling." Integration 63 (September 2018): 220–31. http://dx.doi.org/10.1016/j.vlsi.2018.04.008.

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Niemann, Christoph, Munawar Ali, Obaid Ullah Shah, Jakob Heller, and Dirk Timmermann. "Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization." Integration 75 (November 2020): 30–39. http://dx.doi.org/10.1016/j.vlsi.2020.05.006.

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Chan, Tuck-Boon, Wei-Ting Jonas Chan, and Andrew B. Kahng. "On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 10 (2014): 2920–30. http://dx.doi.org/10.1109/tcsi.2014.2321204.

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Dissertations / Theses on the topic "Adaptive voltage scaling"

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Shiomi, Jun. "Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits." Kyoto University, 2017. http://hdl.handle.net/2433/228252.

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Akgul, Yeter. "Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20132/document.

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Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante. C'est une des raisons pour lesquelles de nouvelles technologies ont été développées, notamment celles basées sur Silicium sur Isolant (SOI). Par ailleurs, la généralisation des architectures complexes de type multi-cœurs, accentue le problème de gestion de la consommation à grain-fin. Les technologies CMOS FD-SOI offrent de nouvelles opportunités pour la gestion de la consommation en permettant d'ajuster, outre les paramètres usuels que sont la tension d'alimentation et la fréquence d'horloge, la tension de body bias. C'est dans ce contexte que ce travail étudie les nouvelles possibilités offertes et explore des solutions innovantes de gestion dynamique de la tension d'alimentation, fréquence d'horloge et tension de body bias afin d'optimiser la consommation énergétique des systèmes sur puce. L'ensemble des paramètres tensions/fréquence permettent une multitude de points de fonctionnement, qui doivent satisfaire des contraintes de fonctionnalité et de performance. Ce travail s'intéresse donc dans un premier temps à une problématique de conception, en proposant une méthode d'optimisation du placement de ces points de fonctionnement. Une solution analytique permettant de maximiser le gain en consommation apporté par l'utilisation de plusieurs points de fonctionnement est proposée. La deuxième contribution importante de cette thèse concerne la gestion dynamique de la tension d'alimentation, de la fréquence et de la tension de body bias, permettant d'optimiser l'efficacité énergétique en se basant sur le concept de convexité. La validation expérimentale des méthodes proposées s'appuie sur des échantillons de circuits réels, et montre des gains en consommation moyens allant jusqu'à 35%<br>Beyond 28nm CMOS BULK technology node, some limits have been reached in terms of performance improvements. This is mainly due to the increasing power consumption. This is one of the reasons why new technologies have been developed, including those based on Silicon-On-Insulator (SOI). Moreover, the standardization of complex architectures such as multi-core architectures emphasizes the problem of power management at fine-grain. FD-SOI technologies offer new power management opportunities by adjusting, in addition to the usual parameters such as supply voltage and clock frequency, the body bias voltage. In this context, this work explores new opportunities and searches novel solutions for dynamically manage supply voltage, clock frequency and body bias voltage in order to optimize the power consumption of System on Chip.Adjusting supply voltage, frequency and body bias parameters allows multiple operating points, which must satisfy the constraints of functionality and performance. This work focuses initially at design time, proposing a method to optimize the placement of these operating points. An analytical solution to maximize power savings achieved through the use of several operating points is provided. The second important contribution of this work is a method based on convexity concept to dynamically manage the supply voltage, the frequency and the body bias voltage so as to optimize the energy efficiency. The experimental results based on real circuits show average power savings reaching 35%
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Liu, Chun-Wen, and 劉仲文. "Adaptive Voltage Scaling for Discrete Cosine Transform." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/00937421266683497648.

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碩士<br>國立交通大學<br>電子工程系所<br>96<br>In the modern digital IC system, adaptive voltage scaling is the most efficient technology for low power design. A new variable voltage generator (VVG) has been proposed in this paper. Five voltage levels ranged from 0.8V to 1.2V can be generated. An adaptive voltage scaling controller has been developed to fit the VVG to form an adaptive voltage scaling control system. In stead of the off-chip DC-DC converter which is often used in voltage regulation, the on-chip VVG takes an important roll in this system. Discrete Cosine Transform (DCT) has become one of the widely used transform techniques in digital signal processing. The adaptive voltage scaling system has been applied to DCT and reduces at most 45% power consumption of DCT. All simulations are implemented in TSMC0.13-μm CMOS technology.
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CHANG, YU-SIAN, and 張裕銑. "Variation-Resilient Adaptive Voltage Scaling Control Loop Design." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/yckr6a.

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碩士<br>國立中正大學<br>資訊工程研究所<br>105<br>Traditionally, to estimate one of AVS control parameters of AVS results takes large simulation time, pre-error AVS system have been proposed to simplify the procedure of estimate AVS result, which just simulated delay distributions at different voltage for once with Markov chain to estimate all set of AVS control parameters of AVS result. In this paper, we evaluate pre-error AVS system in 90nm CMOS, using delay distributions of 100,000 patterns and 20mV step voltage and Markov chain to estimate the AVS result which the error of RMSE of voltage scatter with AVS in 90nm CMOS is 34.86%, but the error of RMSE of voltage scatter with AVS in 90nm CMOS is 2.78% while increasing the patterns to 10,000,000 patterns, the reason of this difference is the tail information of delay distribution is not enough (i.e. limit precision). We proposed using delay distributions of 1,000 patterns with Interpolate Gaussian mathematic model to replace delay distributions of 100,000 patterns to estimate AVS results which the error of RMSE of voltage scatter with AVS in 90nm CMOS is 5.68%. We also analysis the sensitivity of AVS control parameters (N, nlimit↓, nlimit↑) which the result is N> nlimit↓> nlimit↑, therefore, fixed n_lb=1, n_ub=N*2% and adjust N to get the difference error rate from control parameters, and evaluate the adjust method in 90nm CMOS to get the error rate from 10-2 to 10-5.
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Chou, Hong-Lin, and 周宏霖. "Study on Instruction Cache Design with Adaptive Voltage Scaling." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/uqtjqc.

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碩士<br>國立中正大學<br>資訊工程研究所<br>100<br>Adaptive voltage scaling (AVS) has been successfully applied in energy-efficient microprocessor designs. However, the technique has not been widely used in memory (SRAM) designs. This thesis tries to adopt the AVS technique (especially with voltage overscaling ) in embedded memory systems. While encountering data losses due to overscaling the supply voltage of instruction caches, the cache line can be discarded & the instruction can be fetched from the next-level memory. The situation in regarded as “reliability miss” is our analysis. The optimal supply voltage is studied, considering the extra memory accessed due to reliability misses. We have extended traditional trace-based simulations for our evaluations. The CACTI model & a 65nm testchip are used for energy estimation. Beyond the trace-based simulations, FPGA environment has also been constructed for evaluating real workload.
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Tsou, Jie-Wen, and 鄒文傑. "Digital Low Dropout Regulator with Anti-PVT-Variation Technique for Dynamic Voltage Scaling and Adaptive Voltage Scaling Multi-core Processor." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/65537854981781684887.

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碩士<br>國立交通大學<br>電控工程研究所<br>105<br>Multi-core processor have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. To maximize the energy efficiency of a processor when using DVS and AVS, it is highly desirable to independently control the supply and the clock frequency for each core. As the number of cores grows, fast, cost-effective, and energy-efficient DVS and AVS schemes become prohibitively challenging to implement using off-chip switching regulators. Therefore, the fully integrated digital low-dropout regulators (DLDO) are used to achieve fast, cost-effective, and energy-efficient DVS and AVS schemes. However, the DLDO regulator has current quantization error (CQE) which produces an undesirable output voltage ripple. Moreover, the CQE of DLDO regulator is affected by process, voltage and temperature (PVT) variations, which represents the output voltage ripple of DLDO regulator depends on PVT variations. Recently, some techniques are proposed to remove CQE and thus reduce the output voltage ripple. Unfortunately, there always is a tradeoff between output voltage ripple and load regulation, which both degrade the performance of processor. As a result, the DLDO regulator with anti-PVT-variation technique is proposed in this thesis for resolve the aforementioned issues and this technique can minimize the CQE under any PVT variations and maintain good load regulation simultaneously.
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Park, Junyoung. "Self-tuning dynamic voltage scaling techniques for processor design." 2013. http://hdl.handle.net/2152/22989.

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The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows for almost cubic reduction in dynamic power consumption with only a nearly linear reduction in performance. Due to its virtue, the DVS technique has been used for the two main purposes: energy-saving and temperature reduction. However, recently, a Dynamic Voltage Scaled (DVS) processor has lost its appeal as process technology advances due to the increasing Process, Voltage and Temperature (PVT) variations. In order to make a processor tolerant to the increasing uncertainties caused by such variations, processor designers have used more timing margins. Therefore, in a modern-day DVS processor, reducing voltage requires comparatively more performance degradation when compared to its predecessors. For this reason, this technique has a lot of room for improvement for the following facts. (a) From an energy-saving viewpoint, excessive margins to account for the worst-case operating conditions in a DVS processor can be exploited because they are rarely used during run-time. (b) From a temperature reduction point of view, accurate prediction of the optimal performance point in a DVS processor can increase its performance. In this dissertation, we propose four performance improvement ideas from two different uses of the DVS technique. In regard to the DVS technique for energy-saving, in this dissertation, we introduce three different types of margin reduction (or margin decision) techniques. First, we introduce a new indirect Critical Path Monitor (CPM) to make a conventional DVS processor adaptive to its given environment. Our CPM is composed of several Slope Generators, each of which generates similar voltage scaling slopes to those of potential critical paths under a process corner. Each CPR in the Slope Generator tracks the delays of potential critical paths with minimum difference at any condition in a certain voltage range. The CPRs in the same Slope Generator are connected to a multiplexer and one of them is selected according to a current voltage level. Calibration steps are done by using conventional speed-binning process with clock duty-cycle modulation. Second, we propose a new direct CPM that is based on a non-speculative pre-sampling technique. A processor that is based on this technique predicts timing errors in the actual critical paths and undertakes preventive steps in order to avoid the timing errors in the event that the timing margins fall below a critical level. Unlike direct CPM that uses circuit-level speculative operation, although the shadow latch can have timing error, the main Flip-Flop (FF) of our direct CPM never fails, guaranteeing always-correct operation of the processor. Our non-speculative CPM is more suitable for high-performance processor designs than the speculative CPM in that it does not require original design modification and has lower power overhead. Third, we introduce a novel method that determines the most accurate margin that is based on the conventional binning process. By reusing the hold-scan FFs in a processor, we reduce design complexity, minimize hardware overhead and increase error detecting accuracy. Running workloads on the processor with Stop-Go clock gating allows us to find which paths have timing errors during the speed binning steps at various, fixed temperature levels. From this timing error information, we can determine the different maximum frequencies for diverse operating conditions. This method has high degree of accuracy without having a large overhead. In regard to the DVS technique for temperature reduction, we introduce a run-time temperature monitoring scheme that predicts the optimal performance point in a DVS processor with high accuracy. In order to increase the accuracy of the optimal performance point prediction, this technique monitors the thermal stress of a processor during run-time and uses several Look-Up Tables (LUTs) for different process corners. The monitoring is performed while applying Stop-Go clock gating, and the average EN value is calculated at the end of the monitoring time. Prediction of the optimal performance point is made using the average EN value and one of the LUTs that corresponds to the process corner under which the processor was manufactured. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature within threshold temperature.<br>text
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Chun-TaChen and 陳俊達. "Design of A Variation-Aware Adaptive Voltage Scaling Technique and Its Applications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/17989314897813431608.

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Liu, Shih-Hao, and 劉士豪. "Hardware Realization and FPGA Verification of Adaptive Voltage Scaling on Digital Filters." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/3w53qj.

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碩士<br>國立中正大學<br>資訊工程研究所<br>103<br>Adaptive voltage scaling (AVS) has already been successfully applied in low-power processor and datapath designs. This study tries to apply AVS in memory designs, 78% power reduction has been observed in a lookup-table (LUT)-based digital filter, where 6 extra SECDED bits have been implemented for 16-bit LUT entries. 'Zero-count'-based error detection and an approximate computing scheme has been designed for the specific 'slow cells' in modern ultra-low-voltage SRAM macros. The design has already been verified on Xilinx Zynq FPGA.
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Huang, Shao-Cheng, and 黃劭丞. "Behavior Analysis and Modeling of Adaptive Voltage Scaling for digital image processing." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/g97c63.

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碩士<br>國立中正大學<br>電機工程研究所<br>107<br>The method proposed in the literatures of adaptive voltage scaling at present is rarely designed for the characteristic of the human eyes on the image.Considering the chraceteristics of the images is real-time , Unable to analyze the image quality that has been output , apply the determined pressure regulation mechanism to the image thatcomes immediately.And voltage scaling does not just discuss the error rate of the entire picture.In order to avoid the errors being all located in certain areas, virtual hardware environmental value is used beforehand to simulate the the quality of the video after the voltage scaling , Flip the output value of the image processing circuit and then analyze Image quality to decide the voltage scaling mechanism. In this paper, the behavior analysis and modeling of applying adaptive voltage scaling to digital image processing are proposed.When there are other variations that cause timing error, our paper discusses how to adjust the voltage to make up for the delay caused by each variation.The occurrence of timing error can lead to incorrect data and then causes data defects. Therefore, it is critical to decide the voltage scaling mechanism of image processing to work with the method of remedying the defective image data. Index Terms -- AVS , human vision system
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Books on the topic "Adaptive voltage scaling"

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Wirnshofer, Martin. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013.

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Wirnshofer, Martin. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4.

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Jain, Saurabh, Longyang Lin, and Massimo Alioto. Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-38796-9.

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Variationaware Adaptive Voltage Scaling For Digital Cmos Circuits. Springer, 2013.

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Wirnshofer, Martin. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer, 2015.

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Wirnshofer, Martin. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer, 2013.

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Alioto, Massimo, Saurabh Jain, and Longyang Lin. Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling: From the Clock Path to the Data Path. Springer, 2020.

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Book chapters on the topic "Adaptive voltage scaling"

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Clark, Lawrence T., Franco Ricci, and William E. Brown. "Dynamic Voltage Scaling with the XScale Embedded Microprocessor." In Adaptive Techniques for Dynamic Processor Optimization. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76472-6_6.

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Wirnshofer, Martin. "Adaptive Voltage Scaling by In-situ Delay Monitoring." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_4.

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Meijer, Maurice, and José Pineda Gyvez. "Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning." In Adaptive Techniques for Dynamic Processor Optimization. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-76472-6_2.

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Wirnshofer, Martin. "Introduction." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_1.

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Wirnshofer, Martin. "Sources of Variation." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_2.

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Wirnshofer, Martin. "Related Work." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_3.

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Wirnshofer, Martin. "Design of In-situ Delay Monitors." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_5.

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Wirnshofer, Martin. "Modeling the AVS Control Loop." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_6.

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Wirnshofer, Martin. "Evaluation of the Pre-Error AVS Approach." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_7.

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Wirnshofer, Martin. "Conclusion." In Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6196-4_8.

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Conference papers on the topic "Adaptive voltage scaling"

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Mhira, S., V. Huard, A. Benhassain, et al. "Dynamic adaptive voltage scaling in automotive environment." In 2017 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2017. http://dx.doi.org/10.1109/irps.2017.7936279.

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Krause, P. K., and I. Polian. "Adaptive voltage over-scaling for resilient applications." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763153.

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Hashimoto, Masanori, and Yutaka Masuda. "MTTF-aware design methodology for adaptive voltage scaling." In 2018 China Semiconductor Technology International Conference (CSTIC). IEEE, 2018. http://dx.doi.org/10.1109/cstic.2018.8369326.

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Malavasi-Mora, Andres, and Renato Rimolo-Donadio. "Voltage Drop Mitigation by Adaptive Voltage Scaling using Clock-Data Compensation." In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). IEEE, 2020. http://dx.doi.org/10.1109/lascas45839.2020.9069016.

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Zhao, Xia, Yao Guo, and Xiangqun Chen. "Transaction-based adaptive dynamic voltage scaling for interactive applications." In the 14th ACM/IEEE international symposium. ACM Press, 2009. http://dx.doi.org/10.1145/1594233.1594294.

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Rathnala, Prasanthi, Ahmad Kharaz, and Tim Wilmshurst. "An efficient adaptive voltage scaling using delay monitor unit." In 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2015. http://dx.doi.org/10.1109/prime.2015.7251346.

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Gupta, Ankur, Rajat Chauhan, Vinod Menezes, Vikas Narang, and H. M. Roopashree. "A Robust Level-Shifter Design for Adaptive Voltage Scaling." In 2008 21st International Conference on VLSI Design. IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.61.

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Chang, Kuo-Chiang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, and Yuan-Hua Chu. "MORAS: An energy-scalable system using adaptive voltage scaling." In 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2018. http://dx.doi.org/10.1109/vlsi-dat.2018.8373243.

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Kirolos, Sami, and Yehia Massoud. "Adaptive SRAM design for dynamic voltage scaling VLSI systems." In 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/mwscas.2007.4488788.

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Chan, Tuck-Boon, Wei-Ting Jonas Chan, and Andrew B. Kahng. "Impact of Adaptive Voltage Scaling on Aging-Aware Signoff." In Design Automation and Test in Europe. IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.340.

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