Relevant bibliographies by topics / ADC (Analog to Digital Converter)

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'ADC (Analog to Digital Converter)'

Author: Grafiati
Published: 5 June 2025
Last updated: 2 August 2025

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Journal articles on the topic "ADC (Analog to Digital Converter)"

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Nykyruy, L. I., R. V. Ilnytskyi, and M. F. Pavlyuk. "MODELING OF ANALOG-TO-DIGITAL SIGNAL CONVERTERS FOR SENSOR MICROSYSTEMS IN THE MICROWIND SOFTWARE." Sensor Electronics and Microsystem Technologies 21, no. 1 (2024): 29–35. http://dx.doi.org/10.18524/1815-7459.2024.1.300140.

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For the results of simulating the operation of analog-digital converters, we chose such a converter as the serial approximation ADC (SAR ADC). A sequential approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform to a discrete digital representation by binary search through all possible quantization levels before finally converging on a digital output for each conversion. There are three important blocks in the SAR ADC architecture: the sample and hold circuit (Sample and Hold, S/H), the comparator, and the SAR block. The topology and principle of o
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Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are
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Wang, Weihe, and Hongqi Yu. "Pipelined Memristive neural network analog-to-digital converter." Journal of Physics: Conference Series 2632, no. 1 (2023): 012004. http://dx.doi.org/10.1088/1742-6596/2632/1/012004.

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Abstract This paper designs a pipelined memristive neural network ADCs. Cascade the sub stages of memristive neural network ADC with pipeline structure to improve the conversion accuracy of memristive neural network ADC. First, the signal flow of the pipeline architecture is optimized, and the compatibility between the 4 bit memristive neural network ADC and the pipeline architecture is solved. Secondly, the application of random disturbance circuits in pipeline architecture was analyzed. Combining the calibration circuit with the pipeline DAC to reduce the power consumption of the calibration
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Bialek, J., A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, and T. Ussmueller. "Implementation of a digital trim scheme for SAR ADCs." Advances in Radio Science 11 (July 4, 2013): 227–30. http://dx.doi.org/10.5194/ars-11-227-2013.

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Abstract. Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the
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Anvekar, Dinesh K., and B. S. Sonde. "Programmable Nonlinear Adc: An Illustrative Example." International Journal of Electrical Engineering & Education 33, no. 3 (1996): 216–24. http://dx.doi.org/10.1177/002072099603300303.

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Programmable nonlinear ADC: an illustrative example Programmable nonlinear analog-to-digital conversion is a new topic in EE curricula. With a view to introducing the EE student to the concept of transfer characteristic programmability of an analog-to-digital converter (ADC), a memory-prefetch programmable nonlinear ADC is presented. The design, analytical evaluation, and experimental implementation for the ADC are described.
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Li, Donggen. "Comparative Study of High Speed ADCs." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 146–52. http://dx.doi.org/10.54097/hset.v27i.3731.

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With the development of information technology, analog-to-digital converter (ADC) is widely used. In products such as radar, ultra wideband communication system, high-performance digital oscilloscope and so on, the speed performance of analog-to-digital converter is usually the bottleneck of the whole system performance, so the research of high-speed ADC has attracted much attention. ADC is an interface circuit that converts analog signals into digital signals that can be processed by DSP. This paper will start with the basic knowledge of ADC, explain the general working process of ADC, introd
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Seo, Dong-Hwan, Sunghoon Cho, Jung-Gyun Kim, and Byung-Geun Lee. "A Self-Calibration of Capacitor Mismatch Error for Pipeline ADCs." Applied Sciences 13, no. 22 (2023): 12322. http://dx.doi.org/10.3390/app132212322.

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This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricate
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Laoudias, Costas, George Souliotis, and Fotis Plessas. "A High ENOB 14-Bit ADC without Calibration." Electronics 13, no. 3 (2024): 570. http://dx.doi.org/10.3390/electronics13030570.

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This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp,
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NING, NING, LING DU, HUA CHEN, SHUANGYI WU, QI YU, and YANG LIU. "A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC." Journal of Circuits, Systems and Computers 23, no. 01 (2014): 1450006. http://dx.doi.org/10.1142/s0218126614500066.

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A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals a
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Liu, Xiaolu, Jin Shao, Peng Zhang, Guoyu Cui, and Haifeng Qian. "Multi-channel and high-precision analog-to-digital converter chips for power grid detection." Journal of Physics: Conference Series 2584, no. 1 (2023): 012139. http://dx.doi.org/10.1088/1742-6596/2584/1/012139.

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Abstract This project focuses on the research of high-precision multi-channel analog-to-digital converter chips for power grid detection and system applications. There have been breakthroughs made in a series of key technologies, such as successive approximation ADC architecture, oversampling ADC architecture, and digital calibration technology. By combining it with multi-channel ADC to achieve high-precision multi-channel analog-to-digital converter design, it provides strong support for China to achieve autonomous and controllable high-precision multi-channel ADC chips and has extremely high
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Dissertations / Theses on the topic "ADC (Analog to Digital Converter)"

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Parsons, Colton A. "Variable Precision Tandem Analog-to-Digital Converter (ADC)." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1255.

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This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence. As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precis
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Orchanian, Shant. "Split Non-Linear Cyclic Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/324.

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Analog-to-Digital Converters (ADC's) are inherently optimized for linearity in order to produce an accurate digital representation of an analog voltage. The Cyclic ADC's linearity is limited by one of its components, the residue amplifier. The residue amplifier is used to amplify the error between the analog voltage and the digital decision by a gain of two in each cycle of a conversion. In previous designs, this was accomplished by using a compound op-amp with a large open loop gain for linearity, and negative feedback to achieve the gain of two. This thesis explores the use of a resistively
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Croughwell, Rosamaria. "A 16-b 10Msample/s Split-Interleaved Analog to Digital Converter." Digital WPI, 2007. https://digitalcommons.wpi.edu/etd-theses/974.

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"This work describes the integrated circuit design of a 16-bit, 10Msample/sec, combination ‘split’ interleaved analog to digital converter. Time interleaving of analog to digital converters has been used successfully for many years as a technique to achieve faster speeds using multiple identical converters. However, efforts to achieve higher resolutions with this technique have been difficult due to the precise matching required of the converter channels. The most troublesome errors in these types of converters are gain, offset and timing differences between channels. The ‘split ADCâ
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Carter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.

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This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage str
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Spetla, Hattie. "Split Cyclic Analog to Digital Converter Using A Nonlinear Gain Stage." Digital WPI, 2009. https://digitalcommons.wpi.edu/etd-theses/1014.

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"Previous implementations of digital background calibration for cyclic ADCs have required linear amplifier behavior in the gain stage for accurate correction. Correction is digital decoding of ADC outputs to determine the original ADC input. Permitting nonlinearity in the gain stage of the ADC allows for less demanding amplifier design requirements, reducing power and size. However this requires a method of determining the value of this variable gain during digital correction. Look up tables (LUTs,) are an effective and efficient method of compensating for analog circuit imperfections. The LUT
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Levski, Dimitrov Deyan. "A Cyclic Analog to Digital Converter for CMOS image sensors." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103193.

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The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to
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Tchambake, Yapti Kelly. "Wideband Analog-to-Digital Converter (ADC) design for power amplifiers linearization." Electronic Thesis or Diss., Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLT047.

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De nos jours, la consommation d’énergie devient un des principaux défis à surmonter dans le développement des réseaux de communications mobiles. L’amplificateur de puissance est le composant le plus gourmand en énergie dans les stations de base. La cinquième génération de téléphonie mobile de part ses larges bandes de communication et ses modulations complexes augmente encore plus les contraintes sur l’amplificateur de puissance. Pour palier ce problème, il est courant de faire appel à des techniques de pré-distorsion. Une contrainte importante dans la mise en oeuvre de cette technique est la
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Majidi, Rabeeh. "DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/275.

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With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing s
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Radhakrishnan, Venkataraman. "Design of a low power analog to digital converter in a 130nmCMOS technology." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72700.

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Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the advancement in the analog and mixed signalcircuit design.Analog to digital converter (ADC) is an essential part in a modernreceiver system. Its development is driven by the progress of CMOStechnologies with an aim to reduce area and power consumption. In thearea of RF integrated circuits for wireless application low operationalvoltage, and less current consumption are the central aspects of thedesign. The aim of this master thesis is the d
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Aust, Carrie Ellen. "A Low-Power, Variable-Resolution Analog-to-Digital Converter." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/33737.

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Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary
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Books on the topic "ADC (Analog to Digital Converter)"

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Motorola. Modular microcontroller family ADC analog-to-digital converter reference manual. Motorola, 1993.

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Ahmed, Imran. Pipelined ADC design and enhancement techniques. Springer, 2010.

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Ruiz-Amaya, Jesus. Device-level modeling and synthesis of high-performance pipeline ADCs. Springer, 2011.

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(Firm), Motorola. QADC: Queued analog-to-digital converter reference manual. Motorola, 1995.

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Wrixon, Adrian. D-A converter test optimisation. University College Dublin, 1996.

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Uster, Markus. Current-mode analog-to-digital converter for array implementation. Hartung-Gorre, 2003.

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Singor, Henry W. High performance current scaling digital-to-analog converter design. National Library of Canada, 1990.

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Xin, Jane Q. A high-precision digital-to-analog converter for tuning applications. National Library of Canada = Bibliothèque nationale du Canada, 1992.

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Santos, Mauro, Jorge Guilherme, and Nuno Horta. Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-15978-8.

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An, Wei. An 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter. National Library of Canada, 2000.

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Book chapters on the topic "ADC (Analog to Digital Converter)"

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Gadre, Dhananjay V., and Sarthak Gupta. "Analog to Digital Converter (ADC)." In Getting Started with Tiva ARM Cortex M4 Microcontrollers. Springer India, 2017. http://dx.doi.org/10.1007/978-81-322-3766-2_14.

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Asadi, Farzin. "Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC)." In Essentials of Arduino™ Boards Programming. Apress, 2023. http://dx.doi.org/10.1007/978-1-4842-9600-4_3.

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Ohnhäuser, Frank. "Advanced SAR ADC Design." In Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Converters. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-47020-6_3.

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. "Sub-ADC Architectures for Time-interleaved ADCs." In Time-interleaved Analog-to-Digital Converters. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_3.

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Karmakar, Supriya. "Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) Using Quantum Dot Gate Field-Effect Transistor (QDGFET)." In Novel Three-state Quantum Dot Gate Field Effect Transistor. Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1635-3_7.

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. "Implementation of a High-speed Time-interleaved ADC." In Time-interleaved Analog-to-Digital Converters. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_4.

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Kutre, Tejaswini Jayawant, Sujata N. Patil, Sheela Kore, and V. M. Aparanji. "Advanced Architecture of Analog to Digital Converter Derived from Half Flash ADC." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2281-7_14.

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Gamad, Radheshyam. "Dynamic test technique of analog to digital converter (ADC) for 6G communication." In 6G Communication Network. CRC Press, 2024. http://dx.doi.org/10.1201/9781003522003-19.

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Bajdechi, Ovidiu, and Johan H. Huijsing. "Sigma-Delta ADC for Audio Applications." In Systematic Design of Sigma-Delta Analog-to-Digital Converters. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-7946-7_6.

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Figueiredo, Michael, João Goes, and Guiomar Evans. "Application of Circuit Enhancement Techniques to ADC Building Blocks." In Reference-Free CMOS Pipeline Analog-to-Digital Converters. Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-3467-2_4.

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Conference papers on the topic "ADC (Analog to Digital Converter)"

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Shao, Linbo, Joseph G. Thomas, Bernadeta R. Srijanto, Kevin C. Lester, Ivan I. Kravchenko, and Yizheng Zhu. "Electro-optic Analog-to-Digital Converter Using Spectral Interferometry." In CLEO: Science and Innovations. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_si.2024.sw3r.8.

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We demonstrate an optical analog-to-digital converter (ADC) leveraging spectral interferometry of an integrated electro-optic Mach-Zehnder interferometer on thin-film lithium niobate. The ADC features a high dynamic range of 118 dB/Hz with a 3-Vpp input range.
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Narayanan, V., R. Jain, and T. Senter. "Radiation Effects Characterization of TI ADC128S102-SEP Analog to Digital Converter (ADC) (July 2024)." In 2024 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with 2024 NSREC). IEEE, 2024. http://dx.doi.org/10.1109/redw61286.2024.10759222.

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Teja, Nagavelly Tarun, Kondapaka Karthikeya, and J. Ajayan. "Reliability and Power Supply Scaling Effects on Nanoscale Comparators for Future Flash/SAR Analog to Digital Converter (ADC) Applications." In 2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT). IEEE, 2024. http://dx.doi.org/10.1109/icccnt61001.2024.10725836.

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Angerbauer, Stefan, Franz Enzenhofer, Michael Gattringer, Andreas Springer, and Werner Haselmayr. "A Molecular Analog-to-Digital Converter." In GLOBECOM 2024 - 2024 IEEE Global Communications Conference. IEEE, 2024. https://doi.org/10.1109/globecom52923.2024.10901464.

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Prusten, Mark J., and Arthur F. Gmitro. "An Optical Flash Analog to Digital Converter." In Optical Computing. Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.otue3.

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Fast analog-to-digital (A/D) converters are important in a number of applications. Several systems have been proposed for fast A/D converters using optical technology1-4. The most common types of converters are the successive approximation and Flash converters. In a Flash converter there is a separate comparator for each possible output bit code. Each comparator is biased with a reference level that is a specific increment of the full scale value. Since comparators in a Flash converter operate in parallel, this architecture is intrinsically fast. However, as the accuracy requirements increase,
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Larson, Eric D. "Serial pixel analog-to-digital converter (ADC)." In OPTO, edited by Shibin Jiang, Michel J. F. Digonnet, John W. Glesener, and J. Christopher Dries. SPIE, 2010. http://dx.doi.org/10.1117/12.845801.

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Abhirami, S., D. Vishnu, S. Sreelal, A. Sajeena, and Anu Assis. "Second-order Oversampled Delta-sigma Analog to Digital Converter." In 2nd International Conference on Modern Trends in Engineering Technology and Management. AIJR Publisher, 2023. http://dx.doi.org/10.21467/proceedings.160.18.

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The Delta Sigma modulation technology has been around for a while, but because of technological advancements, the devices are now more widely used and feasible. The work proposes a multi-bit Delta Sigma ADC of second order having a very low power consumption. MATLAB Simulink is used to develop both the Delta Sigma ADCs of first and second order and the digital output is passed through a digital filter to recreate the original signal. According to simulation results, at 100 KHz frequency of output sampling, the Delta-Sigma modulator exhibits a Spurious Free Dynamic Range of 95.38 dB, and also i
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Takhti, Mohammad, Amir M. Sodagar, and Reza Lotfi. "Domino ADC: A novel analog-to-digital converter architecture." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537633.

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Daryoush, Afshin S., Kai Wei, and Tianchi Sun. "All Optical GSPS Analog-Digital Converters (ADC)." In 2019 IEEE Photonics Conference (IPC). IEEE, 2019. http://dx.doi.org/10.1109/ipcon.2019.8908296.

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Yip, T. Gary, and Elizabeth B. Nadworny. "A Successive Approximation ADC Simulation Project." In ASME 1992 International Computers in Engineering Conference and Exposition. American Society of Mechanical Engineers, 1992. http://dx.doi.org/10.1115/cie1992-0067.

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Abstract This paper describes a three week long project designed for first year graduate students in mechanical engineering taking a course in Modern Instrumentation. The project entails constructing a successive approximation analog-to-digital converter without a controller, developing a control sequence, and implementing it to produce a digital representation of an analog input voltage. The course is made up of a series of laboratory activities that start with the fundamentals of equipment control and data acquisition, then increase in difficulty by requiring students to develop systems and
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Reports on the topic "ADC (Analog to Digital Converter)"

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Bowers, M., B. Deri, R. Haigh, et al. LDRD final report: photonic analog-to-digital converter (ADC) technology. Office of Scientific and Technical Information (OSTI), 1999. http://dx.doi.org/10.2172/13923.

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Morris, Frank. Analog-to-Digital Converter. Defense Technical Information Center, 1989. http://dx.doi.org/10.21236/ada268538.

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Morris, Frank. Analog-to-Digital Converter. Defense Technical Information Center, 1987. http://dx.doi.org/10.21236/ada268539.

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Morris, Frank. Analog-to-Digital Converter. Defense Technical Information Center, 1987. http://dx.doi.org/10.21236/ada268540.

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Morris, Frank. Analog-to-Digital Converter. Defense Technical Information Center, 1991. http://dx.doi.org/10.21236/ada268541.

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Morris, Frank. Analog-to-Digital Converter. Defense Technical Information Center, 1991. http://dx.doi.org/10.21236/ada268542.

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Morris, Frank. Analog-to-Digital Converter. Defense Technical Information Center, 1992. http://dx.doi.org/10.21236/ada268545.

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8

Morris, Frank, and W. R. Wisseman. Analog-to-Digital Converter. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada268835.

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9

Morris, Frank, and W. R. Wisseman. Analog-to-Digital Converter. Defense Technical Information Center, 1990. http://dx.doi.org/10.21236/ada268836.

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10

Morris, Frank, and W. R. Wisseman. Analog-to-Digital Converter. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada268837.

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