Dissertations / Theses on the topic 'Adder design'

Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will improve on theoretical limit. The major scope of this proposed design is to increase the speed of carry generation between intermediate blocks of Carry select Adder (CSA) by introducing fast multiple clock Domino Manchester carry chain (MCC) that generates carry outputs. This design technique will have some advantages compared to pre-existing implementations in operating speed and power delay product. Simulation has been done using GPDK (Generic Process Design Kits) technology using cadence virtuoso. Thus the proposed technique provides advantages over pre-existing techniques in terms of operating speed.

Implementation of the polyphase decomposed FIR filter structure involves two steps; the generation of the partial products and the efficient reduction of the generated partial products. The partial products are generated by a constant multiplication of the filter coefficients with the input data and the reduction of the partial products is done by building a pipelined adder tree using FAs and HAs. To improve the speed and to reduce the complexity of the reduction tree a4:2 counter is introduced into the reduction tree. The reduction tree is designed using a bit-level optimized ILP problem which has the objective function to minimize the overall cost of the hardware used. For this purpose the layout design for a 4:2 counter has been developed and the cost function has been derived by comparing the complexity of the design against a standard FA design. The layout design for a 4:2 counter is implemented in a 65nm process using static CMOS logic style and DPL style. The average power consumption drawn from a 1V power supply, for the static CMOS design was found to be 16.8μWand for the DPL style it was 12.51μW. The worst case rise or fall time for the DPL logic was 350ps and for the static CMOS logic design it was found to be 260ps. The usage of the 4:2 counter in the reduction tree infused errors into the filter response, but it helped to reduce the number of pipeline stages and also to improve the speed of the partial product reduction.

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, Sept. 2001.
Thesis advisor(s): Fouts, Douglas; Pace, Phillip. Includes bibliographical references (p. 51-52). Also available online.

Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well.

In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources.

In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations.

The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs.

Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.

In this thesis, design and simulation of optical logic gases based on different photonics crystals presented to used in the electronics and telecommunication industries. Optical devices perform faster with higher efficiencies compare to the electrical device.The photonic crystal applications to achieve higher transmission power and contrast ratio focus on the design criteria. Results proved promising insights toward the development of gas sensors. The proposed structures have small dimensions as well as a wide functional interval.In Chapter 1,before employing the wavelength-division multiplexing (WDM) method, the notion of the electromagnetic wave in free space and in conductors with a description of equations was defined.Chapter 2 is dedicated to studying literature and similar research,started by the review of photonic crystals and photonic band gap. The gates, characteristics and design layouts were discussed without using nonlinear materials and optical amplifiers.Chapter 3 describes schemes proposed structures.In chapter 4, simulation studies and analysis of six new structures are presented. The procedure is as follows to use the linear logic NOT, OR and AND gates first. These structures have an input waveguide for applying a Gaussian optical pulse at a wavelength of 1550 nm. By changing the radius of the defect, the best dimension with the highest transmission is obtained.Afterward, by coupling these gates, and getting NOR and NAND gates in to study a reasonable contrast ratio and transmission power in each case by changing the defect radius obtained and proved the design concept. A full adder based on metal-insulator-metal (MIM) waveguide-based plasmonic waves. We studied the 4-input OR gate to design and simulate a full adder circuit, which used plasmonic waves to transmit signals; the 4-input gate presented in this study has a simple structure and is manufactured at a low cost. By optimizing the structure's dimensions, the losses and achieve a transmission coefficient of about 0.62 and educe the losses to 25% less than the mentioned design in the references.The next propose structure is a 2DPC based eight channels demultiplexer. This structure is proposed and designed using an octagonal ring resonator for WDM applications.The functional parameters are resonant wavelength, Q factor, channel spacing, spectral width, output efficiency, and crosstalk, are investigated. In this attempt, the channel selection is carried out by altering the octagonal ring resonator's size. The average transmission efficiency, Q factor, spectral width, and channel spacing of the proposed demultiplexer are 98.65%, 2212, 0.76 nm, and 1.75 nm, respectively. The proposed demultiplexer's crosstalk is low (30 dB ) as the even number of channels and the odd number of channels are dropped separately. The demultiplexer's size is about 752.64 µm2, and the functional characteristics of the proposed demultiplexer meet the requirements of WDM systems. Hence this demultiplexer can be incorporated for integrated optics. We have shown that the device is perfectly suitable for communication applications.Chapter 5 is the conclusion of the thesis and recommendation of future studies which has been presented for industrial purposes. In this thesis, a new photonic crystal slab for its use in gas sensing applications is proposed. Theoretical studies have been done to determine the response of the proposed structure to carbon dioxide. A simple laser with around 1 nm spectral widths can be used to simulate this device. Measurements can be done in two steps, which can be done simultaneously by using a reference device: step one with synthetic air and then adding known concentrations of CO.The output is referenced to the measurement with synthetic air.Our theoretical results show that variations of 17% in the transmission intensity and a clear variation on the transmission peaks' central wavelength.These results are already promising for the development of gas sensors
En esta tesis, diseño y simulación de gases ópticos lógicos basados en diferentes cristales fotónicos presentados para ser utilizados en las industrias de la electrónica y las telecomunicaciones. Los dispositivos ópticos funcionan más rápido con mayor eficiencia en comparación con el dispositivo eléctrico. Las aplicaciones de cristal fotónico para lograr una mayor potencia de transmisión y una relación de contraste se centran en los criterios de diseño. Los resultados demostraron conocimientos prometedores hacia el desarrollo de sensores de gas. Las estructuras propuestas tienen pequeñas dimensiones así como un amplio intervalo funcional. En el Capítulo 1, antes de emplear el método de multiplexación por división de longitud de onda (WDM), se desarrolló la noción de onda electromagnética en el espacio libre y en conductores con una descripción de ecuaciones. El capítulo 2 está dedicado al estudio de la literatura e investigaciones similares, comenzando por la revisión de los cristales fotónicos y la banda prohibida fotónica. Se discutieron las puertas, las características y los diseños de diseño sin utilizar materiales no lineales ni amplificadores ópticos. En el capítulo 3 se describen los esquemas de estructuras propuestos, en el capítulo 4 se presentan estudios de simulación y análisis de seis nuevas estructuras. El procedimiento es el siguiente para utilizar primero las puertas lógicas NOT, OR y AND de lógica lineal. Estas estructuras tienen una guía de ondas de entrada para aplicar un pulso óptico Gaussi-an a una longitud de onda de 1550 nm. Al cambiar el radio del defecto, se obtiene la mejor dimensión con la mayor transmisión. Posteriormente, al acoplar estas puertas y hacer que las puertas NOR y NAND estudien una relación de contraste y potencia de transmisión razonables en cada caso, cambiando el radio de defecto obtenido y probado el concepto de diseño. Un sumador completo basado en ondas plasmónicas basadas en guías de ondas de metal-aislante-metal (MIM). Estudiamos la puerta OR de 4 entradas para diseñar y simular un circuito sumador completo, que usaba ondas plasmónicas para transmitir señales; la compuerta de 4 entradas presentada en este estudio tiene una estructura simple y está fabricada a bajo costo. Optimizando las dimensiones de la estructura, las pérdidas y logran un coeficiente de transmisión de alrededor de 0,62 y reducen las pérdidas a un 25% menos que el diseño mencionado en las referencias. La siguiente estructura propuesta es un demultiplexor de ocho canales basado en 2DPC. Esta estructura se propone y diseña utilizando un resonador de anillo octagonal para aplicaciones WDM. Los parámetros funcionales son la longitud de onda resonante, el factor Q, el espaciado de canales, el ancho espectral, la eficiencia de salida y la diafonía. En este intento, la selección de canal se lleva a cabo alterando el tamaño del resonador de anillo octagonal. La eficiencia de transmisión promedio, el factor Q, el ancho espectral y el espaciado de canales del demultiplexor propuesto son 98,65%, 2212, 0,76 nm y 1,75 nm, respectivamente. La diafonía del demultiplexor propuesto es baja (30 dB) ya que el número par de canales y el número impar de canales se eliminan por separado. El tamaño del demultiplexor es de aproximadamente 752,64 µm2 y las características funcionales del demultiplexor propuesto cumplen los requisitos de los sistemas WDM. Por tanto, este demultiplexor se puede incorporar para ópticas integradas. Hemos demostrado que el dispositivo es perfectamente apto para aplicaciones de comunicación. El capítulo 5 es la conclusión de la tesis y recomendación de futuros estudios que se ha presentado con fines industriales.En esta tesis, se propone una nueva placa de cristal fotónico para su uso en aplicaciones de detección de gases. Se han realizado estudios teóricos para determinar la respuesta de la estructura propuesta al dióxido de carbono. Se puede utilizar un láser simple con anchos espectrales de alrededor de 1 nm para simular este dispositivo. Las mediciones se pueden realizar en dos pasos, que se pueden hacer simultáneamente utilizando un dispositivo de referencia: el paso uno con aire sintético y luego agregando concentraciones conocidas de CO. La salida se refiere a la medición con aire sintético. Nuestros resultados teóricos muestran que las variaciones de 17% en la intensidad de transmisión y una clara variación en la longitud de onda central de los picos de transmisión, resultados que ya son prometedores para el desarrollo de sensores de gas.
Enginyeria electrònica

Values and concerns of project participants have influence on design quality as well as on the design process itself. These determine the functional, social and æ
sthetic characteristics of the project that are necessary to achieve client satisfaction. The issues of value and quality are compared within the context of architectural programming, including their theoretical and philosophical ground as well as current management techniques. Value and quality can be misunderstood and confused with each other
therefore, it is vital for project participants to have a common understanding of terminology and meaning. This study includes a comprehensive literature survey on architectural programming and design quality. The current approaches to the construction project process in Turkey were observed through analyzing an hotel project in Turgutreis, Turkey. Supporting tools like Project Definition Rating Index (PDRI) and Design Quality Indicators (DQI) were studied in detail and discussed by the project participants who involved in and affected the design of the project. This study on architectural programming aimed to explore opportunities for identifying and delivering values into the current process of construction projects. It attempted to claim due recognition for designers in that they had an important role to play in developing better quality buildings and that they designed buildings within pertinent social, political and cultural contexts. It was expected that analysis of participants&
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values would provide an understanding of the elaborate decision-making that architects have to perform in order to produce added value in designs, and of how architects resolve design problems.

Arbetet har genomförts med målet att skapa ett mervärde för Sony Ericssons produkter, utan att fokusera på telefoner. Vi har undersökt hur man kan öka användarens band till en teknologisk produkt som man alltid bär med sig. Vi har, genom att anordna en workshop, studerat användare och deras attityd gällande personalisering av mobiltelefoner. Vidare har vi besökt Milano och Berlin, och studerat hur mobiltelefoner kommuniceras hos återförsäljare och hur de används, för att få ett globalt perspektiv. Studierna har resulterat i att vi funnit en brist i hur personliga teknologier svarar mot människors känslor. Vi har baserat på detta skapat ett koncept vi kallar Selectíf som innebär en serie riktlinjer, eller kriterier för att skapa tillbehör till mobiltelefoner. Dessa tillbehör skall ta större hänsyn till emotionella aspekter och fokusera mindre på att vara funktions orienterade. Selectíf-produkter sätter känslorna i främsta rummet och skapar därmed ett mervärde baserat på emotionella band.
We have in this thesis studied the area of emotive design as a way to create a stronger user experience. Functionality and features are still important to break new grounds and develop artifacts that can make our life easier, but the value of the product must beconsidered in a new way and communicated on new level, an emotional level.We have within the thesis, in collaboration with Sony Ericsson,investigated how emotions can be evoked by personal technologies.The human computer interaction is today so advanced that we might not always reflect over the impact the technology has on us. Our personal technology is getting more sophisticated which could allow stronger emotional bonds between the user and a device. What we have created is a concept for designing what we call emotional triggers.To find out what triggers users’ emotions towards technologyin order to create an added value, we have studied the relationshipbetween users and their mobile phones. These studies included a workshop where we aimed to find out how users perceive their mobile phone and also how willing they are to personalize it.Furthermore we conducted trend research in Berlin and Milan to see international differences in mobile usage and also tocompare it to other industries such as the fashion industry.The result is a concept we call Selectíf. The concept is a set of design criteria for designing add-ons that are made to illustratemore emotional values of a technical device. The concept is based on the notion of a series of add-ons and we have also createda first prototype, called Selectíf no1 based on the criteria.The prototype focuses less on technology and more on a user’s emotional needs and illuminates how personal technologies canbe designed to be more emotive and thereby create a stronger user experience.

This study focused on game physics, an area of computer game design where physics is applied in interactive computer software. The purpose of the research was a fresh analysis of game physics in order to prove that its current usage is limited and requires advancement. The investigations presented in this dissertation establish constructive principles to advance game physics design. The main premise was that transdisciplinary approaches provide significant value. The resulting designs reflected combined goals of game developers, artists and physicists and provide novel ways to incorporate physics into games. The applicability and user impact of such new game physics across several target audiences was thoroughly examined. In order to explore the transdisciplinary nature of the premise, valid evidence was gathered using a broad range of theoretical and practical methodologies. The research established a clear definition of game physics within the context of historical, technological, practical, scientific, and artistic considerations. Game analysis, literature reviews and seminal surveys of game players, game developers and scientists were conducted. A heuristic categorization of game types was defined to create an extensive database of computer games and carry out a statistical analysis of game physics usage. Results were then combined to define core principles for the design of unconventional new game physics elements. Software implementations of several elements were developed to examine the practical feasibility of the proposed principles. This research prototype was exposed to practitioners (artists, game developers and scientists) in field studies, documented on video and subsequently analyzed to evaluate the effectiveness of the elements on the audiences. The findings from this research demonstrated that standard game physics is a common but limited design element in computer games. It was discovered that the entertainment driven design goals of game developers interfere with the needs of educators and scientists. Game reviews exemplified the exaggerated and incorrect physics present in many commercial computer games. This “pseudo physics” was shown to have potentially undesired effects on game players. Art reviews also indicated that game physics technology remains largely inaccessible to artists. The principal conclusion drawn from this study was that the proposed new game physics advances game design and creates value by expanding the choices available to game developers and designers, enabling artists to create more scientifically robust artworks, and encouraging scientists to consider games as a viable tool for education and research. The practical portion generated tangible evidence that the isolated “silos” of engineering, art and science can be bridged when game physics is designed in a transdisciplinary way. This dissertation recommends that scientific and artistic perspectives should always be considered when game physics is used in computer-based media, because significant value for a broad range of practitioners in succinctly different fields can be achieved. The study has thereby established a state of the art research into game physics, which not only offers other researchers constructive principles for future investigations, but also provides much-needed new material to address the observed discrepancies in game theory and digital media design.

Today’s college students face an uphill battle to find well-matched and fulfilling work upon graduation. Many have generalized their studies, without a specific career path in mind, and are underprepared for professional expectations and needs. Lack of experience and self-knowledge, coupled with an outdated approach to workplace skills, means that they struggle 1) to find their fit, and 2) to convince employers of their worth. My thesis focuses on researching the varying experiences and interactions of stakeholders within the existing recruitment system: college students, their career counselors, and hiring managers. I found that, while all working towards the same goal of mutually beneficial employment, the traditional model of applying to jobs is broken, in that it does not adequately align needs and match candidates. The solution I present here is a holistic approach to assessing and communicating the values and skills that truly create a flourishing workplace and employee/employer relationship. My goal is to equip students with tools for self-discovery and communication, creating more targeted applications, and thereby providing recruiters with richer information about potential hires.

A distribution center that services value-added operations in addition to its normal operations faces a design problem: How to configure the forward/reserve departments for both of these operations. Analytical models are developed to analyze the tradeoff between floorspace and labor efficiency. Our results indicate that the best distribution center design is dependent on a companyâ s customer demand profile as well as the relative cost of floorspace and labor.
Master of Science

This thesis examines three uniquely different community engagement methods that explore the relationship between community values and the physical landscape in two Appalachian communities; Austinville, VA and St. Paul, VA. Each community engagement method is 1) introduced via literature review/case study, 2) modified from the case study to suit local conditions, and 3) analyzed for effectiveness in connecting local values and the physical landscape. I then reflected on this academic research through the lens of a three-year employment as a community development and natural asset planner with a 501(c)3 non-profit in southwest Virginia. The professional experience revealed five community systems that impacted the overall effectiveness of community engagement processes and had the potential to position communities, and their public projects, for a higher level of success. The community systems included: Capacity and Readiness, Involvement, Leadership, Communication, Frame of Reference and Community Vision. Research and professional practice together suggested that an intentional effort to understand and incorporate community values via community engagement ultimately led to more meaningful designs in the public sector.
Master of Landscape Architecture

Thesis (MBA)--Stellenbosch University, 2001.
ENGLISH ABSTRACT: "Value adding process design" entails two underlying concepts, namely "business process" and "value adding": Business process: According to Dr Michael Hammer (Hammer, 1999), the recognised father of process thinking, a business process is an "organised group of related activities that together create customer value". The focus in the process is not on individual units of work, which by themselves accomplish nothing for a customer, but rather on an entire group of activities that, when effectively brought together, create a result that customers value. Value adding: The concept of "value adding" can be defined in different ways depending on the receiver of the value (shareholders, customers or employees). From a shareholder perspective, value adding can be measured by using EVA (Economic Value Added). EVA is a measure of economic profit generally meaning that a positive EVA indicates that value has been created, whereas a negative EVA means value has been destroyed. The perspective from which process improvement is addressed is the value that is added for the customer, but always with the constraint of not negatively impacting the EVA of the organisation. Value adding process design: "Value adding process" design entails the design of a business process or interrelated business processes to ensure that employee and customer needs are satisfied, whilst creating value for shareholders. The objective of this study is to develop a methodology and supporting tools to enable a organisation to make the transition from being task focused to becoming a truly process organisation. The approach that is proposed is the Rynmar VAP Diagnostic Tool. The approach consists of 5 phases, best explained by the metaphor of building a house: • Setting the stage (phase 0) is identifying the need for a house, i.e. being unhappy with the current situation to an extent that one has the burning desire to change surrounding, even if it will cost a lot of time, effort and financial resources. • Visioning (phase 1) is drawing an artist impression of the house. It involves thinking what the new house should look like, for example do I want a Cape-Dutch house with thatched roof and white walls, or an Italian design with tiled roof and off-white walls. Visioning is the magnetic force that one holds on to whenever the question is asked: "Is it worth the effort?" • Design Process (phase 2) entails applying different techniques to draw an architectural design of the firstly the current processes, followed by the future process that will meet the different aspects of the vision. • Prototype & Build (phase 3) involves firstly building a small scale model of the house to test and improve the design made in phase 3, followed by building the actual house. • Train & Implement (phase 4) firstly entails training the different people in the skills required by the new process design and then implementing the process under careful guidance of the project team, i.e. moving into the house. • Continuous Improvement (phase 5) involves continuously improving the process to ensure that incremental performance improvement is achieved, which will lead to a dramatic cumulative improvement over time.
AFRIKAANSE OPSOMMING: "Waarde toegevoeging proses ontwerp" behels twee onderliggende konsepte, naamlik "besigheidsproses" en "waarde toevoeging": Besigheidsproses: Volgens Dr Michael Hammer (Hammer, 1999), die erkende vader van prosesdenke, kan 'n besigheidsproses definieer word as 'n georganiseerde groep van aktiwiteite wat gesamentlik waarde skep vir 'n kliënt. Die fokus in die proses is nie op individuele komponente van werk nie, wat individueel niks vir die gebruiker kan vermag nie, maar eerder op 'n geïntegreerde groep van aktiwiteite wat, indien effektief gegroepeer word, waarde skep vir 'n kliënt. Waarde toevoeging: Die konsep "waarde toevoeging" kan op verskillende maniere gedefinieer word afhangende van die ontvanger van die waarde (aandeelhouers, kliënte of werknemers). Vanuit die perspektief van 'n aandeelhouer word waarde toevoeging gemeet deur gebruik te maak van EVA ("Economic Value Added'). EVA is 'n maatstaf van ekonomiese wins, wat daarop neerkom dat 'n positiewe EVA aandui dat waarde geskep (toegevoeg) is, terwyl 'n negatiewe EVA beteken dat waarde verwoes is (waardevermindering). Prosesverbetering word gevolglik daarop gerig om waarde toe te voeg vir 'n kliënt, maar altyd onderhewig daaraan dat dit 'n positiewe impak op die EVA van die organisasie sal hê. Waarde toegevoegde proses ontwerp: "Waarde toegevoegde proses ontwerp" behels die ontwerp van 'n besigheidsproses of verwante besigheidprosesse wat sal verseker dat daar aan die behoeftes van werknemers en kliënte voldoen word en terselftertyd dat waarde geskep word vir aandeelhouers. Die doelwit van hierdie studie is om 'n metodologie en ondersteunende gereedskap te ontwikkel wat 'n organisasie in staat stel om die transformasie te maak van 'n taak-georiënteerde na 'n ten volle proses-georiënteerde organisasie. Die benadering wat voorgestel word is die Rynmar VAP model. Die benadering bestaan uit vyf fases en kan verduidelik word aan die hand van die metafoor om 'n huis te bou: • Definieer 'n platform vir verandering (fase 0) is om die behoefte te identifiseer om 'n huis te bou, naamlik om ontevrede te wees met die huidige situasie tot so 'n mate dat 'n brandende begeerte bestaan om iets daaraan te doen, selfs al kos dit tyd, moeite en finansies. • Skep van 'n prosesvisie (fase 1) is om 'n kunstenaarsvoorstelling te maak van die huis. Dit sluit in hoe die nuwe huis moet lyk, byvoorbeeld 'n Kaaps-Hollandse huis met 'n grasdak en wit mure. 'n Visie is die magnetiese aantrekkingskrag wat 'n organisasie aan vasklou wanneer die vraag gevra word: "Is dit die moeite werd?" • Proses ontwerp (fase 2) behels die toepassing van verskillende tegnieke om 'n argitekstekening van eerstens die bestaande prosesse te maak, gevolg deur die ontwerp van toekomstige prosesse wat die visie sal verwesenlik. • Prototipering & bou (fase 3) behels die bou van 'n klein skaalmodel van die huis om die ontwerp te toets en verbetering aan te bring, gevolg deur die werklike bou van die huis. • Opleiding & implementering (fase 4) behels eerstens die opleiding van die betrokke partye, gefokus op die vaardighede wat benodig word om die nuwe proses te implementer. Vervolgens word die proses implementeer onder die waaksame oog van die projekspan, naamlik om in die huis in te trek. • Kontinue verbetering (fase 5) behels die kontinue verbetering van die proses wat sal verseker dat inkrementele verbetering behaal word, wat lei tot dramatiese verbetering opgebou oor tyd.

Software products are tools that find more uses in the society every day, both professionally and in daily lives of members of the society. This thesis focuses on the problems and possibilities related to current software products. By analysis of the problems and current issues in the software field, possible contribution of a design-oriented approach to software products is explored. The thesis is supported by a study in the form of a semi-structured observation.

In recent years there has been great concern over what many are calling the “tuition bubble� in American higher education. Baumol and Bowen, in 1966, observed that personally delivered services, like a professor teaching in a university, are difficult to scale, which causes a continuing and compounded rise in real cost. Additionally, universities, in competing for students, tend to invest in expensive assets. The resulting cost of the education and the amount of student debt threatens to rise beyond the intrinsic economic value of a US college degree, especially in the face of equivalent substitutes. The overall objective of this research is not only to analyze but also to design, or re-design, some of the essential aspects of engineering education systems. A new design is proposed using principles from manufacturing, industrial engineering and axiomatic design. The proposed system is able to operate at lower costs while producing high-caliber engineers. The approach presented relies on the decomposition of the functional elements of engineering education as well as defining a quantum of learning as an inventory unit. Methods used include a value-added analysis, and value stream mapping, computer simulation and financial analysis. The results show that the net present value (NPV) for the student increases over the interval from [t start to t graduation] as the time to employment post gradation decreases for a given discount rate. This is due to receiving employment income sooner during the cash flow. Engineering schools might benefit economically from reduced costs and higher tuition revenue resulting from greater system capacity.

碩士
國立勤益科技大學
電子工程系
106
The full adder (FA) is a critical part of these processors for growing portable systems with high-performance. As feature size of CMOS technology scaling down, reliability becomes important issue of IC design. Fault tolerant technology is to prevent system failure while transient fault occurred at a circuit node; some systems are designed to be reconfigurable and self-repairing. In this thesis, proposed a self- repairing full adder based on parity, and design a totally self-checking checker to improve the reliability of the circuit. The self-repairing full adder has superior features with 56 transistor count, 100% area overhead, 38% time overhead, 1.065uW power dissipation, 0.197fJ power delay product and maximum speed up to 1G Hz. The experimental results show the proposed self-repairing full adder design is valid and practical.

Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area. In this thesis, the dynamic switching power consumption of ripple carry adder, carry look ahead adder, carry skip adder, carry select adder, and prefix adder are discussed. The power factor, the sum of products of probability and fan-out of all internal nodes, is presented. This thesis also studies the power and time trade-off with efficiency index which is the product of power factor and worst case gate counts. The result shows that the carry look ahead adder has the lowest efficiency index in the design of a 64 bit adder. The carry skip adder is the best one in a design of a 16 and 32 bit adder. The ripple carry adder is the best choice for an 8 bit adder. This study also presents a low power prefix adder design which will reduce the power consumption of the prefix adder without lost of performance.
Graduation date: 1998

碩士
國立勤益科技大學
電子工程系
99
In this paper, the High Reliability and Low Cost Self-Repair (SR) Carry-Select Adder (CSA) design is proposed. The capability of architecture can on-line detect all single stuck-at faults and repair in normal operation mode. In the area, this paper choose a better way to reduce the area. A self-repair CSA constructed by n two-bit modules has merely one backup redundancy with fault diagnosis circuitry. Effectively reduce the number of transistors, and the proposed new circuit to improve the previous literature the problem of fault coverage. The design is based on TSMC 0.18um process technology. Fault coverage of detection part are high than [8] 11% and [5] 27%. However, improve the circuit fault coverage lead to increased circuit area. In our self-repair methodology, Can effectively reduce the area, when 10-bit SR CSA circuit to add a backup (2-bit), the transistor count less than [10] 11.3%. This work also presents a new checker, in TSMC 0.18μm 1.8V 800MHz power to simulate than the original checker 93.2% of the power saving, at 0.9V operation voltage and can work in the 1.6GHz.

碩士
國立中興大學
資訊科學與工程學系
105
Adder is a critical component in arithmetic and logic units (ALUs). Minimizing the power consumption and delay of adder is an important issue. In this paper, we proposed a high performance multiplexer-based radix-4 adder with refined carry to reduce the propagation delay. To achieve high performance, the proposed radix-4 adder adopts multiplexers which are controlled by the carry signal of previous stage to avoid the long carry chain. The drivability of all outputs is strong because all outputs are full voltage swing. The proposed design was simulated by using the TSMC CMOS 45 nm technology. For 128-bit adders, compared with the previous radix-4 adder and 2-bit carry select adder, our design can reduce 14% and 20% delay, respectively; our design also achieves 7.3% and 67% EDP reduction, respectively.

碩士
國立交通大學
電子工程系所
94
Binary addition is one of the fundamental arithmetic operations in digital system design. Consequently, several adder architectures have been proposed to meet different design requirements in the past. Various architectures like carry-select, parallel-prefix, and carry-lookahead lead to different performance among area, delay, and power. In general, Kogge-Stone parallel-prefix adders provide a good solution to optimize delay and regular structure for VLSI implementation. The proposed architecture uses Ling addition to reduce one logic level delay in parallel-prefix structure for the carry generation. Furthermore, using hybrid parallel-prefix/carry-select architecture and some special function blocks can reduce overall area. Experimental results reveal that the proposed architecture achieves 25% area reduction when compared to traditional Kogge-Stone parallel-prefix adders. Recently, the multimedia plays an important role in our life. Multimedia signal processing usually needs a fast reconfigure adder, which can be run-time reconfigured to handle the operations with different precisions. However, the extra overhead of partition scheme for the purpose of reconfigurability is unavoidable. Therefore, we present a new reconfigurable approach by modifying our original architecture without introducing significant extra area and timing penalty. Finally, experimental results show that the new reconfigurable adder needs only 5.12% delay penalty and 3.98% area penalty. In brief, the proposed adders do our utmost to reduce area without affecting speed and extent to reconfigurable scheme easily.

碩士
國立高雄大學
電機工程學系碩士班
97
In this thesis, we propose a low power-delay product full adder designed in hybrid logic which combines the concepts of static logic, dynamic logic, and multi-threshold CMOS. In this design, the circuit for sum and the circuit for carry out are designed separately for alleviating the loading effect in the interconnections. The multi-threshold CMOS technology does reduce the leakage current either in the circuit for sum or the circuit for carry out. The whole simulations are performed by HSPICE with TSMC 0.18-μm 1P6M process technology. The simulation results show that the proposed full adder can achieve a power-delay product of 0.063 pJ for sum block and 0.021 pJ for carry out block at 400 MHz.

碩士
國立中正大學
電機工程研究所
90
Adders are fundamental building blocks and often constitute part of the critical path. The maximum operating speed of a Ripple Carry Adder (RCA) is limited by the carry propagation delay, and the penalty of the propagation delay depends on the number of primary input bits. In this paper, we propose four high-speed and compact ripple carry adder designs. The key techniques of these novel designs are race-free dynamic CMOS logic technique for high-speed and compact designs. We demonstrate these designs approach using a 32-bit ripple carry adder built with the TSMC 0.25-um CMOS technology. The adder operates at 2.5V. The SPICE simulation shows that the proposed Dynamic Ripple Carry Adders (DRCAs) are at least 2.38 times faster than the conventional static ripple carry adder (SRCA). Further all of the proposed designs compare much favorably to the previous DRCA design that employs the DCVS logic.

碩士
逢甲大學
資訊電機工程碩士在職專班
100
To overcome the full adder without driving outputs structure of that carries signal attenuation issue and improve the full adder with driving outputs structure issue of circuit performance, this paper presents the structure of four complementary binary full adder and four design methods of adder modules. We use four complementary binary full adder circuit structure FA_A, FA_B, FA_C and FA_D adder with four kinds of tree construction techniques, design of M1 ~ M8 eight kinds of high-performance adder cores. In order to compare the performance of all adder circuits, this paper using TSMC 0.18-μm CMOS process technology and HSPICE circuit simulation software to experiment. This paper will M1 ~ M8 adder cores with conventional CMOS full adder, N-HPSC adder, Hybrid-CMOS, DPL-FA and SR-CPL full adder are cascaded into a 12-bit ripple carry adder to do analysis and comparison. We designed the adder modules regardless of the transistor count, the average power consumption, critical path delay time and power-delay product and so have a good advantage. When the operating voltage Vdd = 1.8V when, M2, M3 and M6 with the least transistor count (Tr. #), you can save 38% ~ 62%, M6 power consumption (Pd) decreased -2% ~ 19%, M8 propagation delay time (Td) minimum, reduce the 8% ~ 54%, M2 power delay product (PDP) best reduced by 17% to 58%. When the operating voltage Vdd = 0.6V when, M4 also has the shortest propagation delay time (Td) and the minimum power delay product (PDP), decreased 13% to 30% and 35% to 68%, while the M6 can save 20 % to 53% of power consumption (Pd). When M1 ~ M8 eight kinds of adder cores connected in series to 18-bit RCA, its experimental results with the series into a 12-bit RCA trend is the same.These results confirm our adder design approach is both practical and effective, if these adder modules applied to arithmetic circuit and electronic system, will be able to improve electronic system overall performance.

碩士
中華科技大學
機電光工程研究所在職專班
99
This study is via beam propagation method (BPM) to simulate and analysis of optical logic elements, Extended the basic optical logic gates and combines with the single-mode waveguide design to create the new optical logic components. In the meantime enter the specific range of wavelength with two different light waves to create the traditional electronics logical function components. Researching the design of integrated all-optical logic elements, with the interference properties of the light to control the light output and energy intensity and reach through constructive interference and destructive interference, the principle is a sense of change two kinds of light phase to create the phase difference. During the researching there is two different ways to change the phase waves, one is to change the length of optical waveguide components, and the second way is to change the optical waveguide material itself or to add medium. According to Sri Lanka Cornell's law (Snell's law) the change of the index of refractive / reflectivity of light and the light into a different medium, different reflection, refractive index to cause phase. Using this kind of character to design the optical logiccombination elements. Key words: optical waveguide, integrated optics, optical combinatorial logic elements, optical logic gates, beam propagation method

碩士
國立勤益科技大學
電子工程系
100
Binary Signed-Digit (BSD) number representation has inherently carry-free (CF) addition. Hence, it is widely applied in design of parallel arithmetic and high performance processor. The structure of a BSD adder design is mainly composed of three blocks including binary-to-BSD conversion, BSD computing unit and BSD-to-binary conversion. In design of each block, we find that the binary-to-BSD conversion can be done in constant time. In addition, the performance of BSD-to-binary conversion almost dominates the whole performance of a BSD-based arithmetic system. In this thesis, a high performance BSD adder design is proposed to have the capability of on-line detection all single stuck-at fault and repairing in normal operation mode. The tree-structure two-rail code checker (TRC) is chosen in our self-checking and repair circuits design due to its simple and easier implementation. The BSD adder with self-repair capability can provides higher reliability. The validations and realizations of our design are based on TSMC 0.18μm process technology, and the experimental results have proved our design is valid and can effectively reduce the transistor count, carry propagation delay and power consumption.

碩士
國立勤益科技大學
電子工程系
99
In this thesis, we propose a completely parallel adder design based on BSD (Binary Signed-Digit) representation. The binary signed-digit number representation has inherently carry-free property. Therefore, binary signed-digit number representation is widely used to implement parallel arithmetic and high performance processor. The thesis focuses on the key issues of parallel adder design based on binary signed-digit representation. The proposed parallel adder designs can efficiently reduce the carry propagation delay. Realization and simulation are based on both TSMC 0.35um process technology and TSMC 0.18um process technology, and the experimental results have proved our proposed structure being with high performance and reliability. The structure of a BSD adder design is mainly composed of three blocks including Binary to BSD conversion, BSD Unit and BSD to binary conversion. In design of each block, efforts are focused on functional realization, schematics design, analysis, and comparison of performance. Finally, the checking circuits are partly added for achieving higher reliability. The tree-structure two-rail code checker is chosen in our design due to its simple structure and easier implementation. It is more suitable for high bit-count design than non-tree structure two-rail code checker.

碩士
國立高雄應用科技大學
電子工程系
99
The hardware implementation of digital filters is mainly dominated by the multiplier blocks. Implementing constant coefficient digital FIR filters multiplier block using adders, subtractors, and shifters will achieve lower power consumption. In this thesis, we use the graph representation to reduce designed hardware complexity, and uses the reduced adder graph (RAG) algorithm to implement filter multiplier blocks. To further reduce the adder cost, we try to enhance the hardware resources sharing for the coefficients realization of different filters. The proposed method may avoid the use of heuristic part of RAG algorithm. Therefore, the reduced adder cost is attained. Two-operand binary addition is the most widely used in digital filters operation. To improve the efficiency of this operation, it is desirable to use an adder with good performance and area tradeoff characteristics. This thesis also presents a modified carry-lookahead adder architecture based on the parallel prefix computation graph. The proposed two-operand binary adder has fewer component counts and better figure of merit (FOM) than previous related work. The proposed adder is used to implement the multiple FIR filters in TSMC 0.18μm CMOS technology. The realized 24bit adder has 40% chip area and 40% power consumption reductions comparing with previous works [14]. The implemented filters have 27% chip area and 10% power consumption reductions comparing with previous works [5]. Therefore, this thesis achieves high-efficiency FIR filter designs.

碩士
國立中興大學
資訊科學與工程學系所
100
In this paper, we propose an imprecise radix-4 adder for image processing of multimedia applications. In order to reduce power consumption of the architecture and maintain acceptable image quality, we utilize the relaxtion of numerical accuracy in error tolerant to reduce the logic of radix-4 adder complexity. Based on TSMC 90nm CMOS technology, the simulation results indicate that dynamic power saving is 13~24%, 14~22% reduction in leakage ,and the image quality degradation is minor campared to the previous researches respectively.

碩士
南台科技大學
電子工程系
95
GDI (Gate Diffusion Input) is a new technique which was proposed in few years ago. This technique allows reducing power consumption, delay time and area of circuit. The most important feature of the GDI circuit is to simplify the design of a complicated digital circuit. Although there are many different circuits that can be used to improve speed, reduce power consumption and area of circuit, most of these circuits are very complex. Among these circuits, PTL (Pass-Transistor Logic) is one of the most common low power circuits. However, it is very difficult and complex to design a PTL circuit from top to down. Since there is no suitable and simple cell library for designers to use. Adder is one of the most common operation units in ALU (Arithmetic Logic Unit), e.g, subtractor, multiplier, and divider, which are all based on the adder. This thesis is based on the GDI circuit which is used to propose a brand new 16 bit IGDI adder/subtractor. We have compared the power consumption, speed, and number of transistors with other adders. We can find that the adder /subtractor based on the IGDI structure has less power consumption and high speed.

碩士
華梵大學
機電工程研究所
91
In this thesis, a 3-step subexpression sharing method is proposed to share some adders in the adder block of transposed-form FIR filters. Without increasing the critical path in the adder block, the number of adders required to implement the FIR filter is reduced. A program developed in this thesis is used to generate RTL-VHDL code. In this program, some techniques are employed to approach low-complexity design: coefficients expressed in canonical sign-digit (CSD) representation, multiplication replaced by add/subtract and shift operations. Beside, sign extension elimination is involved to overcome a large load problem on the input data bus of the transposed-form FIR filter. We also have a discussion about the CRA-type architecture and the CSA-type architecture in this thesis. The CRA-type FIR filter can achieve small area but can only operate at low throughput rate. The CSA-type FIR filter can operate at high throughput rate. However, it requires more registers and an extra VMA adder, this results in a large realized area. Base on high—level design flow, we use ModelSim to verify the logic of the output VHDL code and use Synopsys with TSMC 0.25μm cell library to synthesize the VHDL code and implement DFT design. From this, we can obtain the estimated size、speed、power consumption and fault coverage of the circuit.

碩士
國立雲林科技大學
電子與資訊工程研究所
93
How to handle the balance of the performance and power consumption in layout area reduced design is the most important issue for designer. In this paper, we proposed a novel full adder design featuring both low voltage and low energy ( power delay product ) operation using as few as 10 transistors per bit. To achieve low voltage operation, the design adopts inverter based XOR/XNOR designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from direct cascading if no extra buffering is employed. The proposed design successfully embeds the buffering circuit in the full adder design so that the transistor count is kept as minimum. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both DC and AC performances of the proposed design are evaluated against various full adder designs via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35μm process models, indicate that the proposed design has the lowest working Vdd ( 1.9V ) and highest working frequency ( 1300MHz @ 3.3V ) among all designs using 10 transistors. It also features the highest frequency and lowest energy consumption per addition in the application of ripple carry adder.

碩士
中正理工學院
電機工程研究所
87
Most of the cryptosystem, which implemented in software or hardware methods, need modular multiplication and modular exponentiation. In the hardware design of a good cryptosystem, the basic circuit should not include any error. The adder, which constructs the basic device of the cryptosystem, should operate fast and provide the ability of error detection. The traditional binary adder has the carry propagation delay so it is slow. The carry look-ahead adder improves the carry propagation delay but it has another disadvantage, i.e., more bits size of the circuit involves the more complexity of the circuit. It is unrealistic that very large fan-in are required by the carry look-ahead adder. One of the valid way to solve the carry propagation delay is using the signed binary digit (SBD) system. In this thesis, we propose a SBD based adder, which is fast and error detection. Base on this adder, the cryptosystem is more robust.

博士
逢甲大學
電機與通訊工程博士學位學程
102
Since a full adder plays the most critical role in the performance of an arithmetic circuit, this dissertation aims to present three high performance full adders for the chip area and power consumption reduction, and for the improvement in robust output driving capability and modular circuit structures. They are designated as a regularly modularized multiplexer-based full adder (MUXFA), a low power high speed and low-complexity full adder (LPHS-FA), and a fully symmetric parallel full Adder (FSPFA). The MUXFA full adder is composed of three identical modules, in which each module separately operates for an XOR-XNOR function, a sum function, and a carry function. The structure of the multiplexer-based full adder can be easily constructed by merely having a single multiplexer module, the features of which include fast design time, a regular structure, a simple layout, and enhanced layout efficiency. The advantages of the design concern design simplicity, design regularity, and integrated-circuit (IC) layout modularity. These characteristics are useful and important in cell-based design, especially for increasing in IC layout efficiency. Due to the regularity and modularity, the proposed full adder uses nineteen transistors only. As compared with NEW-HPSC, Hybrid-CMOS, DPLFA and SR-CPL full adders, the transistor count is reduced from 26.3% to 47.3% and power-delay-product (PDP) is reduced from 48.4%-122%. A low-power, high-speed, and low-complexity full adder, abbreviated as LPHS-FA, is presented in this work as a detailed method to reduce its circuit complexity and to elevate its performance. Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60% to 86% fewer transistors than other types of existing full adders. Compared with other types of existing full adders, an LPHS-FA is found to provide a 20.4% to 27% power saving, a 12.3% to 67.0% delay time reduction, and a 35.2% to 102% reduction in power delay product. There is no doubt that a full adder serves as the core foundation in an arithmetic circuit. For performance elevation, the FSPFA full adder performs parallel logic operations, i.e. sum and carry output operations, in a sum module and a carry module, respectively. Consequently, both the sum output (So) and the carry output (Co) can be generated in a highly efficient fashion. Although the sum and the carry modules conduct independent operations, they both share exactly the same circuit architecture. In this context, the circuit layout is simple, clean, and compact, giving rise to a direct and considerable improvement in the circuit design efficiency. In simple terms, a single circuit layout can be used for both modules, that is, approximately a 100% efficiency elevation. In comparison with the other four full adders, the FSPFA is found to provide superior performance in power consumption, delay time, and power delay product. There are three high performance full adders presented here. a MUXFA, an LPHS-FA and an FSPFA. The MUXFA has a regular modular circuit structure as well as high circuit layout efficiency. The LPHS-FA has a simple circuit configuration and reduced transistor count. The FSPFA has parallel processing, symmetrical structure, and high circuit layout efficiency. The applications of these high-performance full adders apply to any type of arithmetic systems, the total performance of the system will be directly boosted as a whole.