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Journal articles on the topic 'Adder design'

Author: Grafiati

Published: 4 June 2021

Last updated: 2 February 2022

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1

S. B, Rashmi, Praveen B, and Tilak B G. "Design of Optimized Reversible BCD Adder/Subtractor." International Journal of Engineering and Technology 3, no. 3 (2011): 230–34. http://dx.doi.org/10.7763/ijet.2011.v3.229.

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2

Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

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3

B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool.

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4

Haruehanroengra, Sansiri, and Wei Wang. "Efficient Design of QCA Adder Structures." Solid State Phenomena 121-123 (March 2007): 553–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.553.

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Optimizing arithmetic primitives such as quantum-dot cellular automata (QCA) adders is important for investigating high-performance QCA computers in this emerging nano-technological paradigm. In this paper, we demonstrate that QCA ripple carry adder and bit-serial adder designs actually outperform carry-look-ahead and carry-select adder designs because of the increase in required interconnects. Simulation results obtained by using the QCADesigner tool for the proposed adder designs are also presented.

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5

Hameed, Ahmed Salah, and Marwa Jawad Kathem. "High speed modified carry save adder using a structure of multiplexers." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (April 1, 2021): 1591. http://dx.doi.org/10.11591/ijece.v11i2.pp1591-1598.

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Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.

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6

., Chandrahash Patel. "COMPARATOR DESIGN USING FULL ADDER." International Journal of Research in Engineering and Technology 03, no. 07 (July 25, 2014): 365–68. http://dx.doi.org/10.15623/ijret.2014.0307062.

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7

Wei, B. W. Y., and C. D. Thompson. "Area-time optimal adder design." IEEE Transactions on Computers 39, no. 5 (May 1990): 666–75. http://dx.doi.org/10.1109/12.53579.

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8

Lu, Shih-Lien. "Low voltage Manchester adder design." Electronics Letters 33, no. 16 (1997): 1358. http://dx.doi.org/10.1049/el:19970926.

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9

Mehrabani, Yavar Safaei, and Mohammad Eshghi. "High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells." Journal of Circuits, Systems and Computers 24, no. 09 (August 27, 2015): 1550130. http://dx.doi.org/10.1142/s0218126615501303.

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In this paper, three CNT-based full adder designs, called Design1, Design2 and Design3, are proposed. In these designs 12, 14 and 16 transistors are used, respectively. In all designs only 3-input NAND, Majority-not and NOR functions are used. First, a preliminary structure (Design1) is presented using 12 transistors. Then its weaknesses are tackled in two steps. In fact, in each step a new design is presented by adding two more transistors to its predecessor. Therefore two new structures called Design2 and Design3 are built in which Design3 is the most efficient one. To study the performance of Design3 versus other silicon-based and CNT-based 32-nm classical and state-of-the-art cells, comprehensive simulations with regard to various supplies, loads, operating frequencies, and temperatures are performed using Synopsys HSPICE tool. Simulation results confirm that the proposed cell is superior to the other cells. At last the robustness of Design3 against the diameter mismatches of CNTs which is one of the most important concerns of nanoelectronics is studied using Monte Carlo transient analysis. This simulation reveals that Design3 functions very well against manufacturing process variations.

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10

Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX.

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11

Seo, Hyoju, Yoon Seok Yang, and Yongtae Kim. "Design and Analysis of an Approximate Adder with Hybrid Error Reduction." Electronics 9, no. 3 (March 11, 2020): 471. http://dx.doi.org/10.3390/electronics9030471.

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This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.

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12

Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (March 25, 2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.

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13

Prabhu, C. M. R., Tan Wee Xin Wilson, and T. Bhuvaneswari. "Low Power 11T Adder Comparator Design." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 1 (March 1, 2020): 28. http://dx.doi.org/10.11591/ijres.v9.i1.pp28-33.

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Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.

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14

VERGOS, HARIDIMOS T., and CONSTANTINOS EFSTATHIOU. "ON THE DESIGN OF EFFICIENT MODULAR ADDERS." Journal of Circuits, Systems and Computers 14, no. 05 (October 2005): 965–72. http://dx.doi.org/10.1142/s0218126605002726.

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Modular adders are met in various applications of computer systems. In this paper, we investigate a new architecture for their design that utilizes a carry save adder stage and two binary adders that operate in parallel. Realizations in static CMOS reveal that the introduced architecture leads to modular adder implementations that offer significant savings in delay and power consumption over implementations based on previously proposed architectures. In parallel, the proposed architecture offers significantly smaller implementation area for small operand widths.

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15

Choubey, Sonika, and Rajesh Kumar Paul. "Design of Controlled Adder /Subtractor Cell Using Shannon Based Full Adder." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, no. 02 (February 20, 2015): 738–42. http://dx.doi.org/10.15662/ijareeie.2015.0402033.

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16

Singh, Shiwani, Tripti Sharma, K. G. Sharma, and B. P. Singh. "9T Full Adder Design in Subthreshold Region." VLSI Design 2012 (March 11, 2012): 1–5. http://dx.doi.org/10.1155/2012/248347.

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This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are performed on 45 nm standard model on Tanner EDA tool version 13.0.

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17

Poornima, N., and V. S. Kanchana Bhaaskaran. "Design and Implementation of 32-Bit High Valency Jackson Adders." Journal of Circuits, Systems and Computers 26, no. 07 (March 17, 2017): 1750123. http://dx.doi.org/10.1142/s0218126617501237.

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Parallel prefix addition offers a highly efficient solution to most of the applications which requires fast addition of two binary numbers. An efficient adder design demands proper selection of recurrence equations and its realization. There are different recursion equations like Weinberger recursion, Ling recursion, Jackson recursion, to name a few, available to suit a variety of design requirements. In this work, we have proposed adders based on Jackson recursion. In these adders, the complexity found in generate term is reduced at all the levels of the carry graph to optimize the adder performance parameters. The proposed adder structures are implemented for a word size of 32-bit based on the Jackson recursion equations for valency-4 and valency-5. The synthesis results reveal that the high-valency Jackson adder structures are superior in terms of power and area over the Ling adders for comparable delay values. Experimental results obtained reveals that an average of [Formula: see text] and [Formula: see text] savings in area and power, respectively, are achieved by the proposed adders, as compared to Ling adders for the same word size. Furthermore, the proposed adders demonstrate enhanced area-delay and the power-delay values compared to the adders based on the Weinberger’s recursion.

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18

Gowthami, K., and Y. Yamini Devi. "Design of 16-bit Heterogeneous Adder Architectures Using Different Homogeneous Adders." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 5, no. 10 (October 20, 2016): 7843–49. http://dx.doi.org/10.15662/ijareeie.2016.0510007.

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19

Zhang, Qi, Yuping Wu, and Lan Chen. "A Subthreshold Bootstrapped SAPTL-Based Adder Design." Electronics 8, no. 10 (October 12, 2019): 1161. http://dx.doi.org/10.3390/electronics8101161.

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This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amplifier including a voltage boosting part and adopting an adder architecture based on bootstrapped SAPTL, significant improvements in performance and energy efficiency can be achieved. A case study of 16 bit adders in SMIC 130 nm technology demonstrated that the proposed adder outperformed other works in terms of performance, energy consumption, and energy efficiency. Furthermore, the statistical results of the Monte Carlo analysis proved the proposed adder’s significant enhancement of robustness against process and temperature variations. At 0.3 V (TT corner, 25 °C), the proposed 16 bit adder achieved improvements of 72% in performance and 8% in energy savings, as well as a 74% reduction in energy-delay production as compared with the current design.

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20

Swathi, M. "Design of Parallel Self-Timed Adder." International Journal for Research in Applied Science and Engineering Technology 6, no. 3 (March 31, 2018): 1025–27. http://dx.doi.org/10.22214/ijraset.2018.3164.

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21

V J, Ylaya. "Improved Design of Binary Full Adder." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 3 (June 25, 2020): 4113–16. http://dx.doi.org/10.30534/ijatcse/2020/239932020.

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22

Terzer, M., O. Nikolayeva, E. Zitzler, J. Stelling, R. Schütz, M. Jovanovic, F. Zürcher, et al. "Design of a biological half adder." IET Synthetic Biology 1, no. 1 (June 1, 2007): 53–58. http://dx.doi.org/10.1049/iet-stb:20070013.

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23

Mohanty, Basant Kumar. "Efficient Fixed-Width Adder-Tree Design." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 2 (February 2019): 292–96. http://dx.doi.org/10.1109/tcsii.2018.2849214.

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24

Jayanthi. "Design of an Error Tolerant Adder." American Journal of Applied Sciences 9, no. 6 (June 1, 2012): 818–24. http://dx.doi.org/10.3844/ajassp.2012.818.824.

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25

Gupta, Ankita, and Rajeev Thakur. "Full adder Design using Hybrid Technology." International Journal of Computer Applications 130, no. 7 (November 17, 2015): 25–27. http://dx.doi.org/10.5120/ijca2015907029.

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26

Dobson, J. M., and G. M. Blair. "Fast two's complement VLSI adder design." Electronics Letters 31, no. 20 (September 28, 1995): 1721–22. http://dx.doi.org/10.1049/el:19951200.

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27

Hari Kishore, K., B. K. V.Prasad, Y. Manoj Sai Teja, D. Akhila, K. Nikhil Sai, and P. Sravan Kumar. "Design and comparative analysis of inexact speculative adder and multiplier." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 413. http://dx.doi.org/10.14419/ijet.v7i2.8.10472.

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A Carry look ahead adder is a sort of the summer used in the logic design of the digital systems. The CLA boost up the speed by decreasing the measure of duration needed to calculate the carry bits. The CLA based outline of the inexact speculative adder is pipelined architecture to incorporate couple of logic paths along its basic way and in this manner, improving the recurrence of operation. This paper presents the comparative analysis of the pipelined inexact speculative adder and the general carry look ahead adder and showed that the delay is reduced to 48.27% when compared to carry look ahead adder and also we have designed the pipelined multiplier using the Inexact speculative adders and observed that the delay is reduced to 48.32% when compared to the normal multiplier. This entail Xilinx ISE Design Suite 14.5 Tool.

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28

Kumar Saxena, Rakesh, Neelam Sharma, and A. K. Wadhwani. "Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity." International Journal of Engineering and Technology 3, no. 3 (2011): 274–78. http://dx.doi.org/10.7763/ijet.2011.v3.237.

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29

Solomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (April 30, 2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.

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Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

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30

Singhal, Subodh Kumar, B. K. Mohanty, Sujit Kumar Patel, and Gaurav Saxena. "Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 29, no. 12 (February 4, 2020): 2050186. http://dx.doi.org/10.1142/s0218126620501868.

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Parallel prefix adder (PPA) is the core component of diminished-1 modulo ([Formula: see text]) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo ([Formula: see text]) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo ([Formula: see text]) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energy-delay-product (EDP) than the best of the existing modulo adder structure.

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31

Batek, Michael J., and John P. Hayes. "Optimal Testing and Design of Adders." VLSI Design 1, no. 4 (January 1, 1994): 285–98. http://dx.doi.org/10.1155/1994/74269.

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On-the-fly calculations of area and performance are a typical part of the computer-aided iterative design process in VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test-generation time and test-set size. However, determining test sets on-the-fly as one circuit is transformed into another is extremely difficult. Our goal is to add a test dimension to the design optimization process that complements methods concerned with area and performance optimization. We define a set of logic transformations that result in easily computed changes to test sets. Test-set preserving (TSP) transformations preserve a combinational circuit’s test sets, while test-set altering (TSA) transformations introduce a minimum number of tests needed to maintain completeness. We illustrate our approach with a family of adders that share area-efficient tree structures and differ in the amount of carry-lookahead used to accelerate carry computation. Members include the ripple-carry adder, which has no lookahead, and the standard carry-lookahead adder, which exploits lookahead across all inputs. It is straightforward to derive area and performance measures for this class of adders. Given an n-bit adder with lookahead degree k, we determine a sequence of circuit transformations that produce the adder of degree k2 and test sets of minimum size. Optimal test sets of size k(logkn + 1) + 2 result for arbitrary n and k, which improve significantly upon previously reported tests.

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32

KWAK, SANGHOON, JEONG-GUN LEE, EUN-GU JUNG, DONGSOO HAR, MILOS D. ERCEGOVAC, and JEONG-A. LEE. "EXPLORATION OF POWER-DELAY TRADE-OFFS WITH HETEROGENEOUS ADDERS BY INTEGER LINEAR PROGRAMMING." Journal of Circuits, Systems and Computers 18, no. 04 (June 2009): 787–800. http://dx.doi.org/10.1142/s0218126609005368.

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The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder.

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33

Hebbar, Abhishek R., Piyush Srivastava, and Vinod Kumar Joshi. "Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder." Procedia Computer Science 143 (2018): 317–24. http://dx.doi.org/10.1016/j.procs.2018.10.402.

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34

Sasipriya, S., and R. Arun Sekar. "Vedic Multiplier Design Using Modified Carry Select Adder with Parallel Prefix Adder." Journal of Computational and Theoretical Nanoscience 16, no. 5 (May 1, 2019): 1927–37. http://dx.doi.org/10.1166/jctn.2019.7826.

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35

Hajare, Raju, and C. Lakshminarayana. "Design and software characterization of finFET based full adders." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 1 (February 11, 2019): 51. http://dx.doi.org/10.11591/ijres.v8.i1.pp51-60.

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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

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36

Ramana Murthy, G., C. Senthilpari, P. Velrajkumar, and Lim Tien Sze. "Monte-Carlo analysis of a new 6-T full-adder cell for power and propagation delay optimizations in 180 nm process." Engineering Computations 31, no. 2 (February 25, 2014): 149–59. http://dx.doi.org/10.1108/ec-01-2013-0023.

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Purpose – Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operations usually involve addition. Building low-power and high-performance adder cells are of great interest these days, and any modifications made to the full adder would affect the system as a whole. The full adder design has attracted many designer's attention in recent years, and its power reduction is one of the important apprehensions of the designers. This paper presents a 1-bit full adder by using as few as six transistors (6-Ts) per bit in its design. The paper aims to discuss these issues. Design/methodology/approach – The outcome of the proposed adder architectural design is based on micro-architectural specification. This is a textual description, and adder's schematic can accurately predict the performance, power, propagation delay and area of the design. It is designed with a combination of multiplexing control input (MCIT) and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-T adder cell. The design adopts MCIT technique effectively to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. Findings – The proposed adder circuit simulated results are used to verify the correctness and timing of each component. According to the design concepts, the simulated results are compared to the existing adders from the literature, and the significant improvements in the proposed adder are observed. Some of the drawbacks of the existing adder circuits from the literature are as follows: The Shannon theorem-based adder gives voltage swing restoration in sum circuit. Due to this problem, the Shannon circuit consumes high power and operates at low speed. The MUX-14T adder circuit is designed by using multiplexer concept which has a complex node in its design paradigm. The node drivability of input consumes high power to transmit the voltage level. The MCIT-7T adder circuit is designed by using MCIT technique, which consumes more power and leads to high power consumption in the circuit. The MUX-12T adder circuit is designed by MCIT technique. The carry circuit has buffering restoration unit, and its complement leads to high power dissipation and propagation delay. Originality/value – The new 6-T full adder circuit overcomes the drawbacks of the adders from the literature and successfully reduces area, power dissipation and propagation delay.

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Diksha Siddhamshittiwar. "An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique." International Journal of New Practices in Management and Engineering 6, no. 02 (June 30, 2017): 07–12. http://dx.doi.org/10.17762/ijnpme.v6i02.57.

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Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

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Ms. Mayuri Ingole. "Modified Low Power Binary to Excess Code Converter." International Journal of New Practices in Management and Engineering 4, no. 03 (September 30, 2015): 06–10. http://dx.doi.org/10.17762/ijnpme.v4i03.38.

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Utilization of power is a major aspect in the design of integrated circuits. Since, adders are mostly employed in these circuits, we should design them effectively. Here, we propose an easy and effective method in decreasing the maximum consumption of power. Carry Select Adder is the one which is dependent on the design of two adders. We present a high performance low-power adder that is implemented. Also, here in Carry Select Adder, Binary Excess Code-1is replaced by Ripple Carry Adder. After analyzing the results, we can come to a conclusion that the architecture which is proposed will have better results in terms of consumption of power compared to conventional techniques.

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Chen, Tao, Yue Wang, and Gang Zhang. "Design of Adder Based on Abacus Algorithm." Advanced Materials Research 662 (February 2013): 918–21. http://dx.doi.org/10.4028/www.scientific.net/amr.662.918.

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Abstract. Currently the hardware design of adder and multiplier is quite mature, the principle of which is to map addition or multiplication operations into a series of logic computations. While the various optimization approaches have reached their limits, and hardware divider cannot be achieved still. The ancient Chinese abacus operates based on pithy formula, fulfilling kinds of computations including division fast and accurately. Yet the essence of it is not fully exploited. In this study, the hardware adder in view of the principle of abacus algorithm and operation prototype has been designed, verified on FPGA and superior to existing adders that are fully optimized. This offers broad research space to further optimize hardware multiplier or even achieve hardware divider.

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Ghabri, H., D. Ben Issa, and H. Samet. "Performance Optimization of 1-bit Full Adder Cell based on CNTFET Transistor." Engineering, Technology & Applied Science Research 9, no. 6 (December 1, 2019): 4933–36. http://dx.doi.org/10.48084/etasr.3156.

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The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

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S, Haroon Rasheed, Mohan Das S, and Samba Sivudu Gaddam. "DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS." International Journal of Engineering Technology and Management Sciences 4, no. 6 (September 28, 2020): 15–18. http://dx.doi.org/10.46647/ijetms.2020.v04i06.004.

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This paper presents an energy efficient 1-bit full adder designed with a low voltage and high performance internal logic cells which leads to have abridged Power Delay Product (PDP). The customized XNOR and XOR gates, a necessary entity, are also presented. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 1-bit adder cell is compared with various trendy adders based on speed, power consumption and energy (PDP). The proposed adder schemes with modified internal entity cells achieve significant savings in terms of delay and energy consumption and which are more than 77% and 40.47% respectively when compared with conventional “C-CMOS” 1-bit full adder and other counter parts.

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Feizi, Khadijeh, and Ali Shahhoseini. "Design of Quaternary Half Adder Using Hybrid SETMOS Cell." Applied Mechanics and Materials 110-116 (October 2011): 5085–89. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5085.

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Adder is one of the important arithmetic units in computers. In this paper, we investigate the implementation of quaternary half adder based on multiple-valued (MV) logic gates using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. We use hybrid SETMOS universal literal gate which has been proposed by Mahapatra and Ionesco. We apply two 4-radix inputs to the proposed quaternary half adder and obtain sum and carry outputs. The logic operation of the proposed quaternary half adder is verified by using HSPICE simulator. Moreover we compare the performance of our proposed quaternary half adder with the performance of a quaternary half adder based on MOS technology.

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Becker, Bernd, and Reiner Kolla. "On the Construction of Optimal Time Adders." Fundamenta Informaticae 12, no. 2 (April 1, 1989): 205–20. http://dx.doi.org/10.3233/fi-1989-12207.

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In this paper we present the design of a novel optimal time adder: the conditional carry adder. In order to perform addition a tree-like combination of multiplexer cells is used in the carry computation part. We show that, for the complete conditional carry adder, this results in an overall computation time which seems to be substantially shorter than for any other known (optimal time) adder (e.g. carry look ahead adders ([5]) or conditional sum adders ([12])). The second part of this paper contains a uniform approach to the computation of the carry function resulting in seven different classes of optimal time adders. It is shown that the conditional carry adder and the carry look ahead adder are representatives of two different classes. While section 1 defines the conditional carry adder and proposes a realization which is very time efficient, section 2 provides the possibility to compare this choice with other possible realizations and to choose a different design depending e.g. on specific properties of a given technology.

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A, Vishnupriya, and Sudarmani R. "Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder." International Journal of Computer Applications 67, no. 6 (April 18, 2013): 33–38. http://dx.doi.org/10.5120/11401-6717.

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., Gulivindala Suresh. "PERFORMANCE EVALUATION OF FULL ADDER AND ITS IMPACT ON RIPPLE CARRY ADDER DESIGN." International Journal of Research in Engineering and Technology 03, no. 16 (May 25, 2014): 23–28. http://dx.doi.org/10.15623/ijret.2014.0316005.

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Dalloo, Ayad, Ardalan Najafi, and Alberto Garcia-Ortiz. "Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 8 (August 2018): 1595–99. http://dx.doi.org/10.1109/tvlsi.2018.2822278.

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Sen, Bibhash, Ayush Rajoria, and Biplab K. Sikdar. "Design of Efficient Full Adder in Quantum-Dot Cellular Automata." Scientific World Journal 2013 (2013): 1–10. http://dx.doi.org/10.1155/2013/250802.

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Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

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SaiAbhinav, B., M. Jaipal Reddy, Y. Siva Kumar, and S. Sivanantham S.Sivanantham. "ASIC Design of Reversible Adder and Multiplier." International Journal of Computer Applications 109, no. 10 (January 16, 2015): 6–10. http://dx.doi.org/10.5120/19222-0638.

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ZHANG, Zhen, and Jing FENG. "Design of high performance barrel integer adder." Journal of Computer Applications 30, no. 11 (December 14, 2010): 3138–40. http://dx.doi.org/10.3724/sp.j.1087.2010.03138.

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Lin, Jin-Fa. "Low Power Latch-adder Based Multiplier Design." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 17, no. 6 (December 31, 2017): 806–14. http://dx.doi.org/10.5573/jsts.2017.17.6.806.

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