Relevant bibliographies by topics / Adiabatic Circuits

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Adiabatic Circuits'

Author: Grafiati
Published: 4 June 2025
Last updated: 23 June 2025

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Journal articles on the topic "Adiabatic Circuits"

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Shinghal, Deepti, Amit Saxena, and Arti Noor. "Comparative Analysis of Conventional CMOS and Adiabatic Logic Gates." MIT International Journal of Electronics and Communication Engineering 4, no. 1 (2014): 39–43. https://doi.org/10.5281/zenodo.5406915.

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This paper deals with comparative study of conventional CMOS circuits with CMOS based reversible logic circuits employing Adiabatic switching methods. The power dissipation an important characteristic is tested by means of SPICE circuit simulation techniques for a CMOS AND-OR-INVERTER (AOI) gate. Results from both conventional and adiabatic logic switching simulations are compared. The breakdown of adiabatic operation for these reversible circuits, due to the finite threshold voltages, is tested by checking the logic circuit node current/voltage transient waveform during the logic switching transitions. On the basis of simulation results conclusion has been derived that the performance of reversible logic circuits employing adiabatic switching is better than conventional switching in terms of power dissipation.
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Schlachta, C., and M. Glesner. "Resonance circuits for adiabatic circuits." Advances in Radio Science 1 (May 5, 2003): 223–28. http://dx.doi.org/10.5194/ars-1-223-2003.

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Abstract. One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.
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Saxena, Amit, Deepti Shinghal, and Arti Noor. "POWER EFFICIENT ADIABATIC SWITCHING CIRCUITS." MIT International Journal of Electronics and Communication Engineering 3, no. 2 (2013): 98–103. https://doi.org/10.5281/zenodo.5408158.

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This paper deals with design opportunities of CMOS based reversible logic circuits employing adiabatic switching methods. The power dissipation an important characteristics are tested by means of SPICE circuit simulation techniques for a CMOS transmission gate based reversible logic circuits, such as Controlled Not gates & Controlled Controlled Not gate. Results from both conventional and adiabatic logic switching simulations are compared. The breakdown of adiabatic operation for these reversible circuits, due to the finite threshold voltages, is tested by checking the logic circuit node current/voltage transient waveform during the logic switching transitions. On the basis of simulation results conclusion has been derived that the performance of reversible logic circuits employing adiabatic switching is better than conventional switching in terms of a factor-power dissipation.
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Upadhyay, Shipra, R. A. Mishra, R. K. Nagaria, and S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits." ISRN Electronics 2013 (February 10, 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.

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The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.
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Mei, Feng Na, and Peng Jun Wang. "Design of Ternary Clocked Adiabatic Synchronous Reversible Counter." Applied Mechanics and Materials 88-89 (August 2011): 154–59. http://dx.doi.org/10.4028/www.scientific.net/amm.88-89.154.

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Based on the study of synchronous counter and adiabatic circuits, a new design scheme of ternary adiabatic synchronous reversible counter is proposed. According to the theory of three essential circuit elements, circuit structure of four-bit ternary adiabatic synchronous reversible counter is realized by using NMOS transistors with different thresholds and cross-storage structure and combining with the principle of energy recovery. Computer simulation results indicate that the designed circuits have correct logic function. Compared with traditional CMOS counter, the average power consumption of circuits saves up to 67.5%.
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Shinghal, Deepti, Amit Saxena, and Arti Noor. "Adiabatic Logic Circuits: A Retrospect." MIT International Journal of Electronics and Communication Engineering 3, no. 2 (2013): 108–14. https://doi.org/10.5281/zenodo.5406139.

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With ever-increasing growth in VLSI technologies the number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. Then, to limit the power dissipation adiabatic operation promises large reductions of power consumption because it does not dissipate energy. This paper reviews different types of adiabatic logic families. First, adiabatic logic circuits working principle is discussed. Next, adiabatic switching and how it can be used to conserve power is discussed. Also reviewed is an adiabatic logic gate alongwith its circuit. Finally, adiabatic logic family is covered, which can be classified as fully and partially adiabatic alongwith discussion circuit diagram and details of each. This review also covers some important future research directions.
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Kordetoodeshki, Elham, and Alireza Hassanzadeh. "Design of Low Voltage Low Power DC–DC Converters Using Adiabatic Technique." Journal of Circuits, Systems and Computers 27, no. 06 (2018): 1850094. http://dx.doi.org/10.1142/s0218126618500949.

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In this paper two low voltage, low power DC–DC converter circuits have been designed with input voltages as low as 290[Formula: see text]mV to 500[Formula: see text]mV. Adiabatic technique has been used to reduce power consumption and increase the efficiency of the charge pump of the converters. Boost converter circuits are simulated and the efficiency and power consumption are improved using adiabatic technique. Optimum capacitor bank and rise time–fall time values have been obtained for the adiabatic circuits. Power consumption for the doubler circuit with 310[Formula: see text]mV input decreases by 67% using adiabatic technique and 0.18[Formula: see text][Formula: see text]m CMOS technology parameters.
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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.
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Jiang, Jin Tao, Yu Zhang, and Jian Ping Hu. "P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits." Advanced Materials Research 159 (December 2010): 155–61. http://dx.doi.org/10.4028/www.scientific.net/amr.159.155.

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With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.
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Ni, Hai Yan, and Jian Ping Hu. "Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes." Key Engineering Materials 460-461 (January 2011): 837–42. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.837.

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This paper presents adiabatic flip-flops operating on near-threshold supply voltages. The near-threshold adiabatic flip-flops and sequential circuits are realized with improved CAL (Clocked Adiabatic Logic) circuits using a single-phase power clock. An auxiliary clock generator is used to obtain the non-overlap sinusoidal auxiliary signal pair. A near-threshold mode-10 counter is implemented. All circuits are simulated using Predictive Technology Model (PTM) 45nm process. The near-threshold adiabatic circuits attain large energy savings over a wide range of frequencies, as compared with conventional static CMOS logic circuits.
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Dissertations / Theses on the topic "Adiabatic Circuits"

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Suram, Ragini. "Low power adiabatic circuits and power clocks for driving adiabatic circuits /." free to MU campus, to others for purchase, 2003. http://wwwlib.umi.com/cr/mo/fullcit?p1418070.

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Raghav, Himadri Singh. "Adiabatic circuits for power-constrained cryptographic computations." Thesis, University of Westminster, 2018. https://westminsterresearch.westminster.ac.uk/item/q948q/adiabatic-circuits-for-power-constrained-cryptographic-computations.

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This thesis tackles the need for ultra-low power operation in power-constrained cryptographic computations. An example of such an application could be smartcards. One of the techniques which has proven to have the potential of rendering ultra-low power operation is ‘Adiabatic Logic Technique’. However, the adiabatic circuits has associated challenges due to high energy dissipation of the Power-Clock Generator (PCG) and complexity of the multi-phase power-clocking scheme. Energy efficiency of the adiabatic system is often degraded due to the high energy dissipation of the PCG. In this thesis, nstep charging strategy using tank capacitors is considered for the power-clock generation and several design rules and trade-offs between the circuit complexity and energy efficiency of the PCG using n-step charging circuits have been proposed. Since pipelining is inherent in adiabatic logic design, careful selection of architecture is essential, as otherwise overhead in terms of area and energy due to synchronization buffers is induced specifically, in the case of adiabatic designs using 4-phase power-clocking scheme. Several architectures for the Montgomery multiplier using adiabatic logic technique are implemented and compared. An architecture which constitutes an appropriate trade-off between energy efficiency and throughput is proposed along with its methodology. Also, a strategy to reduce the overhead due to synchronization buffers is proposed. A modification in the Montgomery multiplication algorithm is proposed. Furthermore, a problem due to the application of power-clock gating in cascade stages of adiabatic logic is identified. The problem degrades the energy savings that would otherwise be obtained by the application of power-clock gating. A solution to this problem is proposed. Cryptographic implementations also present an obvious target for Power Analysis Attacks (PAA). There are several existing secure adiabatic logic designs which are proposed as a countermeasure against PAA. Shortcomings of the existing logic designs are identified, and two novel secure adiabatic logic designs are proposed as the countermeasures against PAA and improvement over the existing logic designs.
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Morrison, Matthew Arthur. "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications." Scholar Commons, 2013. https://scholarcommons.usf.edu/etd/5082.

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Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Adiabatic logic is a design methodology for reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architectures. Production of cost-effective Secure Integrated Chips, such as Smart Cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. In order to design successful security-centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms such as AES and Triple DES by preventing side channel attacks, such as Differential Power Analysis (DPA). Dynamic logic obfuscates the output waveforms and the circuit operation, reducing the effectiveness of the DPA attack. Significant research exists in the design and analysis of locally optimal adiabatic elements towards mitigation of side channel attacks. However, none of these works have addressed the use of adiabatic logic in implementation of flexible and programmable hardware security policies. Nor has adiabatic logic been employed in hardware security applications such as trustworthy voting systems and data encryption standards. In this dissertation, I address theory, synthesis, and application of adiabatic and reversible logic circuits for security applications. First, two major debates in reversible computing are addressed. These debates must be addressed in order to devise computational logic primitives in any emerging quantum computing technology. First, we address whether charged based computing is limited due to the use of charge as a state variable. We propose the use of body biasing in CMOS adiabatic systems as a design methodology for reducing the need for gradually changing the energy barriers. Simulation results in HSPICE at 22nm are presented which show behavior of a source-memory device operating at sub-Landauer operation. Second, we address whether reversible logic can be used to design sequential computing structures, such as memory devices. we present an analysis of Quantum Turing Machines with sequential reversible logic structures, to show that the entropy gain is substantially less than the Landauer Barrier of kTln(2), which is the limiting factor for irreversible computing. A mathematical proof is presented showing bit erasure does not occur in sequential reversible logic structures, and that these devices are physically reversible as long as appropriate delay elements are inserted in the feedback paths to prevent race conditions. This proof validates implementation of sequential reversible logic towards ultra-low power computing. Next, a novel algorithm for synthesis of adiabatic circuits in CMOS is proposed. This approach is unique because it correlates the offsets in the permutation matrix to the transistors required for synthesis, instead of determining an equivalent circuit and substituting a previously synthesized circuit from a library. Parallelism is used, and the bijective properties of the device to achieve synthesis of the logic structure in O(n) time. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node in parallel, we optimize the synthesized circuit. It is demonstrated that the algorithm produces a 32.86% improvement over previously synthesized circuit benchmarks. For stronger mitigation of DPA attacks, we propose the implementation of Adiabatic Dynamic Differential Logic for applications in secure IC design. Such an approach is effective in reducing power consumption, demonstrated using HSPICE simulations with 22nm predictive technology. The benefits of our design are demonstrated by comparing instantaneous power waveforms and observing the magnitude of differential power spikes during switching events. First, simulation results for body-biasing on sub-threshold adiabatic inverters show an improvement in differential power up to 43.28% for similar inverters without body biasing. Then, a High Performance Adiabatic Dynamic Differential Logic (PADDL) is presented for an implementation in high frequency secure ICs. This method improves the differential power over previous dynamic and differential logic methods by up to 89.65%. Finally, we propose a Body-Biased Adiabatic Dynamic Differential Logic (BADDL) for ultra-low power applications. Simulation results show that the differential power was improved upon by a factor of 199.16. Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse.
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Vikstål, Pontus. "Continuous-variable quantum annealing with superconducting circuits." Thesis, Linköpings universitet, Institutionen för fysik, kemi och biologi, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-151889.

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Quantum annealing is expected to be a powerful generic algorithm for solving hard combinatorial optimization problems faster than classical computers. Finding the solution to a combinatorial optimization problem is equivalent to finding the ground state of an Ising Hamiltonian. In today's quantum annealers the spins of the Ising Hamiltonian are mapped to superconducting qubits. On the other hand, dissipation processes degrade the success probability of finding the solution. In this thesis we set out to explore a newly proposed architecture for a noise-resilient quantum annealer that instead maps the Ising spins to continuous variable quantum states of light encoded in the field quadratures of a two-photon pumped Kerr- nonlinear resonator based on the proposal by Puri et al. (2017). In this thesis we study the Wigner negativity for this newly proposed architecture and evaluate its performance based on the negativity of the Wigner function. We do this by determining an experimental value to when the presence of losses become too detrimental, such that the Wigner function of the quantum state during the evolution within the anneal becomes positive for all times. Furthermore, we also demonstrate the capabilities of this continuous variable quantum annealer by simulating and finding the best solution of a small instance of the NP-complete subset sum problem and of the number partitioning problem.
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Bapat, Akhilesh V. "Experimental and numerical evaluation of single phase adiabatic flows in plain and enhanced microchannels /." Online version of thesis, 2007. http://hdl.handle.net/1850/5536.

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Mohammad, Azhar. "EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/125.

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The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on some of those emerging and novel low power design technique namely Adiabatic logic and low power devices like Magnetic Tunnel Junction (MTJ) and Carbon Nanotube Field Effect transistor (CNFET). Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.
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Duprez, Hélène. "From design to characterization of III-V on silicon lasers for photonic integrated circuits." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEC005/document.

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Ces trois années de thèse balayent la conception, la fabrication et la caractérisation de lasers III V sur silicium à 1.31 µm pour les data-communications. Le design des sources englobe notamment l’optimisation du couplage entre l’empilement III V et le silicium, effectué grâce à un taper adiabatique, ainsi que l’étude de la cavité laser inscrite, comme le taper, dans le silicium. Trois types de cavités à base de réseaux ont été étudiées: les cavités à contre-réaction distribuée (DFB pour distributed feedback), celles à réseaux de Bragg distribuées (DBR pour distributed Bragg reflector) et enfin celles à réseaux de Bragg échantillonnées (SGDBR pour sampled-grating DBR). Deux solutions ont été abordées concernant les lasers DFB: le réseau, inscrit dans le guide silicium sous la zone de gain, est soit gravé au-dessus du guide Si, soit sur les côtés. La seconde possibilité, appelée ‘DFB lasers couplés latéralement’, simplifie la fabrication et élargit les possibilités de design.Les lasers DFB fabriqués sont très prometteurs en terme de puissance (avec jusque 20 mW dans le guide) ainsi que pour leur pureté spectrale (avec une différence de plus de 50 dB entre le mode principal et le mode suivant). Une accordabilité spectrale de plus de 27 nm a été obtenue en continu avec les lasers SGDBR tout en conservant une très bonne pureté spectrale et une puissance de plus de 7 mW dans le guide<br>This 3 years work covers the design, the process and the characterization of III-V on silicon lasers at 1.31 µm for datacommunication applications. In particular, the design part includes the optimization of the coupling between III V and Si using adiabatic tapers as well as the laser cavity, which is formed within the Si. Three types of lasers were studied, all of them based on cavities which consist of gratings: distributed feedback (DFB) lasers, distributed Bragg reflector (DBR) lasers and finally sampled-grating DBR (SGDBR) lasers. Regarding the DFB lasers, two solutions have been chosen: the grating is either etched on top or on the edges of the Si waveguide to form so called vertically or laterally coupled DFB lasers. The latter type, quite uncommon among hybrid III V on Si technologies, simplifies the process fabrication and broadens the designs possibilities.Not only the lasers demonstrated show high output powers (~20 mW in the waveguides) but also very good spectral purities (with a side mode suppression ratio higher than 50 dB), especially for the DFB ones. The SGDBR devices turn out to be continuously tunable over a wavelength range higher than 27 nm with a good spectral purity as well and an output power higher than 7 mW in the waveguide with great opportunities of improvement
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Selvakumaran, Dinesh Kumar. "ENERGY-EFFICIENT AND SECURE HARDWARE FOR INTERNET OF THINGS (IoT) DEVICES." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/132.

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Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices. Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks. Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack. Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation. Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique. The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations.
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Lamponi, Marco. "Lasers inp sur circuits silicium pour applications en telecommunications." Phd thesis, Université Paris Sud - Paris XI, 2012. http://tel.archives-ouvertes.fr/tel-00769402.

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La photonique du silicium a connu un développent massif pendant les dix derniers années. Presque toutes les briques technologiques de base ont été réalisées et ont démontrées des performances remarquables. Cependant, le manque d'une source laser intégrée en silicium a conduit les chercheurs à développer de composants basés sur l'intégration entre le silicium et les matériaux III-V.Dans cette thèse je décris la conception, la fabrication et la caractérisation des lasers hybrides III-V sur silicium basés sur cette intégration. Je propose un coupleur adiabatique qui permet de transférer intégralement le mode optique du guide silicium au guide III-V. Le guide actif III-V au centre du composant fourni le gain optique et les coupleurs, des deux cotés, assurent le transfert de la lumière dans les guides silicium.Les lasers mono longueur d'onde sont des éléments fondamentaux des communications optiques. Je décris les différentes solutions permettant d'obtenir un laser mono-longueur d'onde hybride III-V sur silicium. Des lasers mono longueur d'onde ont été fabriqués et caractérisés. Ils démontrent un seuil de 21 mA, une puissance de sortie qui dépasse 10 mW et une accordabilité de 45 nm. Ces composants représentent la première démonstration d'un laser accordable hybride III-V sur silicium.
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Jeanniot, Nicolas. "Conception et optimisation d'une alimentation-horloge et d'un réseau de distribution pour la logique adiabatique." Thesis, Montpellier, 2018. http://www.theses.fr/2018MONTS068/document.

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La densité de puissance est devenue la principale préoccupation lorsqu'un circuit numérique est conçu. Comme pour tous les systèmes embarqués, chaque nouvelle génération de système numérique a plus d'applications que la précédente et exige en fin de compte une plus grande densité de puissance. C'est pourquoi de nombreux chercheurs et concepteurs industriels se sont penchés sur de nouvelles méthodes de réduction de la consommation énergétique des circuits numériques. La logique adiabatique est un style de conception prometteur qui peut réduire la dissipation d'énergie dynamique. La logique adiabatique est différente de la logique conventionnelle en deux principaux points : 1) l’alimentation d’une porte logique adiabatique est un signal à 4 phases, et 2) l’énergie stockée dans la porte est récupérée. Afin de respecter ces principes, la logique adiabatique nécessite une alimentation spéciale. Étant donné que l’objectif d’une telle alimentation est d’agir comme une horloge, elle est appelée alimentation-horloge. L'objectif de cette thèse est de concevoir et d'optimiser une alimentation-horloge ainsi que son réseau de distribution. Cette thèse a été financée par l'Agence Nationale pour la Recherche, ANR, avec le projet ADIANEMS2 (numéro de subvention : ANR-15-CE24-0013)<br>Power density has become the primary concern when a digital core is designed. As in any embedded systems, each new digital core generation has more applications than the previous one and ultimately demands more power density. This is why many researchers and industrial designers have been looking into novel methods for reducing power consumption of digital circuit. Adiabatic logic is a promising design style, which can reduce the dynamic energy dissipation. Adiabatic logic is different than conventional logic in two main points: 1) adiabatic gate are charged with a 4-phase power signal, and 2) the energy, which is stored in the gate, is recovered. In order to fulfill these principles, the adiabatic logic needs a special power supply. As the purpose of such supply is to act as a clock also, it is referred as power-clock supply. The aim of this thesis is to design and optimize a power-clock supply and its delivery network. This thesis has been funded by the French National Research Agency, ANR, with the project ADIANEMS2 (Grant number: ANR-15-CE24-0013)
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Books on the topic "Adiabatic Circuits"

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Teichmann, Philip. Adiabatic Logic: Future Trend and System Level Perspective. Springer London, Limited, 2011.

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Teichmann, Philip. Adiabatic Logic: Future Trend and System Level Perspective. Springer, 2013.

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Teichmann, Philip. Adiabatic Logic: Future Trend and System Level Perspective. Springer, 2011.

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Adiabatic Logic Future Trend And System Level Perspective. Springer, 2011.

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Tiwari, Sandip. Information mechanics. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780198759874.003.0001.

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Abstract:
Information is physical, so its manipulation through devices is subject to its own mechanics: the science and engineering of behavioral description, which is intermingled with classical, quantum and statistical mechanics principles. This chapter is a unification of these principles and physical laws with their implications for nanoscale. Ideas of state machines, Church-Turing thesis and its embodiment in various state machines, probabilities, Bayesian principles and entropy in its various forms (Shannon, Boltzmann, von Neumann, algorithmic) with an eye on the principle of maximum entropy as an information manipulation tool. Notions of conservation and non-conservation are applied to example circuit forms folding in adiabatic, isothermal, reversible and irreversible processes. This brings out implications of fluctuation and transitions, the interplay of errors and stability and the energy cost of determinism. It concludes discussing networks as tools to understand information flow and decision making and with an introduction to entanglement in quantum computing.
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Book chapters on the topic "Adiabatic Circuits"

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Pal, Ajit. "Adiabatic Logic Circuits." In Low-Power VLSI Circuits and Systems. Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-1937-8_10.

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Fischer, Jürgen, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, and Doris Schmitt-Landsiedel. "Power Supply Net for Adiabatic Circuits." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_43.

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Jahan, C. S. Shari, and Hardeep Kumar. "RERL Circuits Design Using Adiabatic Technique." In Proceedings of the 7th International Conference on Advance Computing and Intelligent Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-5015-7_27.

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Sharma, Himani, Nidhi Sharma, and Surya Deo Choudhary. "Designing Adiabatic Techniques for Logic Circuits." In Modern Electronics Devices and Communication Systems. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6383-4_5.

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Teichmann, Philip, Jürgen Fischer, Stephan Henzler, Ettore Amirante, and Doris Schmitt-Landsiedel. "Power-Clock Gating in Adiabatic Logic Circuits." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11556930_65.

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C.S., Shari Jahan, and N. Kayalvizhi. "Adiabatic Technique for Designing Energy Efficient Logic Circuits." In Eco-friendly Computing and Communication Systems. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-32112-2_13.

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Knapp, Micah C., Peter J. Kindlmann, and Marios C. Papaefthymiou. "Design and Evaluation of Adiabatic Arithmetic Units." In Analog Design Issues in Digital VLSI Circuits and Systems. Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6101-9_7.

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Hu, Jianping, Hong Li, and Yangbo Wu. "Low-Power Register File Based on Adiabatic Logic Circuits." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_37.

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Hu, Jianping, and Binbin Liu. "Energy Efficient Medium-Voltage Circuits Based on Adiabatic CPL." In Communications in Computer and Information Science. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19853-3_80.

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Houri, Samer, Alexandre Valentian, and Hervé Fanet. "Comparing CMOS-Based and NEMS-Based Adiabatic Logic Circuits." In Reversible Computation. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38986-3_4.

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Conference papers on the topic "Adiabatic Circuits"

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Ayala, Christopher L., Nobuyuki Yoshikawa, Yu Hoshika, and Yuto Omori. "Multi-GHz Zeptojoule Computing Using Emerging Adiabatic Superconductor Circuits." In 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2024. http://dx.doi.org/10.1109/isvlsi61997.2024.00106.

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Liu, Jiaming, and Yasuhiro Takahashi. "Design of Low-Power 6T Adiabatic PUF Circuit." In 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2024. https://doi.org/10.1109/apccas62602.2024.10808318.

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Nagata, Shoya, and Yasuhiro Takahashi. "A Design of PUF Circuit Using Adiabatic Logic." In 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2024. https://doi.org/10.1109/apccas62602.2024.10808900.

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Afsary, Noor, Md Koushik Alam, Zarin Tasnim Nijhum, Md Rahat Ali, Karimul Hoque, and Md Omar Faruk Rasel. "Broadband Graded Index 3dB Adiabatic Coupler for Photonic Integrated Circuits." In 2024 IEEE International Conference on Power, Electrical, Electronics and Industrial Applications (PEEIACON). IEEE, 2024. https://doi.org/10.1109/peeiacon63629.2024.10800285.

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Ribeiro, Bendito Freitas, and Yasuhiro Takahashi. "A New Adiabatic Logic Circuit for RF Energy Harvesting." In 2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC). IEEE, 2024. http://dx.doi.org/10.1109/itc-cscc62988.2024.10628352.

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Zulehner, Alwin, Michael P. Frank, and Robert Wille. "Design automation for adiabatic circuits." In ASPDAC '19: 24th Asia and South Pacific Design Automation Conference. ACM, 2019. http://dx.doi.org/10.1145/3287624.3287673.

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Frank, David J., and Paul M. Solomon. "Electroid-oriented adiabatic switching circuits." In the 1995 international symposium. ACM Press, 1995. http://dx.doi.org/10.1145/224081.224116.

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Jianping Hu, Ling Wang, and Huiying Dong. "Interface circuits between adiabatic and standard CMOS circuits." In 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/mwscas.2007.4488646.

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Henzler, Stephan, Thomas Nirschl, Matthias Eireiner, Ettore Amirante, and Doris Schmitt-Landsiedel. "Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits." In the 2nd conference. ACM Press, 2005. http://dx.doi.org/10.1145/1062261.1062331.

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Arsalan, Muhammad, and Maitham Shams. "Asynchronous Adiabatic Logic." In 2007 IEEE International Symposium on Circuits and Systems. IEEE, 2007. http://dx.doi.org/10.1109/iscas.2007.378651.

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