Dissertations / Theses on the topic 'Adiabatic Circuits'

This thesis tackles the need for ultra-low power operation in power-constrained cryptographic computations. An example of such an application could be smartcards. One of the techniques which has proven to have the potential of rendering ultra-low power operation is ‘Adiabatic Logic Technique’. However, the adiabatic circuits has associated challenges due to high energy dissipation of the Power-Clock Generator (PCG) and complexity of the multi-phase power-clocking scheme. Energy efficiency of the adiabatic system is often degraded due to the high energy dissipation of the PCG. In this thesis, nstep charging strategy using tank capacitors is considered for the power-clock generation and several design rules and trade-offs between the circuit complexity and energy efficiency of the PCG using n-step charging circuits have been proposed. Since pipelining is inherent in adiabatic logic design, careful selection of architecture is essential, as otherwise overhead in terms of area and energy due to synchronization buffers is induced specifically, in the case of adiabatic designs using 4-phase power-clocking scheme. Several architectures for the Montgomery multiplier using adiabatic logic technique are implemented and compared. An architecture which constitutes an appropriate trade-off between energy efficiency and throughput is proposed along with its methodology. Also, a strategy to reduce the overhead due to synchronization buffers is proposed. A modification in the Montgomery multiplication algorithm is proposed. Furthermore, a problem due to the application of power-clock gating in cascade stages of adiabatic logic is identified. The problem degrades the energy savings that would otherwise be obtained by the application of power-clock gating. A solution to this problem is proposed. Cryptographic implementations also present an obvious target for Power Analysis Attacks (PAA). There are several existing secure adiabatic logic designs which are proposed as a countermeasure against PAA. Shortcomings of the existing logic designs are identified, and two novel secure adiabatic logic designs are proposed as the countermeasures against PAA and improvement over the existing logic designs.

Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Adiabatic logic is a design methodology for reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architectures. Production of cost-effective Secure Integrated Chips, such as Smart Cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. In order to design successful security-centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms such as AES and Triple DES by preventing side channel attacks, such as Differential Power Analysis (DPA). Dynamic logic obfuscates the output waveforms and the circuit operation, reducing the effectiveness of the DPA attack. Significant research exists in the design and analysis of locally optimal adiabatic elements towards mitigation of side channel attacks. However, none of these works have addressed the use of adiabatic logic in implementation of flexible and programmable hardware security policies. Nor has adiabatic logic been employed in hardware security applications such as trustworthy voting systems and data encryption standards. In this dissertation, I address theory, synthesis, and application of adiabatic and reversible logic circuits for security applications. First, two major debates in reversible computing are addressed. These debates must be addressed in order to devise computational logic primitives in any emerging quantum computing technology. First, we address whether charged based computing is limited due to the use of charge as a state variable. We propose the use of body biasing in CMOS adiabatic systems as a design methodology for reducing the need for gradually changing the energy barriers. Simulation results in HSPICE at 22nm are presented which show behavior of a source-memory device operating at sub-Landauer operation. Second, we address whether reversible logic can be used to design sequential computing structures, such as memory devices. we present an analysis of Quantum Turing Machines with sequential reversible logic structures, to show that the entropy gain is substantially less than the Landauer Barrier of kTln(2), which is the limiting factor for irreversible computing. A mathematical proof is presented showing bit erasure does not occur in sequential reversible logic structures, and that these devices are physically reversible as long as appropriate delay elements are inserted in the feedback paths to prevent race conditions. This proof validates implementation of sequential reversible logic towards ultra-low power computing. Next, a novel algorithm for synthesis of adiabatic circuits in CMOS is proposed. This approach is unique because it correlates the offsets in the permutation matrix to the transistors required for synthesis, instead of determining an equivalent circuit and substituting a previously synthesized circuit from a library. Parallelism is used, and the bijective properties of the device to achieve synthesis of the logic structure in O(n) time. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node in parallel, we optimize the synthesized circuit. It is demonstrated that the algorithm produces a 32.86% improvement over previously synthesized circuit benchmarks. For stronger mitigation of DPA attacks, we propose the implementation of Adiabatic Dynamic Differential Logic for applications in secure IC design. Such an approach is effective in reducing power consumption, demonstrated using HSPICE simulations with 22nm predictive technology. The benefits of our design are demonstrated by comparing instantaneous power waveforms and observing the magnitude of differential power spikes during switching events. First, simulation results for body-biasing on sub-threshold adiabatic inverters show an improvement in differential power up to 43.28% for similar inverters without body biasing. Then, a High Performance Adiabatic Dynamic Differential Logic (PADDL) is presented for an implementation in high frequency secure ICs. This method improves the differential power over previous dynamic and differential logic methods by up to 89.65%. Finally, we propose a Body-Biased Adiabatic Dynamic Differential Logic (BADDL) for ultra-low power applications. Simulation results show that the differential power was improved upon by a factor of 199.16. Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse.

Quantum annealing is expected to be a powerful generic algorithm for solving hard combinatorial optimization problems faster than classical computers. Finding the solution to a combinatorial optimization problem is equivalent to finding the ground state of an Ising Hamiltonian. In today's quantum annealers the spins of the Ising Hamiltonian are mapped to superconducting qubits. On the other hand, dissipation processes degrade the success probability of finding the solution. In this thesis we set out to explore a newly proposed architecture for a noise-resilient quantum annealer that instead maps the Ising spins to continuous variable quantum states of light encoded in the field quadratures of a two-photon pumped Kerr- nonlinear resonator based on the proposal by Puri et al. (2017). In this thesis we study the Wigner negativity for this newly proposed architecture and evaluate its performance based on the negativity of the Wigner function. We do this by determining an experimental value to when the presence of losses become too detrimental, such that the Wigner function of the quantum state during the evolution within the anneal becomes positive for all times. Furthermore, we also demonstrate the capabilities of this continuous variable quantum annealer by simulating and finding the best solution of a small instance of the NP-complete subset sum problem and of the number partitioning problem.

The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on some of those emerging and novel low power design technique namely Adiabatic logic and low power devices like Magnetic Tunnel Junction (MTJ) and Carbon Nanotube Field Effect transistor (CNFET). Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.

Ces trois années de thèse balayent la conception, la fabrication et la caractérisation de lasers III V sur silicium à 1.31 µm pour les data-communications. Le design des sources englobe notamment l’optimisation du couplage entre l’empilement III V et le silicium, effectué grâce à un taper adiabatique, ainsi que l’étude de la cavité laser inscrite, comme le taper, dans le silicium. Trois types de cavités à base de réseaux ont été étudiées: les cavités à contre-réaction distribuée (DFB pour distributed feedback), celles à réseaux de Bragg distribuées (DBR pour distributed Bragg reflector) et enfin celles à réseaux de Bragg échantillonnées (SGDBR pour sampled-grating DBR). Deux solutions ont été abordées concernant les lasers DFB: le réseau, inscrit dans le guide silicium sous la zone de gain, est soit gravé au-dessus du guide Si, soit sur les côtés. La seconde possibilité, appelée ‘DFB lasers couplés latéralement’, simplifie la fabrication et élargit les possibilités de design.Les lasers DFB fabriqués sont très prometteurs en terme de puissance (avec jusque 20 mW dans le guide) ainsi que pour leur pureté spectrale (avec une différence de plus de 50 dB entre le mode principal et le mode suivant). Une accordabilité spectrale de plus de 27 nm a été obtenue en continu avec les lasers SGDBR tout en conservant une très bonne pureté spectrale et une puissance de plus de 7 mW dans le guide<br>This 3 years work covers the design, the process and the characterization of III-V on silicon lasers at 1.31 µm for datacommunication applications. In particular, the design part includes the optimization of the coupling between III V and Si using adiabatic tapers as well as the laser cavity, which is formed within the Si. Three types of lasers were studied, all of them based on cavities which consist of gratings: distributed feedback (DFB) lasers, distributed Bragg reflector (DBR) lasers and finally sampled-grating DBR (SGDBR) lasers. Regarding the DFB lasers, two solutions have been chosen: the grating is either etched on top or on the edges of the Si waveguide to form so called vertically or laterally coupled DFB lasers. The latter type, quite uncommon among hybrid III V on Si technologies, simplifies the process fabrication and broadens the designs possibilities.Not only the lasers demonstrated show high output powers (~20 mW in the waveguides) but also very good spectral purities (with a side mode suppression ratio higher than 50 dB), especially for the DFB ones. The SGDBR devices turn out to be continuously tunable over a wavelength range higher than 27 nm with a good spectral purity as well and an output power higher than 7 mW in the waveguide with great opportunities of improvement

Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices. Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks. Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack. Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation. Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique. The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations.

La photonique du silicium a connu un développent massif pendant les dix derniers années. Presque toutes les briques technologiques de base ont été réalisées et ont démontrées des performances remarquables. Cependant, le manque d'une source laser intégrée en silicium a conduit les chercheurs à développer de composants basés sur l'intégration entre le silicium et les matériaux III-V.Dans cette thèse je décris la conception, la fabrication et la caractérisation des lasers hybrides III-V sur silicium basés sur cette intégration. Je propose un coupleur adiabatique qui permet de transférer intégralement le mode optique du guide silicium au guide III-V. Le guide actif III-V au centre du composant fourni le gain optique et les coupleurs, des deux cotés, assurent le transfert de la lumière dans les guides silicium.Les lasers mono longueur d'onde sont des éléments fondamentaux des communications optiques. Je décris les différentes solutions permettant d'obtenir un laser mono-longueur d'onde hybride III-V sur silicium. Des lasers mono longueur d'onde ont été fabriqués et caractérisés. Ils démontrent un seuil de 21 mA, une puissance de sortie qui dépasse 10 mW et une accordabilité de 45 nm. Ces composants représentent la première démonstration d'un laser accordable hybride III-V sur silicium.

La densité de puissance est devenue la principale préoccupation lorsqu'un circuit numérique est conçu. Comme pour tous les systèmes embarqués, chaque nouvelle génération de système numérique a plus d'applications que la précédente et exige en fin de compte une plus grande densité de puissance. C'est pourquoi de nombreux chercheurs et concepteurs industriels se sont penchés sur de nouvelles méthodes de réduction de la consommation énergétique des circuits numériques. La logique adiabatique est un style de conception prometteur qui peut réduire la dissipation d'énergie dynamique. La logique adiabatique est différente de la logique conventionnelle en deux principaux points : 1) l’alimentation d’une porte logique adiabatique est un signal à 4 phases, et 2) l’énergie stockée dans la porte est récupérée. Afin de respecter ces principes, la logique adiabatique nécessite une alimentation spéciale. Étant donné que l’objectif d’une telle alimentation est d’agir comme une horloge, elle est appelée alimentation-horloge. L'objectif de cette thèse est de concevoir et d'optimiser une alimentation-horloge ainsi que son réseau de distribution. Cette thèse a été financée par l'Agence Nationale pour la Recherche, ANR, avec le projet ADIANEMS2 (numéro de subvention : ANR-15-CE24-0013)<br>Power density has become the primary concern when a digital core is designed. As in any embedded systems, each new digital core generation has more applications than the previous one and ultimately demands more power density. This is why many researchers and industrial designers have been looking into novel methods for reducing power consumption of digital circuit. Adiabatic logic is a promising design style, which can reduce the dynamic energy dissipation. Adiabatic logic is different than conventional logic in two main points: 1) adiabatic gate are charged with a 4-phase power signal, and 2) the energy, which is stored in the gate, is recovered. In order to fulfill these principles, the adiabatic logic needs a special power supply. As the purpose of such supply is to act as a clock also, it is referred as power-clock supply. The aim of this thesis is to design and optimize a power-clock supply and its delivery network. This thesis has been funded by the French National Research Agency, ANR, with the project ADIANEMS2 (Grant number: ANR-15-CE24-0013)

CMOS based computing is reaching its limits. To take computation beyond Moores law (the number of transistors and hence processing power on a chip doubles every 18 months to 3 years) requires research explorations in (i) new materials, devices, and processes, (ii) new architectures and algorithms, (iii) new paradigm of logic bit representation. The focus is on fundamental new ways to compute under the umbrella of rebooting computing such as spintronics, quantum computing, adiabatic and reversible computing. Therefore, this thesis highlights explicitly Quantum computing and Adiabatic logic, two new computing paradigms that come under the umbrella of rebooting computing. Quantum computing is investigated for its promising application in high-performance computing. The first contribution of this thesis is the design of two resource-efficient designs for quantum integer division. The first design is based on non-restoring division algorithm and the second one is based on restoring division algorithm. Both the designs are compared and shown to be superior to the existing work in terms of T-count and T-depth. The proliferation of IoT devices which work on low-power also has drawn interests to the rebooting computing. Hence, the second contribution of this thesis is proving that Adiabatic Logic is a promising candidate for implementation in IoT devices. The adiabatic logic family called Symmetric Pass Gate Adiabatic Logic (SPGAL) is implemented in PRESENT-80 lightweight algorithm. Adiabatic Logic is extended to emerging transistor devices.

I metodi di calcolo tradizionali per le teorie di gauge su reticolo risultano problematici in regioni di diagrammi di fase a grandi valori del potenziale chimico o quando sono utilizzate per riprodurre la dinamica in tempo reale di un modello. Tali problemi possono essere evitati da simulazioni quantistiche delle teorie di gauge su reticolo, le quali stanno diventando sempre più riproducibili sperimentalmente, grazie ai recenti progressi tecnologici. In questa tesi formuliamo una versione delle teorie di Yang-Mills su reticolo appropriata per risolvere il problema della dimensione infinita dello spazio di Hilbert associato ai bosoni di gauge. Questa formulazione è adatta per essere riprodotta in un simulatore quantistico e ne implementiamo una completa simulazione su un computer quantistico digitale, sfruttando il framework Qiskit. In questa simulazione misuriamo le energie del ground state e i valori di aspettazione di alcuni Wilson loop al variare dell'accoppiamento della teoria, per studiarne le fasi e valutare la prestazione dei metodi usati.

The widespread adoption of photonic circuits requires the economics of volume manufacturing offered by integration technology. A Complementary Metal-Oxide Semiconductor compatible silicon material platform is particularly attractive because it leverages the huge investment that has been made in silicon electronics and its high index contrast enables tight confinement of light which decreases component footprint and energy consumption. Nevertheless, there remain challenges to the development of photonic integrated circuits. Although the density of integration is advancing steady and the integration of the principal components – waveguides, optical sources and amplifiers, modulators, and photodetectors – have all been demonstrated, the integration density is low and the device library far from complete. The integration density is low primarily because of the difficulty of confining light in structures small compared to the wavelength which measured in micrometers. The device library is incomplete because of the immaturity of hybridisation on silicon of other materials required by active devices such as III-V semiconductor alloys and ferroelectric oxides and the difficulty of controlling the coupling of light between disparate material platforms. Metamaterials are nanocomposite materials which have optical properties not readily found in Nature that are defined as much by their geometry as their constituent materials. This offers the prospect of the engineering of materials to achieve integrated components with enhanced functionality. Metamaterials are a class of photonic crystals includes subwavelength grating waveguides, which have already provided breakthroughs in component performance yet require a simpler fabrication process compatible with current minimum feature size limitations. The research reported in this PhD thesis advances our understanding of the structure-property relations of key planar light circuit components and the metamaterial engineering of these properties. The analysis and simulation of components featuring structures that are only just subwavelength is complicated and consumes large computer resources especially when a three dimensional analysis of components structured over a scale larger than the wavelength is desired. This obstructs the iterative design-simulate cycle. An abstraction is required that summarises the properties of the metamaterial pertinent to the larger scale while neglecting the microscopic detail. That abstraction is known as homogenisation. It is possible to extend homogenisation from the long-wavelength limit up to the Bragg resonance (band edge). It is found that a metamaterial waveguide is accurately modeled as a continuous medium waveguide provided proper account is taken of the emergent properties of the homogenised metamaterial. A homogenised subwavelength grating waveguide structure behaves as a strongly anisotropic and spatially dispersive material with a c-axis normal to the layers of a one dimensional multi-layer structure (Kronig-Penney) or along the axis of uniformity for a two dimensional photonic crystal in three dimensional structure. Issues with boundary effects in the near Bragg resonance subwavelength are avoided either by ensuring the averaging is over an extensive path parallel to boundary or the sharp boundary is removed by graded structures. A procedure is described that enables the local homogenised index of a graded structure to be determined. These finding are confirmed by simulations and experiments on test circuits composed of Mach-Zehnder interferometers and individual components composed of regular nanostructured waveguide segments with different lengths and widths; and graded adiabatic waveguide tapers. The test chip included Lüneburg micro-lenses, which have application to Fourier optics on a chip. The measured loss of each lens is 0.72 dB. Photonic integrated circuits featuring a network of waveguides, modulators and couplers are important to applications in RF photonics, optical communications and quantum optics. Modal phase error is one of the significant limitations to the scaling of multimode interference coupler port dimension. Multimode interference couplers rely on the Talbot effect and offer the best in-class performance. Anisotropy helps reduce the Talbot length but temporal and spatial dispersion is necessary to control the modal phase error and wavelength dependence of the Talbot length. The Talbot effect in a Kronig-Penny metamaterial is analysed. It is shown that the metamaterial may be engineered to provide a close approximation to the parabolic dispersion relation required by the Talbot effect for perfect imaging. These findings are then applied to the multimode region and access waveguide tapers of a multi-slotted waveguide multimode interference coupler with slots either in the transverse direction or longitudinal direction. A novel polarisation beam splitter exploiting the anisotropy provided by a longitudinally slotted structure is demonstrated by simulation. The thesis describes the design, verification by simulation and layout of a photonic integrated circuit containing metamaterial waveguide test structures. The test and measurement of the fabricated chip and the analysis of the data is described in detail. The experimental results show good agreement with the theory, with the expected errors due to fabrication process limitations. From the Scanning Electron Microscope images and the measurements, it is clear that at the boundary of the minimum feature size limit, the error increases but still the devices can function.

碩士<br>國立交通大學<br>電子研究所<br>83<br>Adiabatic Switching and Charge Recycling are two new techniques to reduce power consumption: with the Adiabatic Switching technique, heat dissipation on resistive device channels caused by dynamic charging and discharging is reduced if energy transfer period T >> RC, where RC is the time constant of the circuit. Exploiting the Charge Recycling technique, loss of stored energy in capacitive loads can be recovered for reuse in subsequent cycles. In this paper, we propose a new logic family - Pulsed Power Supply Cross-Coupled Differential Logic (PPS- CCDL), which integrates the adiabatic differential logic gate and a latch. PPS-CCDL can be shown througth derivations and simulations to dissipate less power than the previously proposed PPS-CMOS approach, by eliminating the PMOS trees and the unnecessary signal glitches and transitions in PPS-CMOS. A higher power saving of the overall system is anticipated since PPS-CCDL presents a smaller and data-independent capacitive loads to the pulsed power supply. We implemented an 8-bit pipelined adder with a 0.8um standard CMOS technology, which is under testing. Another application chip of PPS/static 23-bit correlator with 8-bit I/O was submitted to CIC for fabrication.

Yeung Wing-ki.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.<br>Includes bibliographical references (leaves 64-65).<br>Abstracts in English and Chinese.<br>Abstracts --- p.i<br>摘要 --- p.iii<br>Acknowledgements --- p.iv<br>Contents --- p.v<br>List of Figures --- p.vii<br>Chapter 1. --- Introduction --- p.1<br>Chapter 1.1. --- Low ower Design --- p.1<br>Chapter 1.2. --- ower Consumtion in Conventional CMOS Logic --- p.2<br>Chapter 1.3. --- Adiabatic Switching --- p.7<br>Chapter 1.3.1. --- Varying Suly Voltage --- p.7<br>Chapter 1.3.2. --- Charge Recovery --- p.12<br>Chapter 2. --- Adiabatic Quasi-static CMOS Logic --- p.13<br>Chapter 2.1. --- AqsCMOS Logic Building Block --- p.14<br>Chapter 2.2. --- AqsCMOS inverter --- p.17<br>Chapter 2.3. --- ower Reduced in Sinusoidal Suly --- p.18<br>Chapter 2.4. --- Clocking Scheme --- p.21<br>Chapter 3. --- Contactless Smart Card --- p.23<br>Chapter 3.1. --- Architecture --- p.23<br>Chapter 3.2. --- Standardization --- p.26<br>Chapter 3.3. --- Universal Asynchronous Receiver and Transmitter (UART) --- p.30<br>Chapter 4. --- Clock Recovery --- p.35<br>Chapter 4.1 --- Adiabatic Ring Oscillator --- p.35<br>Chapter 4.2. --- Secial Frequencies of AqsCMOS Ring Oscillator --- p.39<br>Chapter 4.3. --- ower Extraction --- p.41<br>Chapter 5. --- Evaluations and Measurement Results --- p.43<br>Chapter 5.1. --- Outut Transitions --- p.43<br>Chapter 5.2. --- Ring Oscillator --- p.44<br>Chapter 5.3. --- Synchronization --- p.47<br>Chapter 5.4. --- ower Consumtion --- p.49<br>Chapter 6. --- Conclusion --- p.53<br>Aendix --- p.54<br>Glossary --- p.62<br>Reference --- p.64

by Kelvin Cheung Ka Wai.<br>Thesis submitted in: June 1997.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.<br>Includes bibliographical references.<br>ACKNOWLEDGEMENTS --- p.i<br>ABSTRACT --- p.ii<br>TABLE OF CONTENTS --- p.iii<br>LIST OF FIGURES --- p.vi<br>TIST OF TABLES --- p.viii<br>Chapter 1. --- INTRODUCTION --- p.1-1<br>Chapter 1.1 --- Introduction --- p.1-1<br>Chapter 1.2 --- Objective --- p.1-1<br>Chapter 1.3 --- Static CMOS Logic and Dynamic Logic --- p.1-1<br>Chapter 1.3.1 --- static CMOS logic circuit --- p.1-1<br>Chapter 1.3.2 --- Dynamic logic --- p.1-2<br>Chapter 1.4 --- Power Consumption in Static CMOS Integrated Circuit --- p.1-4<br>Chapter 1.4.1 --- Static power dissipation --- p.1 -4<br>Chapter 1.4.2 --- Dynamic power dissipation --- p.1 -6<br>Chapter 1.4.2.1 --- Short circuit current --- p.1 -6<br>Chapter 1.4.2.2 --- Charging and discharging of load capacitances --- p.1-6<br>Chapter 1.4.2.3 --- Total power consumption --- p.1-8<br>Chapter 1.5 --- Adiabatic Logic --- p.1-8<br>Chapter 1.5.1 --- Low power electronics --- p.1-8<br>Chapter 1.5.2 --- History of adiabatic logic --- p.1 -9<br>Chapter 1.6 --- Resources --- p.1-10<br>Chapter 1.6.1 --- Computing instrument --- p.1-10<br>Chapter 1.6.2 --- CAD tools --- p.1-10<br>Chapter 1.6.3 --- Fabrication --- p.1-11<br>Chapter 1.7 --- Organisation of the Thesis --- p.1-11<br>Chapter 2. --- BACKGROUND THEORIES --- p.2-1<br>Chapter 2.1 --- Limit of energy dissipation --- p.2-1<br>Chapter 2.2 --- Reversible Electronics --- p.2-1<br>Chapter 2.2.1 --- Reversibility --- p.2-1<br>Chapter 2.2.2 --- Adiabatic Switching --- p.2-3<br>Chapter 2.2.2.1 --- Conventional Charging --- p.2-3<br>Chapter 2.2.2.2 --- Adiabatic Charging --- p.2-4<br>Chapter 2.2.3 --- Reversible devices --- p.2-5<br>Chapter 2.3 --- Compatibility to CMOS Logic --- p.2-6<br>Chapter 3. --- ADIABATIC QUASI-STATIC CMOS --- p.3-1<br>Chapter 3.1 --- Swinging between 0 and 1 by Harmonic Motion --- p.3-1<br>Chapter 3.1.1 --- Starting from a simple pendulum --- p.3-1<br>Chapter 3.1.2 --- Inductor-capacitor oscillator --- p.3-2<br>Chapter 3.2 --- Redistribution of Charge --- p.3-3<br>Chapter 3.3 --- Adiabatic Quasi-static Logic --- p.3-4<br>Chapter 3.3.1 --- False reversible inverter --- p.3-4<br>Chapter 3.3.2 --- Adiabatic inverter --- p.3-5<br>Chapter 3.3.3 --- Effective capacitance --- p.3-7<br>Chapter 3.3.4 --- Logic alignment --- p.3-8<br>Chapter 3.3.5 --- Cascading the adiabatic inverters --- p.3-10<br>Chapter 3.3.5.1 --- Compensated cascading --- p.3-10<br>Chapter 3.3.5.2 --- Balanced cascading --- p.3-11<br>Chapter 3.4 --- Frequency Control --- p.3-12<br>Chapter 3.5 --- Compatibility of AqsCMOS with Static CMOS Logic --- p.3-13<br>Chapter 4. --- ADIABATIC QUASI-STATIC CMOS INVERTERS --- p.4-1<br>Chapter 4.1 --- Design --- p.4-1<br>Chapter 4.1.1 --- Realisation of current direction control device --- p.4-1<br>Chapter 4.1.2 --- Implementation of AqsCMOS inverter by current direction control device --- p.4-2<br>Chapter 4.1.3 --- Layout --- p.4-3<br>Chapter 4.1.3.1 --- Horizontal Transistor Diode --- p.4-3<br>Chapter 4.1.3.2 --- Transistor pair --- p.4-9<br>Chapter 4.2 --- Capacitance Calculation --- p.4-9<br>Chapter 4.2.1 --- Non-switching device --- p.4-10<br>Chapter 4.2.2 --- Switching device --- p.4-11<br>Chapter 4.3 --- Clocking Scheme --- p.4-13<br>Chapter 4.4 --- Energy Loss of AqsCMOS inverter --- p.4-14<br>Chapter 5. --- ADIABATIC CLOCKS GENERATOR --- p.5-1<br>Chapter 5.1 --- Introduction --- p.5-1<br>Chapter 5.2 --- Full Adiabatic Clocks Generator --- p.5-1<br>Chapter 5.2.1 --- Sizes of the transistors used --- p.5-2<br>Chapter 5.2.2 --- Energy consumption of full adiabatic clocks generator --- p.5-3<br>Chapter 5.3 --- Half Adiabatic Clocks Generator --- p.5-4<br>Chapter 5.3.1 --- Transistor sizing --- p.5-5<br>Chapter 5.3.2 --- Energy consumption of the half adiabatic clock generator --- p.5-5<br>Chapter 5.3.3 --- Weakness of the half adiabatic clocks generator --- p.5-6<br>Chapter 5.4 --- Automatic Adiabatic Clocks Generator --- p.5-6<br>Chapter 5.4.1 --- Operation of automatic adiabatic clocks generator --- p.5-7<br>Chapter 5.4.2 --- Energy consumption of automatic adiabatic clocks generator --- p.5-9<br>Chapter 6. --- EVALUATION --- p.6-1<br>Chapter 6.1 --- Introduction --- p.6-1<br>Chapter 6.2 --- Simulation Results --- p.6-1<br>Chapter 6.2.1 --- Adiabatic clocks generators --- p.6-1<br>Chapter 6.2.2 --- Adiabatic quasi-static CMOS inverters --- p.6-4<br>Chapter 6.2.2.1 --- Functional evaluation --- p.6-4<br>Chapter 6.2.2.2 --- Performance evaluation --- p.6-6<br>Chapter 6.3 --- Test Circuit - Pendulum --- p.6-8<br>Chapter 6.3.1 --- Layout --- p.6-8<br>Chapter 6.3.2 --- Test circuit of pendulum --- p.6-10<br>Chapter 6.3.3 --- Module 1 - Full adiabatic clocks generator (fclk) --- p.6-11<br>Chapter 6.3.4 --- Module 2 - Half adiabatic clocks generator (hclk) --- p.6-13<br>Chapter 6.3.5 --- Module 3 to 5- Adiabatic inverter chains --- p.6-14<br>Chapter 6.3.5.1 --- DC characteristics --- p.6-14<br>Chapter 6.3.5.2 --- AC characteristics --- p.6-14<br>Chapter 6.3.6 --- Power dissipation --- p.6-17<br>Chapter 7 --- CONCLUSIONS --- p.7-1<br>Chapter 7.1 --- Introduction --- p.7-1<br>Chapter 7.2 --- Design --- p.7-1<br>Chapter 7.2.1 --- Adiabatic quasi-static CMOS logic --- p.7-1<br>Chapter 7.2.2 --- Adiabatic quasi-static CMOS inverters --- p.7-2<br>Chapter 7.2.3 --- Adiabatic clocks generator --- p.7-2<br>Chapter 7.3 --- Function --- p.7-3<br>Chapter 7.4 --- Power Dissipation --- p.7-3<br>Chapter 7.5 --- Discussion --- p.7-3<br>Chapter 7.6 --- Further Development --- p.7-3<br>Chapter 7.7 --- Conclusion --- p.7-4<br>Chapter 8. --- REFERENCES --- p.8-1<br>APPENDIX I TABLE OF PTN LAYOUT PENDULUM --- p.I-1<br>APPENDIX II PHOTOGRAPHS OF PENDULUM --- p.II-1

碩士<br>國立彰化師範大學<br>電子工程學系<br>97<br>This thesis proposes a novel low-power logic circuit, called handshaking quasi-adiabatic logic (HQAL), which combines the advantages of asynchronous circuits and adiabatic logics. The HQAL logics adopt dual-rail encoding, and employ handshaking to transfer data between the adjacent modules. Hence, HQAL has the advantages of asynchronous circuits: no clock skew problem, no power dissipation due to the clock tree, and no dynamic power dissipation when there are no input data. The power line of the HQAL logic gates is controlled by the handshake control chain (HCC). A HQAL logic gate is not supplied with power when it has no input data. Only when a HQAL gate has acquired its input data, it can gain the power and then operate in a way similar to the adiabatic logic. Hence, the HQAL logic can achieve low power dissipation. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits. Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the CMOS implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz. Also, the HQAL implementation can achieve up to 95.6% reduction in static power dissipation as the adiabatic logic blocks in HQAL are not powered and have negligible leakage power dissipation when they have no input.

Mok, King Keung.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.<br>Includes bibliographical references (leaves 77-79).<br>Abstracts in English and Chinese.<br>Abstract --- p.1<br>Contents --- p.5<br>List of Figures --- p.7<br>List of Tables --- p.10<br>Acknowledgments --- p.11<br>Chapter 1. --- Introduction --- p.12<br>Chapter 1.1. --- Low Power Design --- p.12<br>Chapter 1.2. --- Power Consumption in Conventional CMOS Logic --- p.13<br>Chapter 1.2.1. --- Dynamic Power --- p.13<br>Chapter 1.2.2. --- Short-Circuit Power --- p.15<br>Chapter 1.2.3. --- Leakage Power --- p.17<br>Chapter 1.2.4. --- Static Power --- p.19<br>Chapter 1.3. --- Smart Card / RFID --- p.21<br>Chapter 1.3.1. --- Applications --- p.21<br>Chapter 1.3.2. --- Operating Principle --- p.22<br>Chapter 1.3.3. --- Conventional Architecture --- p.23<br>Chapter 2. --- Adiabatic Logic --- p.25<br>Chapter 2.1. --- Adiabatic Switching --- p.25<br>Chapter 2.2. --- Energy Recovery --- p.27<br>Chapter 2.3. --- Adiabatic Quasi-Static CMOS Logic --- p.29<br>Chapter 2.3.1. --- Logic Structure --- p.29<br>Chapter 2.3.2. --- Clocking Scheme --- p.31<br>Chapter 2.3.3. --- Flip-flop --- p.33<br>Chapter 2.3.4. --- Layout Techniques --- p.38<br>Chapter 3. --- Adiabatic RFID --- p.41<br>Chapter 3.1. --- System Architecture --- p.41<br>Chapter 3.2. --- Circuit Design --- p.42<br>Chapter 3.2.1. --- Voltage Limiter --- p.43<br>Chapter 3.2.2. --- Substrate Bias Generation Circuit --- p.45<br>Chapter 3.2.3. --- Ring Oscillator --- p.46<br>Chapter 3.2.4. --- ROM and Control Logic --- p.48<br>Chapter 3.2.5. --- Load Modulator --- p.52<br>Chapter 3.2.6. --- Experimental Results --- p.53<br>Chapter 4. --- Adiabatic Smart Card --- p.59<br>Chapter 4.1. --- System Architecture --- p.59<br>Chapter 4.2. --- Circuit Design --- p.61<br>Chapter 4.2.1. --- ASK Demodulator --- p.61<br>Chapter 4.2.2. --- Clock Recovery Circuit --- p.63<br>Chapter 4.3. --- Experimental Results --- p.67<br>Chapter 5. --- Conclusion --- p.74<br>Chapter 6. --- Future Works --- p.76<br>Reference --- p.77<br>Appendix --- p.80

Mak Wing-sum.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.<br>Includes bibliographical references (leaf [68]).<br>Abstracts in English and Chinese.<br>List of Figures --- p.I<br>List of Tables --- p.III<br>ACKNOWLEDGMENTS<br>ABSTRACT<br>Chapter Chapter I --- Introduction<br>Chapter 1.1 --- Introduction - Low Power --- p.I-1<br>Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1<br>Chapter 1.2.1 --- Static Power Dissipation --- p.I-2<br>Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5<br>Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8<br>Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10<br>Chapter 1.4 --- Objective of the Project --- p.I-10<br>Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic<br>Chapter 2.1 --- Low Power Design --- p.II-12<br>Chapter 2.2 --- Adiabatic Switching --- p.II-12<br>Chapter 2.3 --- Adiabatic Logic --- p.II-14<br>Chapter 2.4 --- History of Adiabatic Logic --- p.II-17<br>Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter<br>Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18<br>Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20<br>Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22<br>Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23<br>Chapter Chapter IV --- Power Clock Generator<br>Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24<br>Chapter 4.2 --- Power Clock Generator<br>Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV<br>Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27<br>Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier<br>Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32<br>Chapter 5.2 --- Structure of Multiplier --- p.V-34<br>Chapter Chapter VI --- Simulations<br>Chapter 6.1 --- AqsCMOS Inverter<br>Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38<br>Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39<br>Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI<br>Chapter 6.2 --- Power Clock Generator --- p.VI -42<br>Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45<br>Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46<br>Chapter ChapterVII --- evaluations<br>Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51<br>Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus<br>Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54<br>Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55<br>Chapter 7.2.3 --- Input Current Measurement --- p.VII -58<br>Chapter 7.3 --- Power Measurement --- p.VII -63<br>Chapter Chapter VIII --- Conclusions and Fiirthfr Developments<br>Chapter 8.1 --- Conclusions --- p.VIII -65<br>Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65<br>Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65<br>Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66<br>Chapter 8.2 --- Further Development --- p.VIII -66<br>Appendix I micro-photography of aqscmos multiplier<br>Appendix II micro-Photography of CMOS multiplier<br>Appendix III micro-photography of AqsCMOS inverter chain testing modules<br>Appendix IV power - meter simulation approach<br>Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers<br>Reference

So Pui Tak.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.<br>Includes bibliographical references.<br>Abstracts in English and Chinese.<br>Abstract --- p.ii<br>Acknowledgement --- p.v<br>Table of Contents --- p.vi<br>List of Figures --- p.ix<br>List of Tables --- p.xii<br>Chapter Chapter 1 --- Introduction --- p.11<br>Chapter 1.1 --- Overview --- p.1-1<br>Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1<br>Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6<br>Chapter 1.4 --- Objectives --- p.1-7<br>Chapter 1.5 --- Thesis Outline --- p.1-8<br>Chapter Chapter 2 --- Background Theory --- p.2-1<br>Chapter 2.1 --- Introduction --- p.2-1<br>Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1<br>Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3<br>Chapter 2.4 --- Asynchro nous Circuits --- p.2-7<br>Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1<br>Chapter 3.1 --- Introduction --- p.3-1<br>Chapter 3.2 --- Architecture --- p.3-2<br>Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4<br>Chapter 3.4 --- Circuit Evaluation --- p.3-7<br>Chapter 3.5 --- Simulation Results --- p.3-8<br>Chapter 3.4 --- Experimental Results --- p.3-9<br>Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1<br>Chapter 4.1 --- Introduction --- p.4-1<br>Chapter 4.2 --- Architecture --- p.4-1<br>Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2<br>Chapter 4.2.2 --- Delay Block Design --- p.4-4<br>Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1<br>Chapter 5.1 --- Introduction --- p.5-1<br>Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1<br>Chapter 5.3 --- Oscillator Block Design --- p.5-3<br>Chapter 5.4 --- Multiplier Architecture --- p.5-6<br>Chapter Chapter 6 --- Layout Consideration --- p.6-1<br>Chapter 6.1 --- Introduction --- p.6-1<br>Chapter 6.2 --- Floorplanning --- p.6-1<br>Chapter 6.3 --- Routing Channels --- p.6-2<br>Chapter 6.3 --- Power Supply --- p.6-4<br>Chapter 6.4 --- Input Protection Circuitry --- p.6-5<br>Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7<br>Chapter Chapter 7 --- Simulation Results --- p.7-1<br>Chapter 7.1 --- Introduction --- p.7-1<br>Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1<br>Chapter 7.3 --- Power Consumption --- p.7-6<br>Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6<br>Chapter 7.3.2 --- AAT Multiplier --- p.7-7<br>Chapter 7.3.3 --- Power Comparison --- p.7-8<br>Chapter Chapter 8 --- Measurement Results --- p.8-1<br>Chapter 8.1 --- Introduction --- p.8-1<br>Chapter 8.2 --- Experimental Setup --- p.8-2<br>Chapter 8.3 --- Measurement Results --- p.8-6<br>Chapter Chapter 9 --- Conclusion --- p.9-1<br>Chapter 9.1 --- Contributions --- p.9-1<br>Chapter Chapter 10 --- Bibliography --- p.10-1<br>Appendix I Building Blocks --- p.1<br>Appendix II Simulated Waveform --- p.7<br>Appendix III Measured Waveform --- p.8<br>Appendix IV Pin List --- p.9

碩士<br>國立臺灣大學<br>電機工程學研究所<br>90<br>This thesis reports a circuit technique to improve the performance of true single-phase adiabatic circuitry. In chapter 2, the principles of adiabatic and non-adiabatic charging/discharging is introduced. Several conventional adiabatic circuit families are reviewed and analyzed with discussion about their advantages and disadvantages. In chapter 3, the first ever true single-phase adiabatic circuit family is reviewed and analyzed. Improved true single-phase adiabatic circuit is proposed by utilizing bootstrapped switch technique. By HSPICE simulation, it is proven that the proposed circuit has better performance in noise margin and signal integrity than the original one.

碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>This thesis reports a 1.5V high-speed 16-bit/8-bit divider circuit usingthe quotient-select architecture and true-single- phase bootstrapped dynamic circuit techniques [2.13],[2.14]. Based on a 0.8um CMOS technology, thespeed performance of this 16-bit/8-bit divider circuit is improved by 45%as compared to the divider using the non-restoring iterative architecture andthe domino dynamic logic circuits without the bootstrapped technique. Thisdivider circuit, which provide an even higher speed advantage--- a 55%improvement at a supply voltage of 1V, is suitable for low-voltage CMOS VLSIsystems. This thesis also reports a 1.5V full-swing energy efficient logic circuit suitable for next-generation low-power VLSI applications using a low supply voltage. Based on the analysis, at an operating frequency of 25MHz and at aclock maximum voltage 1.5V, the power consumption of the EEL circuit is 54% ofthat of ECRL circuit and 36% of that of the static circuit.

碩士<br>國立臺灣大學<br>電子工程學研究所<br>92<br>This thesis reports a new adiabatic circuit technology which uses bootstrapped transistors, pass-transistors and compensated transistors to realize a single power clock logic and driver circuit. In chapter 1, the trend of low voltage design, and its good and bad in recent years will be described In chapter 2, the principles of adiabatic technology will be described. Then several conventional adiabatic and bootstrapped driver circuit families are reviewed, and analyzed with discussion about the advantages and disadvantages. In chapter 3, new adiabatic logic and driver circuits which use bootstrapped transistors and pass-transistors technology are proposed. And by HSPICE simulation, it is proved that in power consumption, noise margin, and the number of clocks have been improved to compare with conventional circuits.