Relevant bibliographies by topics / ALL Digital circuit

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'ALL Digital circuit'

Author: Grafiati
Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "ALL Digital circuit"

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Manjula, Jayamma. "Analysis of Carbon Nanotube based Ternary Multiplexer." Recent Trends in Control and Converter 6, no. 1 (2023): 1–6. https://doi.org/10.5281/zenodo.7638462.

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<em>In this paper, a new ternary multiplexer has been analyzed which are fundamental components of all ternary digital logic circuits. Multiplexer is the most used digital component is many digital circuits. </em><em>A multiple-valued logic (MVL) circuit uses less energy and has more valued logic in each digit than a binary logic circuit. As a result, a ternary multiplier (TMUL) for embedded circuits with low power consumption is proposed in this paper. The cascading proposed ternary multiplexer is all that is used in the CNTFET-based TMUL circuit to reduce the number of transistors and boost
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Cherubini, G., and S. Pupolin. "Performance Analysis of an All-Digital Acquisition Circuit." IEEE Transactions on Communications 33, no. 8 (1985): 862–68. http://dx.doi.org/10.1109/tcom.1985.1096394.

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M.Indu*, S.HasmashruthiA.Nandhini, and N.Megala. "GLITCH-FREE NAND-BASED DIGITALLY CONTROLLED DELAY LINES." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 4 (2016): 117–22. https://doi.org/10.5281/zenodo.48842.

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Glitch is an undesired transition that occurs before the signal settles to its intended value. It is an electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit. The existing Glitch Free NAND-based Digitally Controlled Delay Lines (DCDL) presented some glitching problem which limited their applications. To overcome this limitation new NAND-based DCDL is proposed. This will maintain the same resolution and minimum delay of existing NAND-based DCDL. The proposed DCDL will be working on the basis of two control signals which are u
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Mokhtarnia, Hossein, Shahram Etemadi Borujeni, and Mohammad Saeed Ehsani. "Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950240. http://dx.doi.org/10.1142/s0218126619502402.

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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the propo
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Pan, Zhong Liang, and Ling Chen. "A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams." Applied Mechanics and Materials 29-32 (August 2010): 1040–45. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1040.

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The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The
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Hossain, M., M. P. Singh, and J. K. Rakshit. "Modelling of one-bit Arithmetic Logic Circuit using silicon micro-ring resonator." Journal of Physics: Conference Series 2335, no. 1 (2022): 012003. http://dx.doi.org/10.1088/1742-6596/2335/1/012003.

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Abstract All-optical technology overcomes the problems that arise in traditional digital circuits such as speed limitation, energy consumption and size. In this manuscript, we have implemented a one-bit arithmetic logic circuit employing all-optical silicon micro-ring resonator that utilizes the advantages over other all-optical techniques. The Arithmetic logic circuit is the core component of ultra-fast combinational circuits. The proposed arithmetic logic circuit is validated through MATLAB at about 260 Gbps. Performance of our design has been investigated by numerical simulation. The critic
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Aryanpur, P., and A. A. Prihod'ko. "Using programs of the MicroCap family to study and designing digital components and circuits." Electronics and Communications 16, no. 5 (2012): 48–54. http://dx.doi.org/10.20535/2312-1807.2011.16.5.247740.

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Functional possibilities of the programs of family MicroCap are considered for a study and design of digital components, circuits and systems in courses for digital to circuit technique. General principles design is expounded for all digital objects and features of modeling digital objects of combinative type
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Fischette, Dennis M., Alvin L. S. Loke, Richard J. DeSantis, and Gerry R. Talbot. "An Embedded All-Digital Circuit to Measure PLL Response." IEEE Journal of Solid-State Circuits 45, no. 8 (2010): 1492–503. http://dx.doi.org/10.1109/jssc.2010.2048143.

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Parandin, Fariborz, Saeed Olyaee, Reza Kamarian, and Mohamadreza Jomour. "Design and Simulation of Linear All-Optical Comparator Based on Square-Lattice Photonic Crystals." Photonics 9, no. 7 (2022): 459. http://dx.doi.org/10.3390/photonics9070459.

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An optical comparator is an important logic circuit used in digital designs. Photonic crystals are among the platforms for implementing different kinds of gates and logic circuits, and they are structures with alternating refractive indices. In this paper, an optical comparator is designed and simulated based on a square lattice photonic crystal. In the design of this comparator, a small-sized structure is used. The simulation results show that in the proposed comparator, there is a high difference between logical values “0” and “1”, which are defined based on the optical power level. Due to t
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Seyedi, Saeid, Nima Jafari Navimipour, and Akira Otsuki. "A New Nano-Scale and Energy-Optimized Reversible Digital Circuit Based on Quantum Technology." Electronics 11, no. 23 (2022): 4038. http://dx.doi.org/10.3390/electronics11234038.

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A nano-scale quantum-dot cellular automaton (QCA) is one of the most promising replacements for CMOS technology. Despite the potential advantages of this technology, QCA circuits are frequently plagued by numerous forms of manufacturing faults (such as a missing cell, extra cell, displacement cell, and rotated cell), making them prone to failure. As a result, in QCA technology, the design of reversible circuits has received much attention. Reversible circuits are resistant to many kinds of faults due to their inherent properties and have the possibility of data reversibility, which is importan
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Dissertations / Theses on the topic "ALL Digital circuit"

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Kim, Kwan-Woo. "A fully-integrated all-digital outphasing transmitter for wireless communications." Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37263.

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The objective of the proposed research is to present a new all-digital outphasing transmitter IC, a comprehensive explanation of its operation, and its performance characterization. The all-digital transmitter chip leverages flexible digital phase modulators (DPMs) to adaptively compensate for amplifier mismatches. As the DPM uses a digital input to directly modulate the RF phase of each path, the phase control becomes very simple and accurate for power amplifier (PA) gain/phase mismatch compensation. Furthermore, this digital phase modulation scheme also facilitates minimizing the distortion
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Mello, Israel Sperotto de. "All-MOSFET M-2M digital-to-analog converter for operation with very low supply voltage." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/169086.

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Desde os anos 80 a evolução dos processos de fabricação de circuitos integrados MOS tem buscado a redução da tensão de alimentação, como forma de se reduzir o consumo de energia dos circuitos. Partiu-se dos antigos 5 V, padrão estabelecido pela lógica TTL nos anos 70, até os circuitos modernos que operam com alimentação pouco abaixo de 1 V. Entretanto, desde os primeiros anos da década de 2000, a tensão de alimentação está estabilizada neste patamar, devido a limitações tecnológicas que tem se mostrado difíceis de serem transpostas. Tal desafio tem sido estudado por grupos de pesquisa ao redor
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Paci, Giacomo <1979&gt. "Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2009. http://amsdottorato.unibo.it/1497/1/Paci_Giacomo_Tesi.pdf.

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The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the th
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Paci, Giacomo <1979&gt. "Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2009. http://amsdottorato.unibo.it/1497/.

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The digital electronic market development is founded on the continuous reduction of the transistors size, to reduce area, power, cost and increase the computational performance of integrated circuits. This trend, known as technology scaling, is approaching the nanometer size. The lithographic process in the manufacturing stage is increasing its uncertainty with the scaling down of the transistors size, resulting in a larger parameter variation in future technology generations. Furthermore, the exponential relationship between the leakage current and the threshold voltage, is limiting the th
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Elmore, Joel D. "Design of an All-In-One Embedded Flight Control System." VCU Scholars Compass, 2015. http://scholarscompass.vcu.edu/etd/3981.

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This thesis describes an all-in-one flight control system (FCS) that was designed for unmanned aerial vehicles (UAVs). The project focuses on the embedded hardware aspect of a stand-alone system with low-cost and reliability in mind.
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Tambara, Lucas Antunes. "Analyzing the Impact of Radiation-induced Failures in All Programmable System-on-Chip Devices." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/164461.

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O recente avanço da indústria de semicondutores tem possibilitado a integração de componentes complexos e arquiteturas de sistemas dentro de um único chip de silício. Atualmente, FPGAs do estado da arte incluem, não apenas a matriz de lógica programável, mas também outros blocos de hardware, como processadores de propósito geral, blocos de processamento dedicado, interfaces para vários periféricos, estruturas de barramento internas ao chip, e blocos analógicos. Estes novos dispositivos são comumente chamados de Sistemasem-Chip Totalmente Programáveis (APSoCs). Uma das maiores preocupações acer
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Palanisamy, Karthikeyan. "High Level Preprocessor of a VHDL-based Design System." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4776.

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This thesis presents the work done on a design automation system in which high-level synthesis is integrated with logic synthesis. DIADESfa design automation system developed at PSU, starts the synthesis process from a language called ADL. The major part of this thesis deals with transforming the ADL -based DIADES system into a VHDL -based DIADES system. In this thesis I have upgraded and modified the existing DIADES system so that it becomes a preprocessor to a comprehensive VHDL -based design system from Mentor Graphics. The high-level synthesis in the DIADES system includes two stages: data
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LIAN, ZHAO-MIN, and 連照銘. "All digital ethernet local area network circuit design." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/35057587479729477567.

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Chu, Wei-Jung, and 朱薇蓉. "Design of All-Digital Built-In Self-Test Circuit for All-Digital Phase-Locked Loops." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/22397462569087930795.

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碩士<br>國立中正大學<br>資訊工程研究所<br>99<br>In this thesis, we propose a design of an all-digital built-in self-test circuit for all-digital phase-locked loops (ADPLLs). Testing circuits are embedded on chip to test the circuit instead of using external instruments. In this way, it not only can save the cost of external instruments, but also can decrease error of measured results which needs to pass through the I/O Pads. Because the external instruments would produce the noise influence and the ground bounce caused by the I/O pad transitions affects the measurement, off-chip measurement circuits will mak
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Ku, Hsing-Yen, and 顧興彥. "An All-Digital Feed-Forward CDR Circuit for USB." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/03886153697415879012.

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碩士<br>國立高雄師範大學<br>電子工程學系<br>103<br>This paper introduces the architecture of traditional analog CDR and digital CDR circuit first. Then, we propose an all-digital feed-forward CDR with modified phase detector. The proposed feed-forward CDR architecture is composed of phase detector, digital filter and data decision blocks with a reference clock. The proposed feed-forward CDR is applied to USB2.0 system to test its performance. In this paper, we use Verilog programming language to write the code of the architecture and implement it in Altera DE2-115 FPGA platform. The proposed CDR approach
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Books on the topic "ALL Digital circuit"

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Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer, 2016.

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Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer, 2013.

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Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer London, Limited, 2013.

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Anderson, James A. Computing Hardware. Oxford University Press, 2018. http://dx.doi.org/10.1093/acprof:oso/9780199357789.003.0003.

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Digital computers are built from hardware of great simplicity. First, they are built from devices with two states: on or off, one or zero, high voltage or low voltage, or logical TRUE or FALSE. Second, the devices are connected with extremely fine connections, currently on the order of size of a large virus. Their utility, value, and perceived extreme complexity lie in the software controlling them. Different devices have been used to build computers: relays, vacuum tubes, transistors, and integrated circuits. Theoretically, all can run the same software, only slower or faster. More exotic tec
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González, Mónica Liliana. Dispositivos electrónicos. Editorial de la Universidad Nacional de La Plata (EDULP), 2015. http://dx.doi.org/10.35537/10915/49424.

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Este texto presenta los fundamentos de los Dispositivos Electrónicos básicos, principio físico de funcionamiento y aplicación en circuitos simples. El Capítulo 1 trata al Diodo, dispositivo semiconductor básico, no lineal, sus características y limitaciones de funcionamiento y el estudio de modelos eléctricos equivalentes lineales que permitan utilizar técnicas de análisis de circuitos en circuitos simples. El Capítulo 2 trata al Transistor Bipolar de Unión. Extendiendo el conocimiento logrado en el estudio del Diodo se interpreta el funcionamiento físico de este dispositivo más complejo. Adem
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Radakovich, Rosario. Mutaciones del consumo cultural en el siglo XXI. Teseo, 2019. http://dx.doi.org/10.55778/ts877232219.

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&lt;p&gt;El universo cultural ha cambiado radicalmente en los últimos años. Cambiaron los hábitos, gustos, prácticas y rituales de consumo cultural, así como las sensibilidades, las experiencias y los mecanismos de distinción que anclaban algunas expresiones culturales a determinados patrones sociales. Se modificaron también las estructuras de producción cultural a partir de la tecnología y la desmaterialización de las formas de circulación de la cultura.&lt;/p&gt;&lt;p&gt;&lt;span&gt;En este contexto, presentamos una selección de trabajos queanalizan la internacionalización territorial y virt
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Book chapters on the topic "ALL Digital circuit"

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Frappé, A., A. Kaiser, A. Flament, and B. Stefanelli. "Multimode Transmitters with ΔΣ-Based All-Digital RF Signal Generation." In Analog Circuit Design. Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3083-2_17.

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Karimiyan, Hossein, Andrea Calimera, Alberto Macii, Enrico Macii, and Massimo Poncino. "An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_17.

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Schrape, Oliver, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, and Ulrich Jagdhold. "An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17752-1_22.

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Smith, S. D., A. C. Walker, F. A. P. Tooley, J. G. H. Mathew, and M. R. Taghizadeh. "Demonstration of a Triple Bistable-Element Loop Circuit for a Digital Parallel All-Optical Computer." In Springer Proceedings in Physics. Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/978-3-642-46580-2_3.

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Ruffieux, David, Nicola Scolari, Frédéric Giroud, et al. "A 32 kHz DTCXO RTC Module with an Overall Accuracy of ±1 ppm and an All-Digital 0.1 ppm Compensation-Resolution Scheme." In Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-61285-0_9.

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Saxena, Amit, R. K. Sharma, Manoj Kumar, and R. S. Gupta. "Gate All Around 22 nm SOI Schottky Barrier MOSFET with High ION/IOFF Current Ratio for Low-Power Digital and Analog Circuit Applications." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0412-9_6.

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Dutta Roy, Suhash Chandra. "Derivation of Second-Order Canonic All-Pass Digital Filter Realizations." In Circuits, Systems and Signal Processing. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-6919-2_34.

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Goswami, Vidhi, Brijesh Kumar, and Richa Yadav. "All-p-Type Digital Circuits Using Single Gate and Double Gate Organic Field Effect Transistors." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-7077-3_7.

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Awasthi, Shashank, Satya Prakash Yadav, Manish Chhabra, Richa Gupta, and Rajesh Pokhariyal. "Design and Implementation of a Clock Generator Based on All Digital PLL (ADPLL)." In A Practitioner's Approach to Problem-Solving using AI. BENTHAM SCIENCE PUBLISHERS, 2024. http://dx.doi.org/10.2174/9789815305364124010014.

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Every electronic circuit now includes a clock, which is essential because it regulates the speed and efficiency of electronic circuits. The need for reliable and accurate clock generation mechanisms in the circuits thus increases. There are two ways to generate a clock. The first option is to use a crystal oscillator, which gives the circuit a fixed clock. However, if different clocks are required in separate system components, we must use several crystal oscillators, which increases the circuit's size and complexity. The second choice is to employ a phase-locked loop (PLL) clock generator sys
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Oliveira, Arlindo. "From Maxwell to the Internet." In The Digital Mind. The MIT Press, 2017. http://dx.doi.org/10.7551/mitpress/9780262036030.003.0003.

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The chapter covers the developments in science that led to the digital computers of today. It all started with the understanding of electromagnetic phenomena, made possible by the discovery of Maxwell’s equations, and all the developments that followed and made possible the controlled used of electricity. Following up on the great developments of the last half of the 19th century, the great discoveries in physics led to the invention of the transistor, one of the most important creations of humanity. Transistors made integrated circuits with millions and billions of transistors possible, thank
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Conference papers on the topic "ALL Digital circuit"

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Tooley, F. A. P., B. S. Wherrett, N. C. Craft, M. R. Taghizadeh, J. F. Snowdon, and S. D. Smith. "All-Optical Digital Circuits." In Optical Bistability. Optica Publishing Group, 1988. http://dx.doi.org/10.1364/obi.1988.thd.9.

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Absorbing interference filters can be used as optical three-port logic gates exhibiting gain, hard-limiting single wavelength operation [1]. Furthermore, their large-area (~ cm2) uniformity ensures that two-dimensional arrays of gates (~ 100) can be operated independently with similar power transfer characteristics (a variation of a few percent in the switching power). Such devices offer the potential to demonstrate the feasibility of novel digital computing techniques. The presentation will describe the successful operation of two looped optical circuits; a 4-channel flip-flop and a circuit w
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Smith, S. D., J. G. H. Mathew, M. R. Taghizadeh, F. A. P. Tooiey, and A. C. Walker. "Demonstration of a Triple Bistable-Element Loop Circuit for a Digital Parallel All-Optical Computer." In Optical Bistability. Optica Publishing Group, 1985. http://dx.doi.org/10.1364/obi.1985.ma3.

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An essential feature for any logic gate in an all-optical circuit is cascadibility, ie. the change in output from one device must be of sufficient magnitude to switch the next. We have developed nonlinear interference filters as bistable optical logic gates and have already shown them to be cascadable in simple all-optical digital circuits(1). This paper describes the successful operation of a three-element loop circuit with programmable control of gate bias levels. Such a configuration, extended to arrays of bistable elements, can form the basis of a digital all-optical loop processor.
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Fu-Jen Hsieh and Shao-Ku Kao. "Fast locking PLL with all-digital locked-aid circuit." In 2010 IEEE International Conference of Electron Devices and Solid- State Circuits (EDSSC). IEEE, 2010. http://dx.doi.org/10.1109/edssc.2010.5713762.

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Pasha, Muhammad Touqir, Niklas U. Andersson, and Mark Vesterbacka. "Power-efficient time-to-digital converter for all-digital frequency locked loops." In 2015 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2015. http://dx.doi.org/10.1109/ecctd.2015.7300008.

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SAKAI, Yuki, Hiroyuki NAKASE, Yoji ISOTA, and Kazuo TSUBOUCHI. "All digital One- chip Wireless Modem LSI with Acquisition Circuit." In 2003 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2003. http://dx.doi.org/10.7567/ssdm.2003.p1-6.

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Ensafdaran, Masoud, and Mojtaba Atarodi. "A noise shaped flash time to digital converter for all digital frequency synthesizers." In 2009 European Conference on Circuit Theory and Design (ECCTD 2009). IEEE, 2009. http://dx.doi.org/10.1109/ecctd.2009.5275130.

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Zhuang, Jingcheng, and Robert Bogdan Staszewski. "Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL." In 2013 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2013. http://dx.doi.org/10.1109/ecctd.2013.6662211.

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Raptakis, Adam, Costas Oustoglou, and Paul P. Sotiriadis. "Laboratory jitter removal circuit for single-bit all-digital frequency synthesis." In 2017 Panhellenic Conference on Electronics and Telecommunications (PACET). IEEE, 2017. http://dx.doi.org/10.1109/pacet.2017.8259964.

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Fuegger, Matthias, Attila Kinali, Christoph Lenzen, and Ben Wiederhake. "Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance." In 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). IEEE, 2018. http://dx.doi.org/10.1109/async.2018.00025.

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Tsai, Ming-Chien, Ching-Hwa Cheng, and Chiou-Mao Yang. "An All-Digital High-Precision Built-In Delay Time Measurement Circuit." In 26th IEEE VLSI Test Symposium (vts 2008). IEEE, 2008. http://dx.doi.org/10.1109/vts.2008.25.

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Reports on the topic "ALL Digital circuit"

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Filippo, Agustín, Carlos Guaipatín, Lucas Navarro, and Federico Wyss. México y la cadena de valor de los semiconductores: oportunidades de cara al nuevo escenario global. Banco Interamericano de Desarrollo, 2022. http://dx.doi.org/10.18235/0004276.

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Los semiconductores, chips, o circuitos integrados, son insumos clave para la producción del más amplio y variado espectro de actividades sociales y productivas. Debido a la pandemia, y a las vulnerabilidades propias de esta cadena de valor -que fueron analizadas en un estudio previo, la economía global enfrenta una crisis de abastecimiento de semiconductores impulsada por un quiebre estructural hacia una mayor demanda de productos digitales. Esto derivó en cuantiosos anuncios de inversión de las empresas líderes del sector, junto con fuertes estímulos de los gobiernos, para expandir su capaci
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2

Vargas-Herrera, Hernando, Pamela Andrea Cardozo-Ortiz, Clara Lía Machado-Franco, et al. Reporte de Sistemas de Pago - Junio de 2021. Banco de la República de Colombia, 2021. http://dx.doi.org/10.32468/rept-sist-pag.2021.

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El Banco de la República, con el Reporte de Sistemas de Pago, entrega un panorama completo de la infraestructura financiera local, siendo este un producto importante de la labor de seguimiento a dicha infraestructura. Las cifras contenidas en este reporte corresponden al año 2020, período de pandemia durante el cual las medidas de confinamiento para aliviar la tensión sobre el sistema de salud generaron para Colombia, al igual que en la mayoría de los países, una fuerte reducción de la actividad económica y el consumo. Desde el comienzo de la pandemia, la Junta Directiva del Banco de la Repúbl
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3

Payment Systems Report - June of 2020. Banco de la República de Colombia, 2021. http://dx.doi.org/10.32468/rept-sist-pag.eng.2020.

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With its annual Payment Systems Report, Banco de la República offers a complete overview of the infrastructure of Colombia’s financial market. Each edition of the report has four objectives: 1) to publicize a consolidated account of how the figures for payment infrastructures have evolved with respect to both financial assets and goods and services; 2) to summarize the issues that are being debated internationally and are of interest to the industry that provides payment clearing and settlement services; 3) to offer the public an explanation of the ideas and concepts behind retail-value paymen
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4

Payment Systems Report - June of 2021. Banco de la República, 2022. http://dx.doi.org/10.32468/rept-sist-pag.eng.2021.

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Banco de la República provides a comprehensive overview of Colombia’s finan¬cial infrastructure in its Payment Systems Report, which is an important product of the work it does to oversee that infrastructure. The figures published in this edition of the report are for the year 2020, a pandemic period in which the con¬tainment measures designed and adopted to alleviate the strain on the health system led to a sharp reduction in economic activity and consumption in Colom¬bia, as was the case in most countries. At the start of the pandemic, the Board of Directors of Banco de la República adopted
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