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Journal articles on the topic 'ALL Digital circuit'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Manjula, Jayamma. "Analysis of Carbon Nanotube based Ternary Multiplexer." Recent Trends in Control and Converter 6, no. 1 (2023): 1–6. https://doi.org/10.5281/zenodo.7638462.

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<em>In this paper, a new ternary multiplexer has been analyzed which are fundamental components of all ternary digital logic circuits. Multiplexer is the most used digital component is many digital circuits. </em><em>A multiple-valued logic (MVL) circuit uses less energy and has more valued logic in each digit than a binary logic circuit. As a result, a ternary multiplier (TMUL) for embedded circuits with low power consumption is proposed in this paper. The cascading proposed ternary multiplexer is all that is used in the CNTFET-based TMUL circuit to reduce the number of transistors and boost

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2

Cherubini, G., and S. Pupolin. "Performance Analysis of an All-Digital Acquisition Circuit." IEEE Transactions on Communications 33, no. 8 (1985): 862–68. http://dx.doi.org/10.1109/tcom.1985.1096394.

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3

M.Indu*, S.HasmashruthiA.Nandhini, and N.Megala. "GLITCH-FREE NAND-BASED DIGITALLY CONTROLLED DELAY LINES." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 4 (2016): 117–22. https://doi.org/10.5281/zenodo.48842.

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Glitch is an undesired transition that occurs before the signal settles to its intended value. It is an electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit. The existing Glitch Free NAND-based Digitally Controlled Delay Lines (DCDL) presented some glitching problem which limited their applications. To overcome this limitation new NAND-based DCDL is proposed. This will maintain the same resolution and minimum delay of existing NAND-based DCDL. The proposed DCDL will be working on the basis of two control signals which are u

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4

Mokhtarnia, Hossein, Shahram Etemadi Borujeni, and Mohammad Saeed Ehsani. "Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950240. http://dx.doi.org/10.1142/s0218126619502402.

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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the propo

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Pan, Zhong Liang, and Ling Chen. "A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams." Applied Mechanics and Materials 29-32 (August 2010): 1040–45. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1040.

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The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The

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Hossain, M., M. P. Singh, and J. K. Rakshit. "Modelling of one-bit Arithmetic Logic Circuit using silicon micro-ring resonator." Journal of Physics: Conference Series 2335, no. 1 (2022): 012003. http://dx.doi.org/10.1088/1742-6596/2335/1/012003.

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Abstract All-optical technology overcomes the problems that arise in traditional digital circuits such as speed limitation, energy consumption and size. In this manuscript, we have implemented a one-bit arithmetic logic circuit employing all-optical silicon micro-ring resonator that utilizes the advantages over other all-optical techniques. The Arithmetic logic circuit is the core component of ultra-fast combinational circuits. The proposed arithmetic logic circuit is validated through MATLAB at about 260 Gbps. Performance of our design has been investigated by numerical simulation. The critic

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Aryanpur, P., and A. A. Prihod'ko. "Using programs of the MicroCap family to study and designing digital components and circuits." Electronics and Communications 16, no. 5 (2012): 48–54. http://dx.doi.org/10.20535/2312-1807.2011.16.5.247740.

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Functional possibilities of the programs of family MicroCap are considered for a study and design of digital components, circuits and systems in courses for digital to circuit technique. General principles design is expounded for all digital objects and features of modeling digital objects of combinative type

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8

Fischette, Dennis M., Alvin L. S. Loke, Richard J. DeSantis, and Gerry R. Talbot. "An Embedded All-Digital Circuit to Measure PLL Response." IEEE Journal of Solid-State Circuits 45, no. 8 (2010): 1492–503. http://dx.doi.org/10.1109/jssc.2010.2048143.

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9

Parandin, Fariborz, Saeed Olyaee, Reza Kamarian, and Mohamadreza Jomour. "Design and Simulation of Linear All-Optical Comparator Based on Square-Lattice Photonic Crystals." Photonics 9, no. 7 (2022): 459. http://dx.doi.org/10.3390/photonics9070459.

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An optical comparator is an important logic circuit used in digital designs. Photonic crystals are among the platforms for implementing different kinds of gates and logic circuits, and they are structures with alternating refractive indices. In this paper, an optical comparator is designed and simulated based on a square lattice photonic crystal. In the design of this comparator, a small-sized structure is used. The simulation results show that in the proposed comparator, there is a high difference between logical values “0” and “1”, which are defined based on the optical power level. Due to t

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10

Seyedi, Saeid, Nima Jafari Navimipour, and Akira Otsuki. "A New Nano-Scale and Energy-Optimized Reversible Digital Circuit Based on Quantum Technology." Electronics 11, no. 23 (2022): 4038. http://dx.doi.org/10.3390/electronics11234038.

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A nano-scale quantum-dot cellular automaton (QCA) is one of the most promising replacements for CMOS technology. Despite the potential advantages of this technology, QCA circuits are frequently plagued by numerous forms of manufacturing faults (such as a missing cell, extra cell, displacement cell, and rotated cell), making them prone to failure. As a result, in QCA technology, the design of reversible circuits has received much attention. Reversible circuits are resistant to many kinds of faults due to their inherent properties and have the possibility of data reversibility, which is importan

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11

Pan, Zhong Liang, and Ling Chen. "Test Method for Crosstalk Faults in VLSI Circuits Based on Multiple-Valued Decision Diagrams." Applied Mechanics and Materials 20-23 (January 2010): 641–46. http://dx.doi.org/10.4028/www.scientific.net/amm.20-23.641.

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The crosstalk fault in VLSI circuits is one of the interference effects being caused by parasitic capacitance and inductance coupling, it can lead to functional errors of circuits. It is necessary to detect the crosstalk faults in order to insure the functions of circuits. A new test method for crosstalk faults in VLSI circuits based on multiple-valued decision diagrams is presented in this paper, the test vectors of crosstalk faults are generated by building a multiple-valued decision diagram that is a difference operation of the two multiple-valued decision diagrams corresponding to the norm

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12

Gibbs, Joe, and Lukasz Cincio. "Deep Circuit Compression for Quantum Dynamics via Tensor Networks." Quantum 9 (July 9, 2025): 1789. https://doi.org/10.22331/q-2025-07-09-1789.

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Dynamic quantum simulation is a leading application for achieving quantum advantage. However, high circuit depths remain a limiting factor on near-term quantum hardware. We present a compilation algorithm based on Matrix Product Operators for generating compressed circuits enabling real-time simulation on digital quantum computers, that for a given depth are more accurate than all Trotterizations of the same depth. By the efficient use of environment tensors, the algorithm is scalable in depth far beyond prior work, and we present circuit compilations of up to 64 layers of SU(4) gates. Surpass

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13

Jin, Yuan, Chun Hua Wang, and Ke Li. "Study on Mechanical Automation with Design of Digital Function Generator." Advanced Materials Research 703 (June 2013): 260–63. http://dx.doi.org/10.4028/www.scientific.net/amr.703.260.

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Digital function generator is widely used in mechanical automation,such as mechanical automation control and all kinds of electronic circuits. This paper firstly introduces the principle of digital waveform synthesizer and explains the specific realization method of the digital waveform synthesizer circuit. Next, it is carries on the detailed narration of the principle of DDS, the description of DDS specific design from FPGA, and provides parameter selection of the subsequent simulation processing circuit with 125 KHZ sine signal as an example. Finally, contrast the sine signal generated by th

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14

Wang, Xiaoyuan, Xinrui Zhang, Chuantao Dong, Shimul Kanti Nath, and Herbert Ho-Ching Iu. "Design and Application of Memristive Balanced Ternary Univariate Logic Circuit." Micromachines 14, no. 10 (2023): 1895. http://dx.doi.org/10.3390/mi14101895.

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This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme.

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15

Kao, Shao-Ku, and Fu-Jen Hsieh. "A fast-locking PLL with all-digital locked-aid circuit." International Journal of Electronics 100, no. 2 (2013): 245–58. http://dx.doi.org/10.1080/00207217.2012.692631.

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16

Rajeswaran, N., T. Madhu, and M. Suryakalavathi. "Hardware Testable Design of Genetic Algorithm for VLSI Circuits." Applied Mechanics and Materials 367 (August 2013): 245–49. http://dx.doi.org/10.4028/www.scientific.net/amm.367.245.

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Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.

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17

Kang, Jing, Fei Liu, Ya Hai, and Yongshan Wang. "A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit." Electronics 12, no. 7 (2023): 1610. http://dx.doi.org/10.3390/electronics12071610.

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A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is

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18

Sheng, Duo, Hsin-Ting Lee, and Fu-Chi Huang. "All-digital transmit beamformer for portable high-frequency ultrasound imaging systems." Review of Scientific Instruments 94, no. 3 (2023): 034707. http://dx.doi.org/10.1063/5.0128410.

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To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without va

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19

Fan, Han Bai, Xian Meng, and Jun Ma Hou. "Application and Debugging of All-Digital Frequency Synthesizer." Advanced Materials Research 989-994 (July 2014): 4058–61. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.4058.

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Presents the working principle of Integrated PLL chip Si4133, this paper presents the implementation of a 375MHz local oscillator for a super heterodyne transmitter/receiver by using Si4133.Using programming method to set the divider register Internal chip. In addition, this paper discuss the methods for decreases the phase noise. Debugging circuit using ICCAVR software , and show the debugging results. Facts show that the phase noise and spurious of the frequency synthesizer is low, and it is practical.

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20

Patra, Suman. "NOR Gate Based LED Inverter." International Journal for Research in Applied Science and Engineering Technology 12, no. 10 (2024): 1421–27. http://dx.doi.org/10.22214/ijraset.2024.64873.

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In this paper, the design and simulation of the LED inverter circuit using NOR gate in Proteus software is described. The aim of the practical is to show that simple digital inverter can be created with the NOR gate which is the universal gate and the LED will be used to show that the logic circuit is working. Incidentally, to turn the NOR gate into an inverter, it simply involves linking both inputs together and that simplifies all the layout. The simulation of the circuit was done using proteus software and as the input of the NOR gate-based inverter is changed the output LED source is also

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21

Calazans, Ney Laert Vilar, Taciano Ares Rodolfo, and Marcos L. L. Sartori. "Robust and Energy-Efficient Hardware: The Case for Asynchronous Design." Journal of Integrated Circuits and Systems 16, no. 2 (2021): 1–11. http://dx.doi.org/10.29292/jics.v16i2.518.

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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades,

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22

Cai, Zhi Kuang, Kai Huang, Jun Yang, and Long Xing Shi. "Built-In Self-Test Scheme for All-Digital Phase-Locked Loops." Advanced Materials Research 546-547 (July 2012): 922–27. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.922.

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This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid

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23

Li, Haoxiang. "Comparison and performance optimization of two absolute circuit designs based on Multisim." Applied and Computational Engineering 129, no. 1 (2025): 63–70. https://doi.org/10.54254/2755-2721/2025.20234.

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Digital circuits are crucial in today's technology, underpinning infrastructure such as computing, communicating, and intelligent devices. Its high efficiency, accuracy and programmable capability drive the development of information processing, data transmission and automation systems. The application of digital circuits has promoted innovation in artificial intelligence, the Internet of Things and other fields, providing strong support for the intelligence and interconnection of modern society. The absolute value circuit is discussed in this paper. The absolute value circuit is implemented f

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24

Cong, Haolin, and Massoud Pedram. "All-Digital Phase-Locked Loop in Single Flux Quantum Circuit Technology." IEEE Transactions on Applied Superconductivity 32, no. 3 (2022): 1–8. http://dx.doi.org/10.1109/tasc.2022.3151728.

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25

Go, Gwi-Han, Ki-Sang Jung, Kang-Jik Kim, and Seong-Ik Cho. "Design of Wide-range All Digital Clock and Data Recovery Circuit." Transactions of The Korean Institute of Electrical Engineers 61, no. 11 (2012): 1695–99. http://dx.doi.org/10.5370/kiee.2012.61.11.1695.

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26

Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee. "An all-digital phase-locked loop (ADPLL)-based clock recovery circuit." IEEE Journal of Solid-State Circuits 34, no. 8 (1999): 1063–73. http://dx.doi.org/10.1109/4.777104.

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27

Su, Jun-Ren, Te-Wen Liao, and Chung-Chih Hung. "All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 6 (2013): 1154–64. http://dx.doi.org/10.1109/tvlsi.2012.2205168.

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28

Biereigel, Stefan, Szymon Kulis, Paulo Moreira, Alexander Kölpin, Paul Leroux, and Jeffrey Prinzie. "Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS." Electronics 10, no. 22 (2021): 2741. http://dx.doi.org/10.3390/electronics10222741.

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This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock

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29

Al-Araji, Ahmed. "Digital Protection System of the Engine-Generator Based Microcontroller AT89C51." Journal of Al-Rafidain University College For Sciences ( Print ISSN: 1681-6870 ,Online ISSN: 2790-2293 ), no. 1 (October 25, 2021): 38–48. http://dx.doi.org/10.55562/jrucs.v24i1.463.

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This paper describes the design and implementation of the engine-generator protection circuit based microcontroller AT89C51, which is very popular and is used in a huge number of applications in professional systems and amateur projects. This digital electronic circuit shows further possibilities of improvements, and is employed as a device to protect the engine-generator from the fault type that may occur during operation of the generator such as over heat; oil alert; over speed; and over voltage that will damage the engine and exciter of the generator. It is also used to protect all devices

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30

Abuelma'atti, Muhammad Taher. "Programmable Current-Mode Universal Active Filters Employing Current Conveyors." Active and Passive Electronic Components 21, no. 3 (1998): 221–30. http://dx.doi.org/10.1155/1998/80984.

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Novel current-mode active filter circuits using current-conveyors are presented. The proposed circuits can realize all standard second-order filter functions. The circuits enjoy high output impedances and can, therefore, be easily cascaded to produce higher order filters. Moreover, the realized filter function can be easily programmed using at most a 13-bit digital number without changing the circuit topology.

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31

Viraktamath, Dr S. V. "Arduino Digital Clock without RTC Module." International Journal for Research in Applied Science and Engineering Technology 9, no. 8 (2021): 967–71. http://dx.doi.org/10.22214/ijraset.2021.37546.

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Abstract: This paper analyzes a clock using Arduino without Real time clock (RTC). The development of the digital clock in Arduino is to provide its own time without RTC. Generally, electronic circuit designers use RTC to construct a clock. Such a circuit requires an extra circuit and power. The CMOS battery supplies power to the RTC, once the CMOS battery power is discharged. It automatically erases the date and time and requires an update from an external device. Considering these facts, RTC is avoided and code with nested looping is used to maintain timing in Arduino. It enables us to modif

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32

Tian, Yuan, Chun Hong Hu, Jian Hua Lu, and Qing Wei Dong. "The Hardware Design on the System of High-Speed Image Gathering Based on FPGA and DSP." Applied Mechanics and Materials 568-570 (June 2014): 701–4. http://dx.doi.org/10.4028/www.scientific.net/amm.568-570.701.

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On the foundation of analyzing in an all-round way to the current application situations and development trends with image acquisition and treatment technology on domestic and international, the paper designed one system that aim at the problems including high-speed rate of analog-to-digital conversion, heavy amount data and complicated arithmetic and so on that existing in high-speed image acquisition board and realize the high-speed acquisition and processing of image. The key part of the system is DSP and programmable arrays device FPGA, The main circuit including the standard video signal

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33

Hoiriyah, Hoiriyah. "SIMULASI GERBANG DASAR LOGIKA DALAM APLIKASI." Jurnal Teknik Informatika dan Elektro 2, no. 2 (2022): 01–08. http://dx.doi.org/10.55542/jurtie.v2i2.405.

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It is no longer a secret that all science is currently developing and has technological advances that cannot be denied, especially in digital technology which is currently popular, one of which is a digital electronic system that is composed of logic gates so that it becomes a digital system formed from logic elements. the smallest is the logic gate (Logic Gate): OR, AND and NOT where the circuit work process on this logic gate uses Boolean algebra principles. In its implementation it is rather difficult to provide an understanding of logic gates manually or in theory to the public and the gen

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34

Castro, Lucas, and Rodolfo Azevedo. "Circuitly: A visual and constructive framework for teaching digital circuits." International Journal of Computer Architecture Education 9, no. 1 (2020): 10–15. http://dx.doi.org/10.5753/ijcae.2020.4839.

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This paper describes an interactive and student-friendly framework for teaching digital circuits and computer architecture topics. It aims to improve students learning process by providing a visual drag-and-drop circuit design editor, interactive simulation, signal monitoring and testbench tools - all integrated in a widely accessible application that runs in the browser. Circuitly does so in a programmatic way, to help students better understand the Hardware Description Languages they will encounter in the future.

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Yoon, Myungchul. "Design of an Efficient k-Winners-Take-All Module for ASIC Design." International Journal of Emerging Technology and Advanced Engineering 12, no. 10 (2022): 198–205. http://dx.doi.org/10.46338/ijetae1022_21.

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An efficient k-Winners-Take-All (kWTA) module that selects and sorts the k largest data from multiple binary data is presented in this paper. This module is implemented by pipelining a k largest element selector and a sorting circuit, both of which operate in the bit-serial method. The module completes finding and sorting the k-largest data from N of m-bit binary data in m clock cycles. This could be used as a hardware module for the ASIC design which can be employed for any ASIC chip requiring kWTA operation of digital data. The time complexity of this module is O(N) and its delay is independ

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36

Kumar, Umesh. "A Retrospection of Chaotic Phenomena in Electrical Systems." Active and Passive Electronic Components 21, no. 1 (1998): 1–15. http://dx.doi.org/10.1155/1998/32462.

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In the last decade new phenomena have been observed in all areas of non linear dynamics, principal among these being ‘Chaotic phenomena’. Chaos has been reported virtually from every scientific discipline. This paper summarizes a study of the chaotic phenomena in electrical systems and attempts to translate the mathematical ideas and techniques into language that engineers and applied scientists can use to study ‘Chaos’. Towards this end, the paper has summarized the study of chaos in several examples like Chua’s circuit family; Folded Torus circuit; non-autonomous circuits; switched capacitor

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Heo, Yoon, and Won-Young Lee. "An All-Digital Dual-Mode Clock and Data Recovery Circuit for Human Body Communication Systems." Electronics 13, no. 23 (2024): 4832. https://doi.org/10.3390/electronics13234832.

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This paper describes an all-digital clock and data recovery (CDR) circuit for implementing edge processing with a wireless body area network (WBAN). The CDR circuit performs delay-locked loop (DLL)-based and phase-locked loop (PLL)-based operations depending on the use of an external reference clock and is implemented using a digital method that is robust against external noise. The clock generator circuit shared by the two operation methods is described in detail, and the CDR circuit recovers 42 Mb/s input data and a 42 MHz clock, which are the specifications of human body communication (HBC)

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38

Debany, Warren H. "Coverage of Node Shorts Using Internal Access and Equivalence Classes." VLSI Design 1, no. 1 (1993): 71–85. http://dx.doi.org/10.1155/1993/42309.

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A method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internal access test techniques. These are test techniques that provide observability of circuit nodes, such as CMOS power supply current monitoring (including IDDQ), CrossCheck, and voltage contrast. Only fault-free circuit simulation is used to obtain node states. Two versions of the algorithm are presented: a simple algorithm that is suitable for use with two-state logic (0 and 1), and a more general algorithm for four-state logic (0, 1, X, and Z). The result is a set of sets of nod

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Joel Matthew Thomas Matthew, Nur Zatil Ismah Hashim, Sofiyah Sal Hamid, and Nuha A. Rhaffor. "Enhancing circuit development and layout implementation of benchmark circuit in 0.18-µm CMOS technology." International Journal of Nanoelectronics and Materials (IJNeaM) 18, no. 1 (2025): 1–6. https://doi.org/10.58915/ijneam.v18i1.1679.

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Power consumption and delay are the most critical factors in circuit development and layout implementation. It is challenging to optimize all aspects simultaneously. This research addresses this challenge by analysing the power consumption and delay effects in benchmark circuit operation, C6288, using 0.18-µm CMOS technology operating at an optimal voltage of 1.6V. Additionally, this research also contributes to developing the initial layout implementation of a benchmark circuit with a 10% area reduction. By utilizing new layout techniques and simulations, the study has proven a significant de

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Yoon, Myungchul. "A VLSI Design for Scalable High-Speed Digital Winner-Take-All Circuit." JSTS:Journal of Semiconductor Technology and Science 15, no. 2 (2015): 177–83. http://dx.doi.org/10.5573/jsts.2015.15.2.177.

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41

Grover, W. D., J. Brown, T. Friesen, and S. Marsh. "All-digital multipoint adaptive delay compensation circuit for low skew clock distribution." Electronics Letters 31, no. 23 (1995): 1996–98. http://dx.doi.org/10.1049/el:19951362.

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42

Xing, Ya Min, and Sheng Hu Liu. "Research on LWD Transmit Circuit Based on DDS Technology." Applied Mechanics and Materials 220-223 (November 2012): 1052–55. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.1052.

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A new type of logging transmit circuit applied to measurement while drilling (MWD) based on DDS technology is presented. As for logging instrument, Electromagnetic wave source is very important .The logging transmit circuit adopts TMS320VC33 series digital signal processing chip as main controller, in addition, LWD(logging while drilling) signal waveform generation circuit, peripheral signal processing circuit, DDS module, DSP and AD9850 interfaces, etc have been given.2MHz and 400KHz digital transmit circuit mainly composed of DDS AD9850 , which carries out the shift of the phase and the limi

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Rohit, Kumar *. Sachin Tyagi. "DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 446–56. https://doi.org/10.5281/zenodo.59758.

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With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip c

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Pardo, Fernando, Càndid Reig, José A. Boluda, and Francisco Vegara. "A 4K-Input High-Speed Winner-Take-All (WTA) Circuit with Single-Winner Selection for Change-Driven Vision Sensors." Sensors 19, no. 2 (2019): 437. http://dx.doi.org/10.3390/s19020437.

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Winner-Take-All (WTA) circuits play an important role in applications where a single element must be selected according to its relevance. They have been successfully applied in neural networks and vision sensors. These applications usually require a large number of inputs for the WTA circuit, especially for vision applications where thousands to millions of pixels may compete to be selected. WTA circuits usually exhibit poor response-time scaling with the number of competitors, and most of the current WTA implementations are designed to work with less than 100 inputs. Another problem related t

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Pawase, Ramesh, and N. P. Futane. "MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (2018): 120. http://dx.doi.org/10.11591/ijres.v6.i2.pp120-126.

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<p>Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with le

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Siddesh, K. B., S. Roopa, Parveen B. A. Farzana, and T. Tanuja. "Design of duty cycle correction circuit using ASIC implementation for high speed communication." i-manager’s Journal on Electronics Engineering 13, no. 3 (2023): 33. http://dx.doi.org/10.26634/jele.13.3.19969.

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This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cy

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Zhongliang, Pan, Chen Ling, and Chen Yihui. "Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 77–83. http://dx.doi.org/10.2174/1874129001408010077.

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The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, th

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MASUDA, T., N. SHIRAMIZU, E. OHUE, et al. "A SiGe HBT IC CHIPSET for40-Gb/s OPTICAL TRANSMISSION SYSTEMS." International Journal of High Speed Electronics and Systems 13, no. 01 (2003): 239–63. http://dx.doi.org/10.1142/s0129156403001594.

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Using a 0.2-μm self-aligned epitaxial-growth silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology, we have developed a chipset for 40-Gb/s time-division multiplexing optical transmission systems. In this paper, we describe seven analog and digital ICs: a 45-GHz bandwidth transimpedance amplifier, a 48.7-GHz bandwidth automatic-gain-controllable amplifier, a 40-Gb/s decision circuit, a 40-Gb/s full-wave rectifier, a 40-Gb/s limiting amplifier with a 32-dB gain, a 45-Gb/s 1:4 demultiplexer, and a 45-Gb/s 4:1 multiplexer. To increase bandwidth of the transimpedance amplifie

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FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

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Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the I

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Sayandeep, Nag. "Analog Versus Digital Design: When and Where to Make the Cut." Mapana - Journal of Sciences 1, no. 1 (2002): 69–80. http://dx.doi.org/10.12723/mjs.1.7.

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System designers are frequently asked to create circuits that measure and control the analog world. One of the the challenges in these types of designs is to know when to convert the signal signal from the analog domain to the digital domain. In the analog domain, signal conditioning techniques such as gain, offset, and filtering are used to quickly modify the incoming signal. Alternatively, mathematical algorithms are used in the digital domain to implement similar functions. Every system design is unique and requires custom solutions for each case, but there are some general guidelines that

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