Relevant bibliographies by topics / All digital phase locked loop

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Academic literature on the topic 'All digital phase locked loop'

Author: Grafiati
Published: 4 June 2021
Last updated: 27 July 2025

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Journal articles on the topic "All digital phase locked loop"

1

Staszewski, R. B., and P. T. Balsara. "Phase-domain all-digital phase-locked loop." IEEE Transactions on Circuits and Systems II: Express Briefs 52, no. 3 (2005): 159–63. http://dx.doi.org/10.1109/tcsii.2004.842067.

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Anupama, Patil* Dr P.H.Tandel. "DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP." DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP 5, no. 5 (2016): 134–38. https://doi.org/10.5281/zenodo.51007.

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The Phase Locked Loop (PLL) is an almost always used electronics circuit for communication systems like modulator, demodulator, frequency generator and frequency synthesizer etc. All-digital phase locked loop (ADPLL) is digital version of the PLL. In this paper, a novel Hilbert transform based phase detection system for all-digital phase locked loop (ADPLL) is presented. The digital discrete time components are used to realize the phase detector system reducing the complexity of the design. The Hilbert transform based phase detection system provides a definite advantage over conventional analo
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S C, Mrs Shyamala, Latish Patil, Srinivas Gowda K R, Yashwanth T, and Dhruva Kumar T R. "Realization of an All-Digital Phase-Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39448.

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An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog. Key Words: All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)
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B R, Mr Chethan, Punith H D, Abhishek Gowda H A, Manoj B S, and Rahul H R. "Design of Phase Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39446.

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A Phase-Locked Loop (PLL) is a crucial feedback control system used to synchronize the phase of an output signal with a reference signal. This paper explores the design, analysis, and applications of PLLs in modern communication systems, digital circuits, and power electronics. The study covers the fundamental components of a PLL—phase detector, low-pass filter, and voltage-controlled oscillator (VCO)—and their interactions in achieving phase synchronization. Key performance parameters such as lock time, jitter, stability, and noise sensitivity are examined in detail. Furthermore, the paper di
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Kumm, Martin, Harald Klingbeil, and Peter Zipf. "An FPGA-Based Linear All-Digital Phase-Locked Loop." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 9 (2010): 2487–97. http://dx.doi.org/10.1109/tcsi.2010.2046237.

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Shayan, Y. R., and T. Le-Ngoc. "All digital phase-locked loop: concepts, design and applications." IEE Proceedings F Radar and Signal Processing 136, no. 1 (1989): 53. http://dx.doi.org/10.1049/ip-f-2.1989.0007.

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R, Swetha, J. Manjula, and A. Ruhan bevi. "Design of All Digital Phase Locked Loop for Wireless Applications." International Journal of Engineering & Technology 7, no. 3.12 (2018): 836. http://dx.doi.org/10.14419/ijet.v7i3.12.16513.

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This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.
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Sun, Hua Fang, Xin Ning Liu, and Xin Chen. "Optimum Digital Filter for High-Performance All-Digital Phase-Locked Loop." Applied Mechanics and Materials 182-183 (June 2012): 587–92. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.587.

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The effect of all-digital phase-locked loop (ADPLL) digital filter parameters on the jitter is investigated in time domain, and a systematic design procedure for ADPLL is presented. The pro-posed method not only estimates the output jitter of an ADPLL, but also finds the optimal filter pa-rameter minimizing the overall ADPLL timing jitter. To verify the theoretic analysis, an ADPLL behavior model in matlab is designed. The simulation shows significant performance improvement on the timing jitter.
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Park, Gun-Ho, Jae-Jin Lee, Seong-Jin Oh, and Kang-Yoon Lee. "Low-Power All Digital Delay Locked Loop with Dynamically Phase Error Tracking for a PVT Compensation Loop." Journal of Korean Institute of Electromagnetic Engineering and Science 31, no. 7 (2020): 571–76. http://dx.doi.org/10.5515/kjkiees.2020.31.7.571.

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Jurgo, Marijan. "ALL DIGITAL PHASE-LOCKED LOOP / VISIŠKAI SKAITMENINĖ FAZĖS DERINIMO KILPA." Mokslas - Lietuvos ateitis 5, no. 2 (2013): 128–32. http://dx.doi.org/10.3846/mla.2013.24.

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The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33
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Dissertations / Theses on the topic "All digital phase locked loop"

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Johnson, Alfred, and Fredrik Andersson. "Modeling and Characterization of an All-Digital Phase-Locked Loop." Thesis, Linköping University, Department of Science and Technology, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54441.

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<p>The thesis "Modeling and Characterization of an All-Digital PLL" aims to create a behavioral model of an All-Digital Phase-Locked-Loop (ADPLL). The model should be able to perform accurate and time-effective simulations. Based on the model, a sub-block requirement will be presented as decision basis for test chip manufacturing.</p><p>The wireless communications industry has grown tremendously in the recent years, leading to strong demand for smaller, faster, better and less power consuming circuits. Digital circuits have better properties in these aspects, which have resulted in great inter
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Zhang, Chi. "System Level Modeling and Verification of All-digital Phase-locked Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175151.

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In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of local oscillators. Therefore, evaluating jitter/phase noise should be an essential part when designing wireless communication systems. Typically, LO is achieved by traditional analog PLL. These prototypes have several drawbacks including low integration, narrow bandwidth and high phase noise. With the development of digital techniques, approaches t
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Muppala, Prashanth. "High-frequency wide-range all digital phase locked loop in 90nm CMOS." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049.

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Shen, Jue. "Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.

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With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL. PLL has always been a traditional mixed-signal system limited by analog part performance. Around 2000, there emerged ADPLL of which all the blocks besides oscillator are implemented in digital circuits. There have been successful examples in application of Bluetooth, and it is moving to improve results for application of WiMax and ad-hoc frequency hopping communication link. Based on the theoretic and m
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Jiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.

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The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the pha
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Wali, Naveen, and Balamurali Radhakrishnan. "Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.

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An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were stud
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Kwong, Kelvin Kam Leung. "Implementation of DSP carrier recovery using all-digital phase-locked loop with vector rotation techniques for high speed 8-PSK modems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ36046.pdf.

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Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

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Bouloc, Jeremy. "Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4307/document.

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Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le
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Tsao, Ya-lan, and 曹亞嵐. "All Digital Phase-Locked Loop." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/33585222011275948297.

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Books on the topic "All digital phase locked loop"

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Brandonisio, Francesco, and Michael Peter Kennedy. Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03659-5.

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Purkayastha, Basab Bijoy, and Kandarpa Kumar Sarma. A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2041-1.

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Ruggles, Stephen L. Phase-lock-loop application for fiber optic receiver. National Aeronautics and Space Administration, Langley Research Center, 1991.

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W, Wills Robert, and Langley Research Center, eds. Phase-lock-loop application for fiber optic receiver. National Aeronautics and Space Administration, Langley Research Center, 1991.

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W, Wills Robert, and Langley Research Center, eds. Phase-lock-loop application for fiber optic receiver. National Aeronautics and Space Administration, Langley Research Center, 1991.

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Reeve, Whitham D. Subscriber loop signaling and transmission handbook: Digital. IEEE Press, 1995.

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Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer, 2016.

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Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer, 2013.

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Kennedy, Michael Peter, and Francesco Brandonisio. Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design. Springer London, Limited, 2013.

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Wise, Michael Glynn. Digital phase-locked loop speed control for a brushless d.c. motor. 1985.

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Book chapters on the topic "All digital phase locked loop"

1

Stephens, Donald R. "All Digital Phase-Locked Loops." In Phase-Locked Loops for Wireless Communications. Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5717-3_9.

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Brandonisio, Francesco, and Michael Peter Kennedy. "Phase Digitization in All-Digital PLLs." In Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03659-5_2.

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Brandonisio, Francesco, and Michael Peter Kennedy. "Analytical Predictions of Phase Noise in ADPLLs." In Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03659-5_4.

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Brandonisio, Francesco, and Michael Peter Kennedy. "Modelling and Estimating Phase Noise with Matlab." In Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03659-5_7.

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Brandonisio, Francesco, and Michael Peter Kennedy. "Introduction." In Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03659-5_1.

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Brandonisio, Francesco, and Michael Peter Kennedy. "A Unifying Framework for TDC Architectures." In Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03659-5_3.

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Brandonisio, Francesco, and Michael Peter Kennedy. "Advantages of Noise Shaping and Dither." In Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03659-5_5.

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Brandonisio, Francesco, and Michael Peter Kennedy. "Efficient Modeling and Simulation of Accumulator-Based ADPLLs." In Noise-Shaping All-Digital Phase-Locked Loops. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-03659-5_6.

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Jahangir, Mohd Ziauddin, Chandra Sekhar Paidimarry, Md Sikander, and M. V. Shravanthi. "Design of an All Digital Phase-Locked Loop Using Cordic Algorithm." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-5550-1_14.

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Yadav, Lalita, and Manoj Duhan. "All Digital Phase Locked Loop (ADPLL) and Its Blocks—A Comprehensive Knowledge." In New Approaches for Multidimensional Signal Processing. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-7842-5_21.

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Conference papers on the topic "All digital phase locked loop"

1

Ye, Hongsheng, Kaiming Zhong, Xinnan Guo, et al. "A 10.2-to-14.82-GHz Low-Phase-Noise All-Digital Phase-Locked Loop." In 2025 Conference of Science and Technology of Integrated Circuits (CSTIC). IEEE, 2025. https://doi.org/10.1109/cstic64481.2025.11017799.

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Koech, Tangus. "Design and Simulation of CMOS Fractional-N All-Digital Phase-Locked Loop (ADPLL)." In 2024 International Microwave and Antenna Symposium (IMAS). IEEE, 2024. https://doi.org/10.1109/imas61316.2024.10818114.

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V, Surya, and Seshachalam D. "Design of All Digital Phase Locked Loop for Binary Frequency Shift Keying Modulation." In 2024 Global Conference on Communications and Information Technologies (GCCIT). IEEE, 2024. https://doi.org/10.1109/gccit63234.2024.10862059.

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Balcioglu, Yalcin, and Gunhan Dundar. "All-digital phase locked loop design assistant." In 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). IEEE, 2015. http://dx.doi.org/10.1109/smacd.2015.7301710.

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Singhal, Aastha, Charu Madhu, and Vijay Kumar. "Designs of All Digital Phase Locked Loop." In 2014 Recent Advances in Engineering and Computational Sciences (RAECS). IEEE, 2014. http://dx.doi.org/10.1109/raecs.2014.6799523.

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Vezant, Benoit, Cedric Mansuy, Hung Tien Bui, and Francois-Raymond Boyer. "Direct digital synthesis-based all-digital phase-locked loop." In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA). IEEE, 2009. http://dx.doi.org/10.1109/newcas.2009.5290469.

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Badarov, Dimiter, and Georgy Mihov. "Teaching Methodology for All Digital Phase Locked Loop." In 2020 XI National Conference with International Participation (ELECTRONICA). IEEE, 2020. http://dx.doi.org/10.1109/electronica50406.2020.9305120.

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Badarov, Dimiter, and Georgy Mihov. "Teaching Methodology for All Digital Phase Locked Loop." In 2020 XI National Conference with International Participation (ELECTRONICA). IEEE, 2020. http://dx.doi.org/10.1109/electronica50406.2020.9305120.

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Mollen, N. A. "All-digital phase-locked loop used in a clock recovery algorithm." In IEE Colloquium on Phase Lock Loops: Theory and Practice. IEE, 1999. http://dx.doi.org/10.1049/ic:19990569.

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Bissa, Pradyuman R., and Kirti S. Pande. "All Digital Phase Locked Loop for Low Frequency Applications." In 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI). IEEE, 2018. http://dx.doi.org/10.1109/icacci.2018.8554617.

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Reports on the topic "All digital phase locked loop"

1

Pei, Alex. Numerically Controlled Phase Locked Loop Using Direct Digital Synthesizer. Office of Scientific and Technical Information (OSTI), 1993. http://dx.doi.org/10.2172/1119180.

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