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Muppala, Prashanth. "High-frequency wide-range all digital phase locked loop in 90nm CMOS." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049.
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Wali, Naveen, and Balamurali Radhakrishnan. "Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.
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An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were studied and simulated. TheVernier delay based architecture and inverter delay based architecture was designedand evaluated. There architectures provided certain short comings whilethe pseudo-differential time-to-digital converter architecture was chosen, becauseof it’s less occupation of area. Since there exists a relationship between the sizeof the delay cells and it’s time resolution, the pseudo-differential time-to-digitalconverter severed it’s purpose. The whole time-to-digital converter system was tested on a 1 V power supply,reference frequency 54-MHz which is also the reference clock Fref , and a feedbackfrequency Fckv 2.1-GHz. The power consumption was found to be around 2.78mW without dynamic clock gating. When the clock gating or bypassing is done,the power consumption is expected to be reduced considerably. The measuredtime-to-digital converter resolution is around 7 ps to 9 ps with a load variation of15 fF. The inherent delay was also found to be 5 ps. The total output noise powerwas found to be -128 dBm.
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Shen, Jue. "Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.
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With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL. PLL has always been a traditional mixed-signal system limited by analog part performance. Around 2000, there emerged ADPLL of which all the blocks besides oscillator are implemented in digital circuits. There have been successful examples in application of Bluetooth, and it is moving to improve results for application of WiMax and ad-hoc frequency hopping communication link. Based on the theoretic and measurement results of existing materials, ADPLL has shown advantages such as fast time-to-market, low area, low cost and better system integration; but it also showed disadvantages in frequency resolution and phase noise, etc. Also this new topic still opens questions in many researching points important to PLL such as tracking behavior and quantization effect. In this thesis, a non-linear phase domain model for all digital phase-locked loop (ADPLL) was established and validated. Based on that, we analyzed that ADPLL phase noise prediction derived from traditional linear quantization model became inaccurate in non-linear cases because its probability density of quantization error did not meet the premise assumption of linear model. The phenomena of bandwidth expansion and in-band phase noise decreasing peculiar to integer-N ADPLL were demonstrated and explained by matlab and verilog behavior level simulation test bench. The expression of threshold quantization step was defined and derived as the method to distinguish whether an integer-N ADPLL was in non-linear cases or not, and the results conformed to those of matlab simulation. A simplified approximation model for non-linear integer-N ADPLL with noise sources was established to predict in-band phase noise, and the trends of the results conformed to those of matlab simulation. Other basic analysis serving for the conclusions above covered: ADPLL loop dynamics, traditional linear theory and its quantitative limitations and numerical analysis of random number. Finally, a present measurement setup was demonstrated and the results were analyzed for future work.
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Jiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.
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The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry's characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc.
This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis.
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Bouloc, Jeremy. "Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4307/document.
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Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le système d'asservissement. Le projet ANR Pnano2008 intitulé : ”Cantilevers en carbure de silicium à piézorésistivité métallique pour AFM dynamique à très haute fréquence" a pour objectif d'augmenter significativement les performances d'un FM-AFM en développant un nouveau capteur de force très haute fréquence. Le but est d'augmenter la sensibilité du capteur et de diminuer le temps nécessaire à l'obtention d'une image de la surface du matériau. Le système de contrôle associé doit être capable de détecter des variations de fréquence de 100mHz pour une fréquence de résonance de 50MHz. Etant donné que les systèmes présents dans l'état de l'art ne permettent pas d'atteindre ces performances, l'objectif de cette thèse fut de développer un nouveau système de contrôle. Celui-ci est entièrement numérique et il est implémenté sur une carte de prototypage basée sur un FPGA. Dans ce mémoire, nous présentons le fonctionnement global du système ainsi que ses caractéristiques principales. Elles portent sur la détection de l'écart de fréquence de résonance du capteur de force<br>An atomic force microscope (AFM) is used to characterize insulating materials or semiconductors with a resolution up to the atomic length scale. The microscope includes a force sensor linked to a control electronic in order to properly characterize these materials. Among the various modes (static and dynamic), we focus mainly on the dynamic mode and especially on the frequency modulation mode (FM-AFM). In this mode, the force sensor is maintained as a harmonic oscillator by the servo system. The research project ANR Pnano2008 entitled: "metal piezoresistivity silicon carbide cantilever for very high frequency dynamic AFM" aims to significantly increase the performance of a FM-AFM by developing new very high frequency force sensors. The goal is to increase the sensitivity of the sensor and to decrease the time necessary to obtain topography images of the material. The control system of this new sensor must be able to detect frequency variations as small as 100mHz for cantilevers with resonance frequencies up to 50MHz. Since the state-of-the-art systems doe not present these performances, the objective of this thesis was to develop a new control system. It is fully digital and it is implemented on a FPGA based prototyping board. In this report, we present the system overall functioning and its main features which are related to the cantilever resonant frequency detection. This detection is managed by a phase locked loop (PLL) which is the key element of the system
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Johnson, Alfred, and Fredrik Andersson. "Modeling and Characterization of an All-Digital Phase-Locked Loop." Thesis, Linköping University, Department of Science and Technology, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54441.
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<p>The thesis "Modeling and Characterization of an All-Digital PLL" aims to create a behavioral model of an All-Digital Phase-Locked-Loop (ADPLL). The model should be able to perform accurate and time-effective simulations. Based on the model, a sub-block requirement will be presented as decision basis for test chip manufacturing.</p><p>The wireless communications industry has grown tremendously in the recent years, leading to strong demand for smaller, faster, better and less power consuming circuits. Digital circuits have better properties in these aspects, which have resulted in great interest for more digitally intensive circuits. Since frequency synthesis is an essential part of any wireless system an all digital PLL is very attractive.</p><p>Traditional simulation tools are unable to simulate a complex system like an ADPLL. Since production costs are high and it is necessary to verify the integrity of the design and the circuit behavior before first prototype, an alternative solution is needed. One solution is to use an event-driven simulation technique that only focus on the events that occur at each clock flank. The difficulty lies in creating a realistic model of behavior.</p><p>The project has focused on meeting the phase noise requirements imposed on a WCDMA / HSDPA application. The event-driven model is implemented in Matlab because of its high flexibility during development, and large variety of analytical tools. The proposed model is based on a previously published model that has been evolved in ways that were interesting for the project. The model’s construction and accuracy have been verified against the appropriate theory. By constructing a comprehensible user interface around the model, it is convenient to examine how different parameters affect system performance.</p><p>The simulation results of the model establish how the different parameters affect the phase noise spectrum of the ADPLL. The TDC architecture has big influence on the phase noise and it is of big importance to use high precision in the entire system to prevent an increased in-band noise level.</p><p>A time-effective simulation tool has successfully been constructed and a sub-block requirement specification has been presented.</p><br><p>Examensarbetet “Modeling and Characterization of an All-Digital PLL” har som syfte att skapa en beteendemodell av en All-Digital Phase-Locked-Loop (ADPLL). Modellen ska kunna generera noggranna och tidseffektiva simuleringar. Utifrån modellen ska sedan en kravspecifikation för de olika delblocken skapas för att utgöra ett beslutsunderlag för eventuell tillverkning av testchip.</p><p>Bakgrunden till projektet är att den trådlösa kommunikationsindustrin under de senaste åren har vuxit enormt vilket lett till stor efterfrågan på mindre, snabbare, bättre och energisnålare kretsar. Digitala kretsar har bättre egenskaper i dessa avseenden vilket resulterat i ett stort intresse för kretsar av denna typ. Eftersom frekvenssyntetiseringen utgör en central del i alla trådlösa system är en helt digital PLL mycket attraktiv.</p><p>Traditionella simuleringsverktyg har inte möjlighet att simulera ett så komplext system som en ADPLL. Då tillverkningskostnaderna är höga och det är nödvändigt att kontrollera designens egenskaper och uppförande innan första prototyp, är det ett måste att finna alternativa lösningar. En lösning är då att använda en händelsestyrd simuleringsteknik som endast fokuserar på de händelser som sker vid respektive klockflank. Svårigheten ligger i att skapa en realistisk beteendemodell.</p><p>Projektet har fokuserat på att klara de krav på fasbrus som ställs på en WCDMA/HSDPA applikation. Den händelsestyrda modellen har skapats i Matlab på grund av dess stora flexibilitet under utveckling samt stora flora av analysverktyg. Den föreslagna modellen utgår från en tidigare publicerad modell som har utvecklats i de avseenden som varit intressanta för projektet. Modellens uppförande och noggrannhet har kunnat verifieras mot adekvat teori. Ett överskådligt användargränssnitt runt modellen möjliggör undersökning av olika parametrars påverkan på systemets prestanda.</p><p>Simuleringsresultaten av modellen fastställer hur olika parametrar påverkar ADPLL fasbruset. TDC-arkiteturen har stor påverkan på fasbruset och det är viktigt att använda hög upplösning på hela systemet för att förhindra att ”in-band” brusnivån ökar.</p><p>Med gott resultat har ett tidseffektivt simuleringsverktyg skapats och en kravspecifikation för de olika delblocken har presenterats.</p>
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Zhang, Chi. "System Level Modeling and Verification of All-digital Phase-locked Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175151.
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In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of local oscillators. Therefore, evaluating jitter/phase noise should be an essential part when designing wireless communication systems. Typically, LO is achieved by traditional analog PLL. These prototypes have several drawbacks including low integration, narrow bandwidth and high phase noise. With the development of digital techniques, approaches towards an All-digital Phase-Locked Loop have been forwarded against the traditional analogy type. The thesis mainly deals with the modeling and verification of an All-digital Phase-Locked Loop concerning its architecture, functionality and phase noise modeling and analysis. It starts with a comparison of current frequency synthesizers including direct analog/digital synthesis and indirect synthesis using PLL/ADPLL. The advantage and analogy of ADPLL versus traditional PLL in radio-frequency applications has been discussed. In order to gain overall understanding of ADPLL, a behavioral theory in both time and phase domain has been conducted in detail. Analysis shows that the restrictive factors of proposed ADPLL lie in TDC and DCO phase noise. It is also proved that the bandwidth and settling time of ADPLL is determined by proportional and integrating parameter of loop filter. Upon the completion of ADPLL theory analysis, a model based on simulink has been put forward. The phase noise level of TDC is specified and mode switch is implemented in order to improve the speed of ADPLL. The reason for choosing 2nd-order MASH-1-1 type ߢ modulator is briefly discussed. The phase noise of DCO is generated in time-domain using filtered Gaussian distribution and the free-running DCO achieves -20dB/dec spectrumfrom 10Hz to 500kHz. The results verified the feasibility of proposed ADPLL by achieving -50dBc/Hz in-band noise. Other results including howfractional precision, SDMclock and precision contributed to ADPLL phase noise has been presented. A tradeoff between phase noise shaping quality and settling time was evaluated. Ultimately, global parameters setup for the fulfillment of best performance is demonstrated.
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Kwong, Kelvin Kam Leung. "Implementation of DSP carrier recovery using all-digital phase-locked loop with vector rotation techniques for high speed 8-PSK modems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ36046.pdf.
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Wu, Hsu-Heng, and 吳旭珩. "Fractional Frequency Synthesizer Based on All Digital Phase-Locked Loop (ADPLL)." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/05658100710312003208.
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碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>90<br>The frequency synthesizer is used to generate more one frequency from an input reference source for the applications of accuracy clock requirement, such as clock generator and transceiver. With the rapidly growth of wireless communication system and the high performance in clock accuracy and stability, the frequency synthesizer have became more important.
In this thesis, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A novel phase frequency detector (PFD) is developed for replacing the two independent detections of phase and frequency to improve the ADPLL performance. A modified phase frequency acquisition (PFA) is involved by the modified binary search algorithm (MBSA) with initial half-step size to speed up the convergence in both phase and frequency. The digital control oscillator (DCO) is investigated to have good linearity to further the ADPLL stability. And, the dual modulus frequency divider with divided by four or by five is applied to perform the variable fraction and to increase the accuracy of frequency synthesizer. Experimental results of overall simulation are well matched to our specification.
The frequency synthesizer is implemented to be a chip with TSMC 0.35μm 1p4m CMOS technology. The chip area is 1.3 x 1.3 mm². With the TimeMill and PowerMill tools, we got the more encourage simulation results. The power consumption is only 15mW, and the jitter is 90ps at 300MHz, and the locked time is less then 20 reference cycles.
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Cheng, Chi-Cheng, and 鄭吉成. "The Analysis and Design of All-Digital Phase-Locked Loop (ADPLL)." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/76306613951012057301.
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碩士<br>國立交通大學<br>電子工程系<br>89<br>In this thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. By analyzing and designing each functional block in detail, we point out the important design parameters and discuss some design issues. The DCO consists of four paths, two modes, and a 5-bit controlled delay cell. The delay cell is a digitally controlled current-starved inverter. We adopt a D flip-flop as our PFD. The control unit performs two major functions, i.e., frequency search algorithm and phase tracking algorithm. Frequency search algorithm is similar to binary tree search. In addition, a phase tracking algorithm is proposed to reduce the accumulative phase error without slowing down the tracking speed. We implement the DCO by full custom design style while the other circuits are implemented by cell-based design style. In order to rapidly evaluate the structures and algorithms, we model the DCO in Verilog construct, and verify the ADPLL system by Verilog simulator. The ADPLL is designed in 0.35 um COMS SPQM technology. It needs about 50 reference cycles to make the accumulative phase error smaller than 10%. The DCO can generate frequency from 360 to 625 MHz, which is two times reference clock frequency.
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Hsu, Terng-Yin, and 許騰尹. "The Study of All Digital Phase-Locked Loop (ADPLL) and its Applications." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/08268281986945879028.
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博士<br>國立交通大學<br>電子工程系<br>88<br>All digital phase-locked loop (ADPLL) has a good capacity of portable issues to reduce system-turnaround time during process migration. In order to make system more efficient and robust, new algorithms for ADPLL have been developed in this thesis. By period estimation of phase error and 2-stage frequency search, the proposed ADPLL solution can achieve better performance, compared to available PLL’s solutions, in terms of lock-in time, pull-in range, and system stability. Two digital frequency synthesizer (DFS), and two clock recovery circuits are explored to meet different system specifications, namely basic DFS and time-to-digital (TDC) based DFS, ADPLL based clock recovery and mixed structure based clock recovery.
The basic DFS is a cost-efficient design for on-chip clock generator, which can provide any number of frequencies with 50ps output resolution. From tests, it can operate from 65 to 165MHz less than jitter at 3.3V. In order to make system-level integration more efficient in noisy environment, a new DFS based on TDC technique and mean process is proposed to improve system stability. For increasing frequency accuracy, a higher-resolution DCO is constructed by characteristic of transistor ─ body effect. As a result, the ratio of jitter per period can be improved more than 24dB and DCO output range can be from 50 to 185MHz under 250fs resolution.
ADPLL based design can recover NRZ clock within one data transition and has maximum “f/4” recovering capability with locking range of T/2~3T/2, where tinput is T input period. To operate at higher data rate, a mixed structure is proposed to combine with DFS and ADPLL. This clock recovery can use to recover 36~165Mbps NRZ signal with locking range, however it needs several valid transitions to lock signals.
Based on the proposed ADPLL concepts, two applications have been realized; one is 340~800MHz clock generator, and the other is DSSS baseband processor for wireless local area network (LAN). In order to achieve higher output frequency, a matrix-like DCO with parallel inverter bank is performed to make frequency range from 340 to 800 MHz with <64ps jitter at 3.3V. For DSSS baseband processor, all digital methodology can reduce design effort to make turnaround time more efficient. Based on the proposed methodology, a 4/2/1Mbps DSSS baseband processor with low-power variable-length Pointer Access Memory (PAM) based matched filter, all digital clock recovery, DQPSK demodulator, and on-chip central controller, has been designed and verified on silicon. Test results show that this DSSS baseband transceiver chip has power consumption of (<65mW @ 2.5V/100MHz)/(210mW @ 5V/100MHz).
Note that all above-mentioned approaches belong to portable and intellectual property (IP) based designs that can be developed by hardware description language (HDL) and synthesized for a target cell library. Each of them has been verified on silicon using an in-house 0.6um CMOS Single Poly Triple Metal (SPTM) cell library and 0.35um CMOS Double Poly Triple Metal (DPTM) cell library. As a result, the proposed ADPLL approaches are well-suited for system-level integration, especially in those digital communication application domains
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Sheng, Duo, and 盛鐸. "An All Digital Phase Locked-Loop (ADPLL) with Fast Lock-In Time--Analysis, Implementation and Application." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/96233833440043668566.
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碩士<br>國立中正大學<br>電機工程研究所<br>87<br>In this thesis, a new all digital phase-locked loop (ADPLL) is proposed. The architecture of proposed ADPLL is based on [12], but some modifications are made. The phase-lock process is separated into frequency prediction, frequency comparison and phase detection that reduce phase lock_in cycle significantly. By using our lock_in algorithm, our ADPLL can accomplish phase lock process within 25 reference clock cycles. A digitally-controlled oscillator (DCO) is the core of the ADPLL. The DCO we used is a 3-stage ring oscillator with a 7-bit binary weighted control mechanism, and operating linear with DCO control word. The operating frequency range of new ADPLL is 203MHz - 493MHz and jitter is 250ps (at 235MHz). The whole chip is fabricated in 0.35um CMOS 1P4M process. The transistor number is 2984 and core size is 338um * 362um.
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Yu-Jung, Chen, and 陳育融. "A novel All Digital Phase Locked Loop (ADPLL) with ultra fast frequency lock and high oscillation frequency." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/18014911762767217144.
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碩士<br>淡江大學<br>電機工程學系<br>89<br>This thesis proposed a novel architecture for All Digital Phase-Locked Loop . As we know that a PLL-based circuit has been widely used in many applications such as frequency synthesizer , data recovery circuit , and delay de-skewing . Above circuits are usually used in many digital or communication systems . In the traditional Phase Locked Loop scheme , the low-pass filter (LPF) is a important component because of it’s affection of system stability . But the low-pass filter is consist of resistors and capacitors that in the VLSI technology have great variation problem .Most all-digital phase-locked loops do not provide frequency synthesis ; rather ,they (like 74ACT297) need a high-frequency clock for digital control oscillator . Now , we proposed a novel architecture for All Digital Phase-Locked Loop to solve the problems in traditional ADPLL and traditional HDPLL (PLL) . The fundamental concept of our ADPLL is based on ADPLL proposed by Motorola in 1995 . The phase-lock procedures for our ADPLL also have four modes : frequency acquisition , phase acquisition , and frequency and phase maintenance . In the frequency acquisition mode , a modified binary search is used to capture the right frequency . In the phase acquisition , our algorithm is the binary search instate of bit-shifted method . Finally in the frequency and phase maintenance mode , the frequency maintenance and phase maintenance are proposed concurrently . In our novel scheme of ADPLL , it can efficiently decrease the frequency acquiring time and increase the frequency of oscillator . The circuit is designed by TSMC’s 0.35um 1P4M CMOS process . The system operate in the 680MHz and 820MHz ,and operate at 16x the reference clock . Our lock time is 20 cycles of input clock cycles .
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Tsao, Ya-lan, and 曹亞嵐. "All Digital Phase-Locked Loop." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/33585222011275948297.
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Wang, You-Jen, and 王佑仁. "Design and Application of All-Digital Delay-Locked Loop and All-Digital Phase-Locked Loop." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/29732818975573400808.
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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>This thesis describes digital implementations and applications of analog circuits for delay-locked loop (DLL) and phase-locked loop (PLL). Compared with analog DLLs and PLLs, the all-digital DLLs and all-digital PLLs have the benefits such as easy process migration, no passive loop filter needed, and fast locked time. Therefore, digital equivalent implementations of analog circuits are more popular, such as delay-locked loop (DLL), phase-locked loop (PLL), clock and data recovery circuit (CDR), and frequency synthesizer.
There are four works in this thesis: all-digital DLL, PLL, CDR and frequency synthesizer. First, an all-digital DLL with adjustable duty cycles is proposed. The phase and duty cycle of output clock are fast adjusted by the time-to-digital conversion result of the input period. Therefore, the phase alignment and the duty cycle of output clock are assured in 10 cycles of input clock.
Second, a 15KHz-1.39GHz all-digital PLL with frequency multiplication by 1 to 32768 is presented. The frequency counting and binary searching methods are applied to reduce the locked time. And a programmable divider is proposed for wide frequency range applications. Furthermore, the timing resolution of the proposed digitally-controlled oscillator (DCO) is improved to 0.013ps by the capacitance difference among the varactors.
Third, a 6.34Mbps-1.5Gbps all-digital wide-range CDR circuit is presented. The proposed frequency-searching algorithm reduces the frequency locked time and eliminates the harmonic locking problem over wide-range data rates. The CDR circuit has been fabricated in 90nm CMOS process, and parts of this circuit is digital synthesized and reduce the area to 0.00368mm2, smaller than previous publish works.
Finally, an all-digital frequency synthesizer with cancellation, calibration, and correction loops is presented. The proposed cancellation, calibration and correction loops reduce the fractional spur and phase noise of output clock. And the cancellation, calibration and correction loops are digital synthesized to reduce silicon area. Furthermore, the frequency resolution of the proposed DCO is improved by adjusting the difference of control voltage between the two varactors with small capacitance difference. And a high-gain time amplifier is proposed to reduce the offset of D flip-flops.
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Chin, Yu-Tung, and 秦語彤. "Multi-Function All-Digital Phase-Locked Loop." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/15098274862183007233.
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碩士<br>國立交通大學<br>電子研究所<br>105<br>An ADPLL with spread spectrum circuit, fractional-N circuit, spur reduction circuit, and higher order loop filter is presented. By modulating the output frequency with the triangular profile generator, the simulated EMI reduction can be 30dB. The reference spurs which may mix the signals from adjacent channels can be dealt with by using the spur reduction circuit. When the channel spacing is small, the fractional-N circuit can be utilized for its higher frequency resolution. In the presence of input noise, the ADPLL can select the whole loop as a higher order by turning on the IIR filter to attenuate input noise. Moreover, the phenomenon that spurious tone is getting closer to main tone at higher-order ADPLL, will be analyzed in this thesis.
The chip has been designed and implemented in TSMC 40nm GP 1P9M CMOS process technology. In the proposed ADPLL, all logic cells except the DCO and the LDO are using standard cell, therefore, it can be easily migrated from one technology to another. The total area of the ADPLL core is 0.0257mm2. The simulated RMS jitter from a 5.376GHz output frequency is 0.05% UI. The total power consumption is 5.36mW at 5.376GHz output frequency and 84MHz reference clock.
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You, Rung-Hau, and 游榮豪. "High Speed All Digital Phase-Locked Loop." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/37411327694764982533.
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碩士<br>國立中興大學<br>電機工程學系<br>89<br>Abstract
This thesis describes the architecture and design of a high speed all digital phase-locked loop (ADPLL), which uses sample and encode method to decide DCO operation model and frequency region of the input signal in 16 levels. The method can also modify part of algorithm and DCO design. The proposed ADPLL design has characteristics of fast search speed, short frequency locking time, small phase jitter and high operating frequency. This architecture comprises digital controlled oscillator (DCO), frequency detector (FD), phase detector (PD), UP/DN counter, control unit, start circuit, sample circuit, encoder, bit indicator, divider, phase chooser. The phase-lock procedures for this proposed ADPLL are frequency acquisition, phase acquisition, frequency maintenance and phase maintenance. The phase-lock procedures control unit to execute binary search algorithm, which changes UP/DN counter gain and controls the DCO output. When the ADPLL output is in phase with reference clock the phase-lock procedures are accomplished.
The proposed ADPLL is simulated and implemented by the TSMC 0.35μm 1P4M technology. The supply voltage is 3V. The simulation results show that when DCO operates at 1.25GHz or 2.5GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 34 reference clock cycles (algorithm) or 1us (simulation). The lock-in range is 2.3GHz to 2.6GHz in the mode 0 and 0.8GHz to 1.3GHz in the mode 1. The power consumption is 106.1mW at 1.25GHz and 91.46mW at 2.5GHz.
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Huang, Zheng Hui, and 黃正輝. "Phase-Compensated Skill of All Digital Phase-Locked Loop." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/55349637232260385154.
Full textAbstract:
碩士<br>長庚大學<br>電機工程學系<br>98<br>In the transmission communication field, clock and data recovery circuit is widely used. Among it, in recent years, the development of all-digital clock and data recovery circuit is the mainstream. This paper mainly describes the circuit used in the all-digital clock and data recovery circuit based on phase-locked loop. First, all-digital phase-locked loop will provide locked frequency, let all-digital CDR circuit to recover clock and data, so it can reduce the locking time of all-digital clock and data recovery circuit. However, all-digital PLL has an inherent shortcoming, that is, the circuit needs to use a digital controlled oscillator, resulting in the digital control code of a digital controlled oscillator will be locked in a range. And the signal provided to the all-digital CDR circuit may result in miscarriage of justice. Therefore, this paper proposes to phase compensation correction technology to offset the beating of a digital control code to achieve the output frequency steady and correction.
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Hsu, Sheng-Feng, and 徐聖峰. "DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/48811008021719126435.
Full textAbstract:
碩士<br>大同大學<br>電機工程學系(所)<br>97<br>A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a -chip (SoC) environment is challenging. In addition, the analog PLL is sensitive to process parameters. It is too hard to use the same analog PLL design in different process. On the other hand, The ADPLL has no off-chip components. it is made from standard cells found in most digital standard cell libraries. Therefore, The ADPLL has the higher immunity for supply noise, and temperature variation, and process.
In this thesis, The ADPLL consists of a digital phase frequency detector, a digital loop filter, a digital controlled ring oscillator and frequency divider. This thesis proposed a new architecture of Time-to-Digital converter to get digital phase error. The simulation results show that when reference clock is 20 MHz. The locking time is 6.674us (simulation). Working frequency ranges for this ADPLL is about 152~581MHz. The ADPLL are developed by VHDL (VHSIC Hardware Description Language), and they are simulated with Xilinx Spartan3E XC3S1600E-5FG320 FPGA by ModelSim 6.1i and Xilinx ISE 8.2i to justify the feasibility of the proposed ADPLL .
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Huang, Wen-Jiun, and 黃文駿. "DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/09055301273166765638.
Full textAbstract:
碩士<br>大同大學<br>電機工程學系(所)<br>99<br>In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with only four reference clock. A ring-delay-line consisting of 32 stages makes it possible for both the frequency detector and DCO to have a common time base, resulting in this unique clock generator. The pulse delay circuit is connected in a ring shape with 32 inverters ( inverters).With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. The generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock for a high-speed response. The frequency synthesizers are developed by Verilog, and they are simulated by Modelsim to justify the feasibility of the proposed frequency synthesizer.
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Chang, Hung-ju, and 張弘儒. "DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/24031698315028043856.
Full textAbstract:
碩士<br>大同大學<br>電機工程學系(所)<br>100<br>In this thesis, we designed an all digital phase locked loop (ADPLL). Its structures included phase frequency detectors, time to digital converter, loop filter, digital controlled oscillators, buffer and divider. This thesis not only proposed a new modified time to digital converter which can transform all the impulse into a digital string signal but also modified the circuits of buffer which make all the circuits work well and without interfering of signal delay. Finally, we know that the ranges of locking frequency error are -0.68%~1.62%. The output frequency ranges are 152~581MHz. In this thesis, we use Xilinx Spartan3E XC3S1600E-5FG320, MODELSIM PE 10.1a and ISE 10.1 to check new modified time to digital converter, BUF and all other circuits.
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Chen, I.-Fong, and 陳易楓. "All-digital Clock and Data Recovery and All-digital Phase-locked Loop." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/72656359516188540808.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>In recent years, the orientation of the fabrication process is to shrink the scaling of the transistor. Scaling down the transistor will have less power consumption and faster operation frequency to design circuits. However, it has extra drawbacks for analog circuits, but it is more suitable for digital circuits. Therefore, digital equivalent implementations of analog circuits are more popular, such as the phase-locked loop and the clock and data recovery.
In this thesis, a 1.25 Gbps all-digital clock and data recovery is proposed. The clock frequency of the accumulator is too slow. The proposed pre-accumulator and the path with the scaler (the first integral path) are used to slow down the clock frequency of the accumulator and reduce the loop latency. By reducing the loop latency, the smaller is used to have low jitter performance without sacrificing the phase margin. Compared with the loop without the first integral path, it also increases the damping factor and the bandwidth. The jitter of the proposed 1.25Gbps all-digital clock and data recovery is only 51.1 ps and its bit error rate is below 10-12. The power consumption is 23.4 mW and the core area is 0.423mm2.
In this thesis, a 1.25 GHz all-digital phase-locked loop is proposed. The bang-bang type all-digital phase-locked loop needs long frequency acquisition time because the phase/frequency detector only has binary outputs, and. The proposed algorithm can effectively reduce the frequency acquisition time. The supply noise toward the DCO has severely impact in the all-digital PLL. Therefore, the proposed bandwidth calibration circuit decides the bandwidth which make the all-digital PLL have the lowest jitter by using the timing window measuring the jitter to change the bandwidth. The jitter of the proposed all-digital phase-locked loop is 38.9 ps and the phase noise is -103.22dBc/Hz at 1MHz offset. Its power consumption is 9 mW and the core area is 0.348mm2.
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Kung, Fan-Hsiang, and 孔繁祥. "All Digital Phase-Locked Loop With Programmable Phase Injection Locking." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51857591927968419002.
Full textAbstract:
碩士<br>國立交通大學<br>電機與控制工程系所<br>97<br>This thesis propose an all digital phase-locked loop with programmable phase injection locking mechanics. The phase injection to the digitally controlled oscillator can reduce the phase noise. Using programmable phase injection strength can achieve optimum output performance in different environment. In order to enhance the resolution of digitally controlled oscillator , we use sigma-delta modulator to achieve fractional control on the LSB. This method will enhance resolution of the digitally controlled oscillator.
The proposed ADPLL is implemented in TSMC 0.13 um 1P6M RF technology. The simulation results show that the output clock has a peak-to-peak jitter of 17ps, the power dissipation is 22mW, the output frequency is 1.25GHZ
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Jhu, Yong-Jhen, and 朱永楨. "A 4-GHz 10-Phase All Digital Phase-Locked Loop." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36702875300905409844.
Full textAbstract:
碩士<br>國立中央大學<br>電機工程研究所<br>100<br>A 4-GHz 10-phase all digital phase-locked loop (ADPLL) is proposed for system-on-chip (SoC) systems. The proposed multiphase digital controlled oscillator (MP-DCO) adopts the tri-state inverter loop scheme to obtain the higher operating frequency and wide operation range. The MP-DCO outputs are used to be Time-to-digital Converter (TDC) sampled clock and sample the time difference. Therefore, the reused MP-DCO output can reduce the area cost of the TDC. Time amplifier (TA) can extend the timing resolution of the TDC. The frequency acquisition can achieve the fast locking time using frequency detector (FD) and multi-band operation range of the MP-DCO. Thus, this clock generator is suitable for portable products and mobile applications.
The experimental chip was fabricated by TSMC 90 nm 1P9M CMOS process. The measurement results show that the operation range is from 3 GHz to 4.2 GHz, and the power consumption is 52 mW at 4 GHz. The peak-to-peak jitter and RMS jitter are 12.14 ps and 1.44 ps at 4 GHz, respectively. The whole chip area is 510 × 590 um2, and the core area is 140 × 220 um2.
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Yang, Yu-Sheng, and 楊于昇. "A 0.5V Low Power All-Digital Phase-Locked Loop." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/77999168478677744569.
Full textAbstract:
碩士<br>國立交通大學<br>電控工程研究所<br>99<br>In recent years, low power designs for portable devices become popular. Many consumer electronics are asked to consume as less power as possible to extend the battery lifetime. Owing to the progress in CMOS technology, the threshold voltage of the transistor keeps degrading. But the degrading of the system supply voltage is much faster. Under the low power supply environment, the gate-source voltage decreases which leads to the decay of the driving ability. Hence the operation frequency of digital circuit is limited. Besides, the system suffers from process variation badly when the supply voltage is near the threshold voltage of the transistors. For the ADPLL systems, low power supply decreases the operation frequency of the oscillator. So we propose a bootstrapped delay cell for the digitally-controlled oscillator in ADPLLs. With the bootstrapped cell, the output swing of the oscillator is –VDD to 2VDD. This enlarged swing not only enhances the driving ability but keeps the transistors operate at super VTH region. The circuit then suffers less from the process variation compared to the oscillators composed of the traditional inverters. Finally, our ADPLL is fabricated in 90nm CMOS technology. The core area is 0.057 mm2. Under supply voltage of 0.5V, the locking range is 240 MHz to 480 MHz. The peak-to-peak jitter is measured 69.1 ps while operating at 400 MHz, and the power consumption is 70uW.
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Chen, Jyi-Chang, and 陳吉昌. "Investigation and Desgin of All Digital Phase Locked Loop." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/40526318520931193943.
Full textAbstract:
碩士<br>國立交通大學<br>電子工程系<br>90<br>In this thesis, we present the design of an all digital phase locked loop (ADPLL), which consists of a phase detector (PD), a frequency detector (FD), a digitally controlled oscillator (DCO), a control unit and some auxiliary logic circuits. A new phase tracking algorithm is proposed to reduce the accumulative phase error without slowing down the tracking speed, and a modify frequency detector circuit which can cancel the internal error delay. We analyze and design each functional block in detail, and point out the important design parameters and discuss some design issues. In our design, the DCO consists of three paths, three modes, and a 5 bit controlled delay cell. The control unit performs two major functions, i.e., frequency search algorithm and phase tracking algorithm. We use two D-type flip-flops and some logic circuits for frequency detector to detect the difference of frequency in searching frequency. At the same time, we use two parallel D-type flip-flops for phase detector to track phase. Finally, we use Hspice and Verilog code to verify the overall ADPLL system
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Ciou, Jyun-Han, and 邱俊翰. "Multiphase All Digital Phase Locked Loop with Monitor Counter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/32781326096008575730.
Full textAbstract:
碩士<br>國立高雄第一科技大學<br>電腦與通訊工程研究所<br>99<br>Traditionally, the frequency synthesizer is based on the phase locked loop (PLL). In order to achieve chip synchronization for the requirements of the operating frequency, the PLL is increasingly important. The multi-phase voltage controlled oscillator generates the same frequency with different output phases.
This paper proposes a NAND based architecture for the multi-phase digital control oscillators (DCO). In addition, we also propose a multi-phase ADPLL with monitor counter. The output phases of digital controlled oscillator are eight and the control word is 12-bit. The 12-bit control word which contains a 6-bit digital-to-voltage converter (DVC), and the 6-bit self controlled word. The chip has been implemented in TSMC 0.18um process. It uses 28Pin the ESD protection circuit. The circuit area is 195 * 131 um 2 and the measured frequency range of 104 ~ 464 MHz. The Pk-to-Pk jitter is 64.4 ps and RMS jitter is 10.73 ps at 464MHz.
In addition, I accomplished a multi-phase ADPLL with monitor counter. The circuit uses a control unit, a successive approximation register (SAR), a monitor counter circuit and multiphase digital control oscillator to complete the all-digital phase locked loop. The circuit can synthesize a wide range frequency. When the PLL is locked, the monitor counter circuit keeps track of the status of the entire circuit to achieve a stable output frequency. The chip has been implemented in TSMC 0.18um process, use the 28Pin the ESD protection circuit. The circuit area is 982 * 902 um 2. The Pk-to-Pk jitter is 161 ps and RMS jitter is 27 ps at 307 MHz.
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Huang, Tien-yu, and 黃天佑. "ALL DIGITAL PHASE-LOCKED LOOP WITH ADAPTIVE SEARCHING ALGORITHM." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/92498336738843568554.
Full textAbstract:
碩士<br>大同大學<br>通訊工程研究所<br>98<br>Due to the disadvantages of the traditional analog phase-locked loop (APLL) over source stability, noise interference and design difficulty, the all digital phase-locked loop (ADPLL) can provide better performance than the traditional PLL. The ADPLL is programmable and portable over design that it can efficiently reduce the difficulties in other design process.
This thesis implements an ADPLL with a searching algorithm in its control unit that can perform in high frequency resolutions, and the algorithm provides fast tracking search step to further reduce the lock in time. The ADPLL is simulated with the MATLAB Simulink, and the simulation result shows that when the DCO operating in 0.8GHz-1.4GHz, the lock in time of the reference clock for 134MHz is 1.5μs; when the DCO operating in 1.2GHz-4.35GHz, the lock in time of the reference clock for 300MHz is 0.9μs.
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Lee, Yi-Herng, and 李宜衡. "Adaptive Bandwidth All-Digital Phase-Locked Loop chip design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/37929583369693061704.
Full textAbstract:
碩士<br>元智大學<br>通訊工程學系<br>97<br>Phase-locked loop design in the adaptive bandwidth, for different operating frequency, enables to change the circuit characteristics to achieve the optimal performance. However, the traditional Analog Adaptive-Bandwidth Phase-locked loop, it is challenging to control the parameter. Moreover, the analog circuit design has the higher design complexity and the higher production cost. Hence, we proposed a All-Digital Adaptive-Bandwidth Phase-locked loop, and we will also design the new All-Digital loop filter to reduce the circuit complexity.
Pre-layout and post-layout simulation results based on the TSMC 0.18um cell-based implementation are illustrated to validate the design, which can be used for TSMC 0.18 um realization.
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Huang, Tzu-Chi, and 黃梓期. "All Digital Phase-Locked Loop Using Active Inductor Oscillator." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/40441356915930297288.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>97<br>Phase-locked loop (PLL) is a widely used circuit for clock generation and RF front-end systems. All digital designs have been researched in recent years because of the high area efficiency, adjusting to different process and low noise. In this paper, an all-digital phase-locked loop (ADPLL) using active inductor digital controlled oscillator is presented. The digital controlled active inductor offers a wide operating frequency range, good signal quality and small chip area. The novel phase lock in algorithm has the characteristics of high jitter performance, high frequency accuracy, low circuit complexity and easy design. The ADPLL implemented in a 0.18um single-poly six-metal (1P6M) technology can operate from 318MHz to 458MHz and achieve frequency acquisition within 74 reference clock cycles. The chip size is 760�e740 um2 (core: 390�e390 um2), and the power consumption is 5.4mW at 416MHz.
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Chen, Chun-Ming, and 陳俊銘. "A 1.25GHz All Digital Phase-Locked Loop with 8-phase Output." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/vk5g3b.
Full textAbstract:
碩士<br>國立交通大學<br>電機與控制工程系所<br>94<br>The increasing demand for the data bandwidth in network has driven the development of high-speed serial link technology. The high speed serial links have been applied in optical communication, USB, IEEE-1394. This thesis develops a transmitter front-end circuit design in 0.18um CMOS process technologies. The objective goal of this research is to realize 1.25Gbps an all-digital serial link transmitter.
There are two major topics in this thesis. First, we compare and analyze all types of serializer. Base on the comparison results and IEEE802.3ah specification, we implement a 10 to 1 serializer in all-digital approach. Besides, we integrate this serializer, PLL, and output driver together to become a complete serial link data transmitter. It has been implemented using 0.18um 1P6M TSMC CMOS technology. The measured jitter is about 66ps and can be capable of operate 1.25Gbps data rate. Chip size is about 1900*990um2.
The second research topic is a 1.25GHz all digital phase-locked loop. We propose a high resolution digitally-controlled oscillator with multi-phase output. Functional verification of the ADPLL is performed by MATLAB simulink and gets optimal DCO resolution corresponding to output clock jitter acceptable. It will be implemented using 0.18um 1P6M TSMC CMOS technology. The output clock jitter is about 104ps after post-layout simulation, and power consumption is about 24.49mW. Overall chip size is about 880*730um2 .
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Chung, Yu-Ming, and 張郁敏. "An All-Digital Phase-Locked Loop for Digital Power Management Circuits." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/09774111174976454112.
Full textAbstract:
碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>The phase-locked-loop (PLL) is widely used in different applications, such as frequency synthesis, clock/data recovery, and clock de-skewing. Presently, the most designs of the PLL are digital PLLs which have analog loop filter and oscillator in their circuits, but with the advances in integrated circuit (IC) technology, the fabrication processes is more and more suitable for digital designs. A digital design is scalability and easy redesign with process changes or shrinks. Moreover designing an all-digital PLL can inherent noise immunity of digital circuits.
This paper presents an All-Digital Phase-Locked Loop (ADPLL) which inherits the frequency response and stability characteristics of the analog prototype PLL. Replacing the conventional RC loop filter with an all digital loop filter can decrease the layout area and eliminate the requirements of resistor and capacitor. Moreover, the analog voltage-control oscillator (VCO) is replaced by the digital control oscillator (DCO) in order to enhance the noise immunity. Therefore, this digital architecture can be easily redesign by analyzing the frequency response and stability.
The die area of the proposed chip is 0.759 x 0.954 mm2. The chip was implemented by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm 1P6M CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V process, patronized by National Chip Implementation Center (CIC). The measured results verify the effectiveness of this architecture.
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Hsu, Li-Fan, and 徐立凡. "ALL DIGITAL PHASE-LOCKED LOOP WITH HIGH RESOLUTION DIGITAL CONTROLLED OSCILLATOR." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/03532117016625588613.
Full textAbstract:
碩士<br>大同大學<br>通訊工程研究所<br>98<br>In this thesis, we implement an all digital phase locked loop (ADPLL) with high resolution digital controlled oscillator. We use time to digital converter to quantize phase error and use a high resolution ring oscillator to be the digital controlled oscillator in the circuit. Working frequency ranges for this ADPLL is about 212~366MHz. When reference signal is 5MHz and a multiplication factor of 64, the lock-in time is about 3.5 s. The feasibility and performance of the ADPLL is verified with the MATLAB Simulink.
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Su, Ming-Chiuan, and 蘇明銓. "All Digital Phase-Locked Loop for Spread-Spectrum Clock Generator." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/43743861319797682304.
Full textAbstract:
碩士<br>國立交通大學<br>電子工程系所<br>98<br>Abstract
As SOC(System On Chip) works with increasing internal reference clocks, the spread-spectrum clocking technique is used to mitigate EMI(Electro-Magnetic Interference) effect. Conventional analog PLLs are likely to be affected by PVT (process/voltage/temperature) variations. Hence, when using deep-submicron CMOS process, PLLs are prone to all-digital design.
All-digital PLL consists of bang-bang PFD, accumulator-based digital loop filter, differential DCO and divider. Bang-bang PFD generates phase compare signals to control accumulator-based digital loop filter. Then, DLF outputs coarse-tune and fine-tune control code to change differential DCO’s frequency. Using ΣΔmodulator to further control DCO enhances ADPLL’s frequency resolution. A low-jitter ADPLL is desired under spread-spectrum clocking application.
Spread-spectrum technique is to modulate clock’s center frequency, and the spectrum of the clock is spread over a broader range. Therefore, clock’s peak energy is reduced and it also mitigates EMI effect. Based on an ADPLL, the proposed spread spectrum clock generator (SSCG) is fulfilled usingΣΔmodulator and multiple phases. This SSCG uses Serial-ATA 6Gbps and USB 3.0 5Gbps specifications as reference.
For different system requirements for low-power or low-jitter, the SSCG can do modulation on 10 or 20 phases. The thesis proposes novel ADPLL and SSCG architecture and the circuits are implemented with TSMC 65nm 1P9M CMOS process.
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Yang, E.-Ing, and 楊怡英. "The Implementation and Analysis of All Digital Phase-Locked Loop." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/65915664750386172130.
Full textAbstract:
碩士<br>國立中央大學<br>電機工程學系<br>85<br>In this thesis, an all digital phase-locked loop(ADPLL) is
proposed. The architecture of the proposed ADPLL is based on the
ADPLL proposed by Motorola in 1995, but some modifications are
made. A digitally controlled oscillator form the core of the
ADPLL. The DCO we used is a 3-stage ring oscillator with a
14-bit binary weighted control mechanism, and the operating
frequency range of the DCO is from 280MHz~500MHz. Because we
increase the bits of control word significantly, the phase
jitters of output frequency is reduced. The phase-lock process
is seperarted into frequency acquisition and phase acquisition
that reduce the phase lock time significantly. By using the
modified binary search algorithm, the ADPLL_MB can accomplish
phase lock process within 34 input clock cycles. The whole chip
is fabricated in a 0.6um SPDM process. The chip complexity is
about 4550 transistors and core chip size is about 1.0mm*1.2mm.
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Chao, Kuan-Chieh, and 趙冠傑. "A Study of High-Resolution All-Digital Phase-Locked Loop." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10104992573991641021.
Full textAbstract:
碩士<br>中華大學<br>電機工程學系(所)<br>97<br>The quality of parallel synchronization signal in communication systems is very important. Therefore, Phase-Locked Loops (PLLs) are common circuits of modern circuit design. Traditionally, a Phase-Locked Loop is making up of an analog circuit. The analog-PLL (APLL) has good quality of phase noise and loop bandwidth. But, the APLL is sensitive to process, supply voltage and temperature. The current trend is towards All-Digital Phase-Locked Loop (ADPLL).
In this study, we proposed an ADPLL. The minimum resolution of Digital Controlled Oscillator (DCO) is the major concern of this thesis. The proposed DCO used AOI/OAI standard cells to form as digitally controlled varactor (DCV). Base on the technology of DCV, the minimum resolution of DCO is 10fs. By Spice simulations, the operation range of this DCO is between 0.66MHz and 530MHz.
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Hsieh, Cheng-Che, and 謝承哲. "DESIGN AND IMPLEMENTATION OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/01242378694973792971.
Full textAbstract:
碩士<br>大同大學<br>電機工程學系(所)<br>98<br>A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a-chip (SoC) environment is challenging. In addition, the analog PLL is sensitive to process parameters. It is too hard to use the same analog PLL design in different process. On the other hand, the ADPLL has no off-chip components. It is made from standard cells found in most digital standard cell libraries. Therefore, the ADPLL has the higher immunity for power supply noise, temperature, and process variation.
In this thesis, the ADPLL consists of a digital phase frequency detector, a digital loop filter, a digital controlled oscillator and frequency divider. This thesis proposed a new architecture of digital controlled oscillator has good performance in terms of fine resolution. The ADPLL are developed by Verilog, and they are simulated by ModelSim 6.0i to justify the feasibility of the proposed ADPLL .
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Wang, Kai-Pin, and 王凱平. "Investigation and Analysis of an All Digital Phase-Locked Loop." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/62181159818869755155.
Full textAbstract:
碩士<br>元智大學<br>通訊工程學系<br>92<br>The communication industry develops rapidly in recent years,making its related components also seemed to be the importance more.Among them,phase-locked loop（PLL）plays the most important role,the application of it's architecture is also too numerous to count up.Because of this,how to promote the PLL integrated performance becomes a vary important topic.
In this thesis,a novel all digital phase-locked loop（ADPLL）based on the 74HC/HCT297 single-chip ADPLL.Two values of the K for the K counter are used and implemented.With a dynamical selection of the counter modulus,the counter can be adapted to the real-time phase error and speed the locking procedure.In addition,the locking range of the ADPLL is enlarged with the new structure.The Verilog is used to realize the new structure and corresponding behavior is analyzed in the context.Simulation results are presented to illustrate the increase of locking time of the new ADPLL structure.
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Jan, Wei-Chan, and 鄭為全. "Analysis and Design of the All-Digital Phase-Locked Loop." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/19532210035147422505.
Full textAbstract:
碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>Recently, phase-locked loop (PLL) has been widely used in the
fields ofcomputers and communications. A PLL-based circuit can
synchronize an outputsignal whose frequency is adjustable to
satisfy the specification requirementswith a reference clock in
frequency as well as in phase. In the traditional PLL, a low-
pass filter (LPF) consisting of resistors andcapacitors is
utilized to get rid of the high frequency signal generated by
itscharge-pump circuit. However, resistors and capacitors in the
integrated circuits have great variation in their physical
values. Hence, an all-digital phase-locked loop (ADPLL) scheme
is proposed and designed to conquer the mentioned drawbacks of
the traditional PLL. The charge-pump circuit as well as LPF is
not necessary in the ADPLL. Moreover, the digital nature of the
ADPLL makes it possible to achieve very fast lock time
ascompared to the traditional PLL. This paper reports the
design of an ADPLL-based programmable clock generatorthat has
been implemented with integrated circuits. This ADPLL circuit
has a wide output frequency range over 8MHz to 150MHz.
Experimental results showthat its output signal jitter is less
than 150ps at 80MHz, with lock time lessthan 1us at its
reference clock of 30MHz.
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Guo, Bo-Cheng, and 郭博誠. "An All-Digital Phase-locked Loop Based on Bang-bang Phase Detector." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/65697275653465004904.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>99<br>As the progress of CMOS technology, phase-locked loop has been widely implemented in many applications, such as mems, memory integrated chip and communication systems. It is used to generate the clock frequency and phase in a system. The traditional structure of a phase-locked loop could be classified into two kinds. One is analog phase-locked loop (APLL), the other is all-digital phase-locked loop (ADPLL). Although the former is usually adopted by conventional ic designer, ADPLL is more suggested in recently years because of its good tolerance to PVT variations and less sensitive to supply noise. Furthermore, ADPLL can be portable to new technology. It can reduce the development time for system-on-chip applications.
This thesis proposed an ADPLL based on bang-bang phase detector with a frequency detector. The chip is fabricated in TSMC 0.18μm CMOS technology with an area of 1000 μm x 750 μm. Under 1.8V supply, the power dissipation is 43mW with output buffer. The measured output clock’s rms and peak-to-peak jitter are 7ps and 37ps at 2.4GHz.
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Chang, Chia-Chen, and 張家甄. "Fast Locking All-Digital Phase-Locked Loop with Higher-Order Filter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/rfcq33.
Full textAbstract:
碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>104<br>A stable clock signal plays an important role in a system. As the speed of internal reference clock in the System-on-Chip (SOC) increased and the scaling down of the process, the effect of noise is more significant to the SOC. Therefore, a fast locking all-digital phase-locked loop (ADPLL) with higher-order filter is proposed in the thesis. At the frequency acquisition mode, the locking time is 5 cycles of the reference clock period by using the method of linear interpolation. On the other hand, at the phase tracking mode, the proposed ADPLL can select the loop filter as a first-order or a third-order with higher filtering capability. The ADPLL can attenuate the noise by using the higher-order filter.
The chip has been designed and implemented in TSMC 40nm GP 1P10M CMOS process technology. In the proposed ADPLL, all logic cells except the DCO and the divided-by 2 circuit of duty-cycle correction circuit are from standard cell library, thus, it can be easily retargeted to others CMOS technology because of the cell-based nature. The total area of the ADPLL core is 0.0198mm2. The total locking time is 72 cycles of the reference clock. The total power consumption is 4.86mW at 5GHz output frequency and 96MHz reference clock. The power delay product is 0.972 mW/GHz.
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Xie, Shan-yang, and 謝善揚. "Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/x7jt7e.
Full textAbstract:
碩士<br>國立中山大學<br>資訊工程學系研究所<br>106<br>This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as some control units.
This all-digital phase-locked loop has the following characteristics:
1. The digitally controlled oscillator uses the low power schmitt trigger inverter as a delay element to reduce power consumption and reduce output jitter.
2. Resolution is divided into 6-bit coarse-tuning and 5-bit fine-tuning , coarse delay time range covers the fine delay time, through the delay component to give the least significant bit resolution
3. The use of improved successive approximation register , can solve the process, voltage and temperature conditions can not continue to track the lock caused by all-digital phase-locked loop deadlock problem, so that the entire phase-locked loop after the lock can continue to do the circuit Locked after tracking.
The supply voltage is 1 V. The reference frequency is 20 MHz. The output frequency can achieve from 250 MHz to 1 GHz. The power consumption is 0.438 mW at 1GHz. The simulation of the jitter is 26.7 ps at 1 GHz.
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Su, Hung-Lung, and 蘇鴻隆. "The Implementation and Analysis of an All-digital Phase-Locked Loop." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/y84b7d.
Full textAbstract:
碩士<br>朝陽科技大學<br>資訊工程系碩士班<br>94<br>Abstract
An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in deep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time.
A DCO is implemented for ADPLL applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the same number of ring oscillator stages. Simulation results are presented to evaluate the performance of the DCO.
This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity PFD. Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications.
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Sung, Chuan-Yuan, and 宋權原. "USE FPGA TO DESIGN THE ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/47666718473594873911.
Full textAbstract:
碩士<br>大同大學<br>電機工程學系(所)<br>98<br>The phase- locked loop (PLL) has been widely used in different field such as computer, consumer electronics, and communication , etc. We have to overcome many complicated problems to integrate a analog PLL into the single chip system full of noise. The sensitive process change of analog PLL would result in much noise and other problems. Therefore, we have to redesign the parameters of analog components in different processer and it usually takes a lot of time. In order to solve all the issues, all-digital design is option. Because all-digital circuit means that we use the components of a digital standard cell library to design the circuit only, there is no external unit in the structure of the circuit. Thus, an all-digital PLL has high immunity to temperature change and noise during the process.
In this thesis, the structure of an all-digital PLL contains phase frequency detectors, time to digital converters, control units, digitally controlled ring oscillators and frequency dividers. We use the time to digital converter with a new kind of structure to help get the quantitative phase error. Form the result of circuit simulation, with several different set of reference signal input, the system is converged and locked. The working frequency range for this ADPLL is about 152~574MHz. Finally, we use the Xilinx Spartan3E XC3S1600E-5FG320 FPGA with ModelSim 6.1f and ISE 9.1i to test all the feasibility and functionality of the circuit.
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Liu, Ta-Wei, and 劉大維. "Design and Analysis of a Novel All Digital Phase-Locked Loop." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/51110173758933390178.
Full textAbstract:
碩士<br>淡江大學<br>電機工程學系<br>90<br>Recently, phase-locked loop (PLL) has been widely used in the field of computers and communications systems applications such as frequency synthesizer, data recovery circuit, and delay de-skewing. In the tradition PLL scheme, a low-pass filter (LPF) consisting of resistors and capacitors is utilized to get rid of the high frequency signal generated by its charge-pump circuit. However, resistors and capacitors in the integrated circuits have great variation in their physical values.
Hence, we proposed a novel architecture of All Digital Phase-Lock Loop to solve the problems in traditional PLL. The fundamental concept of our ADPLL is based on ADPLL proposed by Motorola in 1995. In our ADPLL, the new binary search algorithm has “revisit” and “relock” ability. The Phase Frequency Detector (PFD) is a special type for the novel ADPLL such that it just needs one PFD to complete all of locking process. The ADPLL is designed and implement by TSMC’s 0.35um 1P4M CMOS process for 3.3V applications. The frequency locking range of the proposed ADPLL is about 282MHz to 675MHz.
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Chuang, Yun-Chen, and 莊昀蓁. "An All-Digital Phase-Locked Loop with Dynamic Phase Control for Fast Locking." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/54243081322766241504.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>99<br>This thesis presents an all-digital phase-locked loop (ADPLL) featuring a dynamic phase compensation by a set of the auxiliary timing window. When frequency hopping occurs, the compensation scheme is implemented in both frequency and phase domain for fast settling. The detected phase error is continuously sent to the divider chain which changes the divider ratio, and directly modulates the frequency of the digital-controlled oscillator (DCO) through a digital feed-forward path at the same time. The proposed method allows the ADPLL maintaining a small phase error throughout the frequency acquisition process; thereby reducing setting time. Because of the switching mode operation, the mentioned techniques can solve the trade-off between low jitter and fast lock. An uneven-step time-to-digital converter (TDC) with an error correction encoder is implemented to relax circuit design and save power consumption. The DCO adopts the LC-based architecture because it has the finer tuning gain and better phase noise performance. The proposed ADPLL is implemented to optimize timing jitter and lock time.
The proposed technique is incorporated in the design of a 2.4 GHz ADPLL and fabricated in the TSMC 0.18 um CMOS technology. With less than 5 us lock time in hopping frequency from 5 MHz to 25 MHz, the measured rms jitter from a 2.49 GHz carrier is about 1.93 ps. The phase noise at 100 kHz and 1 MHz is -79.6 dBc/Hz and -112.7 dBc/Hz, respectively. The reference spur at 5 MHz offset is under -50 dBc. The whole circuit dissipates 10.35 mA from a 1.8 V supply and the chip area is 1.8 mm2.
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Tseng, Fu-Hsiang, and 曾福祥. "An All Digital Phase-Locked Loop with Novel Phase and Frequency Error Compensation." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/51873907499729226395.
Full textAbstract:
碩士<br>國立臺灣科技大學<br>電機工程系<br>102<br>This thesis presents a phase-frequency error compensation mechanism for an all digital phase-locked loop (ADPLL). First, a novel digital-controlled oscillator (DCO) was designed. This DCO possesses 8 period vs. control code transfer curves with good linearity. When the system starts, the coarse frequency selector selects a proper DCO curve to which the desired frequency belongs.
The phase error compensation mechanism changes the divisor of the divider to resolve the problem of phase error accumulation by calculating the cycle time difference between the positive edge of the reference clock and the positive edge of the feedback signal from the DCO. After that, The frequency error compensation mechanism is activated to generate the correcting amount of the control-code to fix the frequency error. Next, the phased-frequency error compensation mechanism is used in the acquisition mode of the ADPLL. In the tracking mode, after the system is locked, the control code is extended to enhance the frequency stability.
The proposed ADPLL chip was fabricated in TSMC 0.18um 1P6M CMOS process. The DCO was implemented by the full-custom design flow. The other part of the ADPLL is realized by the cell-based design flow. The DCO’s output frequency range is from 598 MHz to 1.4 GHz and its resolution is between 0.315 ps and 0.364 ps at TT 27℃. The power consumption at 960 MHz frequency is 4.75 mW, and the chip size is around 0.88 mm2.
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Li, Ci, and 李琦. "Low Power All-Digital Phase-Locked Loop with Open loop Mechanism for MEMS Oscillator." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/73820810792344310455.
Full textAbstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>101<br>This thesis illustrates the design and implementation of low power all-digital phase-locked loop with open loop mechanism for MEMS oscillator. The digital phase-locked loop performs 72MHz output with hundreds ppm level frequency accuracy for a wide temperature range, which is designed to calibrate frequency drift of MEMS oscillator under temperature change. With open loop mechanism, we reduce 20% power consumption of digital phase-locked loop circuit, and estimated save 70% system power. By using a standard TSMC 65-nm and 0.18-μm CMOS process, there are three circuits implemented.
Firstly, the digital frequency-locked loop architecture is introduced to accelerate the locking process. The proposed architecture is simply composed of digitally controlled oscillator, bang-bang phase detector, digital divider and binary gain shift logic circuit for reducing the hardware cost and power consumption. Secondly, the phase-injection mechanism is applied to phase-locked loop for continuous output. In order to reduce the power consumption, the proposed lock detector is present in the third digital phase-locked loop design.
Operated at a 1-V supply voltage (1.2-V at 0.18-μm CMOS process), the fabricated circuits consume a dc power less than 1 mW. Except the testing circuits and pads, the active areas are all less than 1 mm2. The functions and performance are verified in the measurement result.
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Chen, Chen-Han, and 陳貞翰. "Develop An All-Digital Phase-locked Loop Compiler In Nanometer CMOS Technologies." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/rfct5s.
Full textAbstract:
碩士<br>國立中正大學<br>資訊工程研究所<br>102<br>Phase-locked loop (PLLs) are widely used in a system-on-a-chip (SoC). In contrast to analog PLLs, all-digital phase-locked loops (ADPLLs) use digital design approaches which allows it to be easily integrated with other digital circuits into the systems in advanced CMOS process. In order to reduce the design time and design efforts when processes or specifications are changed, ADPLLs which implemented with standard cells have best portability and suitable for the SoC as compared with analog PLLs.
Among the functional blocks of the ADPLL, digitally controlled oscillator (DCO) is the most critical component. Because the DCO usually occupies the most portions of the chip area and consumes relative large power consumption than the other blocks of the ADPLL. Furthermore, DCO dominates the major performance of the ADPLL, such as the output frequency range, and output jitter. According to different design requirements for realizing an ADPLL for various applications, such as a spread-spectrum clock generator (SSCG), a fast settling ADPLL, an automatic design flow for the ADPLL is demanded in order to speed up the overall design process and reduce design turnaround time.
Traditionally, PLL usually takes long lock-in time. Thus for power management of the SoC, PLL can’t be turned off for reducing the standby power consumption. The continuous operating PLLs often dominate the standby power consumption of the system. If the PLL can quickly achieve lock-in and then the PLL can be turned off for reducing energy consumption.
Therefore, an ADPLL which has a fast settling that generated by an ADPLL compiler with liberty timing files is presented in this thesis. The proposed ADPLL has following characteristics: fast lock-in time, low power consumption and a flexible DCO architecture with high linearity. In addition, the test chip is implemented and tapeouted in 90nm CMOS process to verify the proposed ADPLL compiler.
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Zhao, Ke-Ching, and 趙可卿. "Supply Sensitivity Compensation Scheme of a 0.5V ALL-Digital Phase-Locked Loop." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/zf7ecr.
Full textAbstract:
碩士<br>國立交通大學<br>電機工程學系<br>102<br>This thesis proposes a supply sensitivity compensation scheme for a 0.5V all-digital phase-locked loop. This design includes an ADPLL, a 4-bit adjustable compensation circuit, and a digital detect circuit. The compensation scheme is designed for foreground execution, which means it detects and finds the best compensation value every time when the power is on. The scheme uses some components of the ADPLL to do jitter measure and follow the result to search the compensation value. After the search is complete, the detection circuit is shut sown to avoid unnecessary power consumption. The power consumption of the ADPLL is 120.3uW for a supply voltage of 0.5V and an operating frequency of 400MHz. It’s peak-to-peak jitter is 74ps. For a noise of 10mV 10kHz sinusoidal waveform on the supply voltage, the peak to peak jitter without and with compensation are 370ps and 101.9ps. This chip will be fabricated in TSMC 90nm 1P9M process, with an area of 0.438 mm^2.