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Dissertations / Theses on the topic 'All digital phase locked loop'

Author: Grafiati

Published: 4 June 2021

Last updated: 27 July 2025

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1

Johnson, Alfred, and Fredrik Andersson. "Modeling and Characterization of an All-Digital Phase-Locked Loop." Thesis, Linköping University, Department of Science and Technology, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54441.

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<p>The thesis "Modeling and Characterization of an All-Digital PLL" aims to create a behavioral model of an All-Digital Phase-Locked-Loop (ADPLL). The model should be able to perform accurate and time-effective simulations. Based on the model, a sub-block requirement will be presented as decision basis for test chip manufacturing.</p><p>The wireless communications industry has grown tremendously in the recent years, leading to strong demand for smaller, faster, better and less power consuming circuits. Digital circuits have better properties in these aspects, which have resulted in great inter

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Zhang, Chi. "System Level Modeling and Verification of All-digital Phase-locked Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175151.

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In wirelesscommunication systems, a local oscillator (LO) aims at demodulating radio-frequency signals into baseband signals. The performance of these signals determines the quality of communications which is highly affected by the phase accuracy of local oscillators. Therefore, evaluating jitter/phase noise should be an essential part when designing wireless communication systems. Typically, LO is achieved by traditional analog PLL. These prototypes have several drawbacks including low integration, narrow bandwidth and high phase noise. With the development of digital techniques, approaches t

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3

Muppala, Prashanth. "High-frequency wide-range all digital phase locked loop in 90nm CMOS." Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1313551049.

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Shen, Jue. "Quantization Effects Analysis on Phase Noise and Implementation of ALL Digital Phase Locked-Loop." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37212.

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With the advancement of CMOS process and fabrication, it has been a trend to maximize digital design while minimize analog correspondents in mixed-signal system designs. So is the case for PLL. PLL has always been a traditional mixed-signal system limited by analog part performance. Around 2000, there emerged ADPLL of which all the blocks besides oscillator are implemented in digital circuits. There have been successful examples in application of Bluetooth, and it is moving to improve results for application of WiMax and ad-hoc frequency hopping communication link. Based on the theoretic and m

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Jiang, Bo. "A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration." ScholarWorks @ UVM, 2016. http://scholarworks.uvm.edu/graddis/562.

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The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the pha

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Wali, Naveen, and Balamurali Radhakrishnan. "Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.

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An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were stud

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Kwong, Kelvin Kam Leung. "Implementation of DSP carrier recovery using all-digital phase-locked loop with vector rotation techniques for high speed 8-PSK modems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ36046.pdf.

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Thomas, Renji George. "A Full Digital Phase Locked Loop." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268184406.

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9

Bouloc, Jeremy. "Système de contrôle pour microscope à force atomique basé sur une boucle à verrouillage de phase entièrement numérique." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4307/document.

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Un microscope à force atomique (AFM) est utilisé pour caractériser des matériaux isolant ou semi-conducteur avec une résolution pouvant atteindre l'échelle atomique. Ce microscope est constitué d'un capteur de force couplé à une électronique de contrôle pour pouvoir correctement caractériser ces matériaux. Parmi les différents modes (statique et dynamique), nous nous focalisons essentiellement sur le mode dynamique et plus particulièrement sur le fonctionnement sans contact à modulation de fréquence (FM-AFM). Dans ce mode, le capteur de force est maintenu comme un oscillateur harmonique par le

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10

Tsao, Ya-lan, and 曹亞嵐. "All Digital Phase-Locked Loop." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/33585222011275948297.

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Wang, You-Jen, and 王佑仁. "Design and Application of All-Digital Delay-Locked Loop and All-Digital Phase-Locked Loop." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/29732818975573400808.

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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>This thesis describes digital implementations and applications of analog circuits for delay-locked loop (DLL) and phase-locked loop (PLL). Compared with analog DLLs and PLLs, the all-digital DLLs and all-digital PLLs have the benefits such as easy process migration, no passive loop filter needed, and fast locked time. Therefore, digital equivalent implementations of analog circuits are more popular, such as delay-locked loop (DLL), phase-locked loop (PLL), clock and data recovery circuit (CDR), and frequency synthesizer. There are four works in this thesis: all-

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You, Rung-Hau, and 游榮豪. "High Speed All Digital Phase-Locked Loop." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/37411327694764982533.

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碩士<br>國立中興大學<br>電機工程學系<br>89<br>Abstract This thesis describes the architecture and design of a high speed all digital phase-locked loop (ADPLL), which uses sample and encode method to decide DCO operation model and frequency region of the input signal in 16 levels. The method can also modify part of algorithm and DCO design. The proposed ADPLL design has characteristics of fast search speed, short frequency locking time, small phase jitter and high operating frequency. This architecture comprises digital controlled oscillator (DCO), frequency detector (FD), phase detector (PD), UP/

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Chin, Yu-Tung, and 秦語彤. "Multi-Function All-Digital Phase-Locked Loop." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/15098274862183007233.

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碩士<br>國立交通大學<br>電子研究所<br>105<br>An ADPLL with spread spectrum circuit, fractional-N circuit, spur reduction circuit, and higher order loop filter is presented. By modulating the output frequency with the triangular profile generator, the simulated EMI reduction can be 30dB. The reference spurs which may mix the signals from adjacent channels can be dealt with by using the spur reduction circuit. When the channel spacing is small, the fractional-N circuit can be utilized for its higher frequency resolution. In the presence of input noise, the ADPLL can select the whole loop as a higher order by

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Huang, Zheng Hui, and 黃正輝. "Phase-Compensated Skill of All Digital Phase-Locked Loop." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/55349637232260385154.

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碩士<br>長庚大學<br>電機工程學系<br>98<br>In the transmission communication field, clock and data recovery circuit is widely used. Among it, in recent years, the development of all-digital clock and data recovery circuit is the mainstream. This paper mainly describes the circuit used in the all-digital clock and data recovery circuit based on phase-locked loop. First, all-digital phase-locked loop will provide locked frequency, let all-digital CDR circuit to recover clock and data, so it can reduce the locking time of all-digital clock and data recovery circuit. However, all-digital PLL has an inherent sh

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Chang, Hung-ju, and 張弘儒. "DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/24031698315028043856.

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碩士<br>大同大學<br>電機工程學系(所)<br>100<br>In this thesis, we designed an all digital phase locked loop (ADPLL). Its structures included phase frequency detectors, time to digital converter, loop filter, digital controlled oscillators, buffer and divider. This thesis not only proposed a new modified time to digital converter which can transform all the impulse into a digital string signal but also modified the circuits of buffer which make all the circuits work well and without interfering of signal delay. Finally, we know that the ranges of locking frequency error are -0.68%~1.62%. The output frequenc

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Hsu, Sheng-Feng, and 徐聖峰. "DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/48811008021719126435.

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碩士<br>大同大學<br>電機工程學系(所)<br>97<br>A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a -chip (SoC) environment is challenging. In addition, the analog PLL is sensitive to process parameters. It is too hard to use the same analog PLL design in different process. On the other hand, The ADPLL has no off-chip components. it is made from standard cells found in most digital standard cell libraries. Therefore, The ADPLL has the higher immuni

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Huang, Wen-Jiun, and 黃文駿. "DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/09055301273166765638.

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碩士<br>大同大學<br>電機工程學系(所)<br>99<br>In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with only four reference clock. A ring-delay-line consisting of 32 stages makes it possible for both the frequency detector and DCO to have a common time base, resulting in this unique clock generator. The pulse delay circuit is connected in a ring shape with 32 inverters ( inverters).With the inverter gate-de

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Chen, I.-Fong, and 陳易楓. "All-digital Clock and Data Recovery and All-digital Phase-locked Loop." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/72656359516188540808.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>97<br>In recent years, the orientation of the fabrication process is to shrink the scaling of the transistor. Scaling down the transistor will have less power consumption and faster operation frequency to design circuits. However, it has extra drawbacks for analog circuits, but it is more suitable for digital circuits. Therefore, digital equivalent implementations of analog circuits are more popular, such as the phase-locked loop and the clock and data recovery. In this thesis, a 1.25 Gbps all-digital clock and data recovery is proposed. The clock frequency of t

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Kung, Fan-Hsiang, and 孔繁祥. "All Digital Phase-Locked Loop With Programmable Phase Injection Locking." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51857591927968419002.

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碩士<br>國立交通大學<br>電機與控制工程系所<br>97<br>This thesis propose an all digital phase-locked loop with programmable phase injection locking mechanics. The phase injection to the digitally controlled oscillator can reduce the phase noise. Using programmable phase injection strength can achieve optimum output performance in different environment. In order to enhance the resolution of digitally controlled oscillator , we use sigma-delta modulator to achieve fractional control on the LSB. This method will enhance resolution of the digitally controlled oscillator. The proposed ADPLL is implemented in TSMC 0

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Jhu, Yong-Jhen, and 朱永楨. "A 4-GHz 10-Phase All Digital Phase-Locked Loop." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36702875300905409844.

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碩士<br>國立中央大學<br>電機工程研究所<br>100<br>A 4-GHz 10-phase all digital phase-locked loop (ADPLL) is proposed for system-on-chip (SoC) systems. The proposed multiphase digital controlled oscillator (MP-DCO) adopts the tri-state inverter loop scheme to obtain the higher operating frequency and wide operation range. The MP-DCO outputs are used to be Time-to-digital Converter (TDC) sampled clock and sample the time difference. Therefore, the reused MP-DCO output can reduce the area cost of the TDC. Time amplifier (TA) can extend the timing resolution of the TDC. The frequency acquisition can achieve the f

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Chen, Jyi-Chang, and 陳吉昌. "Investigation and Desgin of All Digital Phase Locked Loop." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/40526318520931193943.

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碩士<br>國立交通大學<br>電子工程系<br>90<br>In this thesis, we present the design of an all digital phase locked loop (ADPLL), which consists of a phase detector (PD), a frequency detector (FD), a digitally controlled oscillator (DCO), a control unit and some auxiliary logic circuits. A new phase tracking algorithm is proposed to reduce the accumulative phase error without slowing down the tracking speed, and a modify frequency detector circuit which can cancel the internal error delay. We analyze and design each functional block in detail, and point out the important design parameters and discuss some des

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Ciou, Jyun-Han, and 邱俊翰. "Multiphase All Digital Phase Locked Loop with Monitor Counter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/32781326096008575730.

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碩士<br>國立高雄第一科技大學<br>電腦與通訊工程研究所<br>99<br>Traditionally, the frequency synthesizer is based on the phase locked loop (PLL). In order to achieve chip synchronization for the requirements of the operating frequency, the PLL is increasingly important. The multi-phase voltage controlled oscillator generates the same frequency with different output phases. This paper proposes a NAND based architecture for the multi-phase digital control oscillators (DCO). In addition, we also propose a multi-phase ADPLL with monitor counter. The output phases of digital controlled oscillator are eight and the control

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Huang, Tien-yu, and 黃天佑. "ALL DIGITAL PHASE-LOCKED LOOP WITH ADAPTIVE SEARCHING ALGORITHM." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/92498336738843568554.

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碩士<br>大同大學<br>通訊工程研究所<br>98<br>Due to the disadvantages of the traditional analog phase-locked loop (APLL) over source stability, noise interference and design difficulty, the all digital phase-locked loop (ADPLL) can provide better performance than the traditional PLL. The ADPLL is programmable and portable over design that it can efficiently reduce the difficulties in other design process. This thesis implements an ADPLL with a searching algorithm in its control unit that can perform in high frequency resolutions, and the algorithm provides fast tracking search step to further reduce the loc

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Huang, Tzu-Chi, and 黃梓期. "All Digital Phase-Locked Loop Using Active Inductor Oscillator." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/40441356915930297288.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>97<br>Phase-locked loop (PLL) is a widely used circuit for clock generation and RF front-end systems. All digital designs have been researched in recent years because of the high area efficiency, adjusting to different process and low noise. In this paper, an all-digital phase-locked loop (ADPLL) using active inductor digital controlled oscillator is presented. The digital controlled active inductor offers a wide operating frequency range, good signal quality and small chip area. The novel phase lock in algorithm has the characteristics of high jitter performance,

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Lee, Yi-Herng, and 李宜衡. "Adaptive Bandwidth All-Digital Phase-Locked Loop chip design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/37929583369693061704.

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碩士<br>元智大學<br>通訊工程學系<br>97<br>Phase-locked loop design in the adaptive bandwidth, for different operating frequency, enables to change the circuit characteristics to achieve the optimal performance. However, the traditional Analog Adaptive-Bandwidth Phase-locked loop, it is challenging to control the parameter. Moreover, the analog circuit design has the higher design complexity and the higher production cost. Hence, we proposed a All-Digital Adaptive-Bandwidth Phase-locked loop, and we will also design the new All-Digital loop filter to reduce the circuit complexity. Pre-layout and post-layou

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Yang, Yu-Sheng, and 楊于昇. "A 0.5V Low Power All-Digital Phase-Locked Loop." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/77999168478677744569.

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碩士<br>國立交通大學<br>電控工程研究所<br>99<br>In recent years, low power designs for portable devices become popular. Many consumer electronics are asked to consume as less power as possible to extend the battery lifetime. Owing to the progress in CMOS technology, the threshold voltage of the transistor keeps degrading. But the degrading of the system supply voltage is much faster. Under the low power supply environment, the gate-source voltage decreases which leads to the decay of the driving ability. Hence the operation frequency of digital circuit is limited. Besides, the system suffers from process var

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Chen, Chun-Ming, and 陳俊銘. "A 1.25GHz All Digital Phase-Locked Loop with 8-phase Output." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/vk5g3b.

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碩士<br>國立交通大學<br>電機與控制工程系所<br>94<br>The increasing demand for the data bandwidth in network has driven the development of high-speed serial link technology. The high speed serial links have been applied in optical communication, USB, IEEE-1394. This thesis develops a transmitter front-end circuit design in 0.18um CMOS process technologies. The objective goal of this research is to realize 1.25Gbps an all-digital serial link transmitter. There are two major topics in this thesis. First, we compare and analyze all types of serializer. Base on the comparison results and IEEE802.3ah specification,

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Chung, Yu-Ming, and 張郁敏. "An All-Digital Phase-Locked Loop for Digital Power Management Circuits." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/09774111174976454112.

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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>The phase-locked-loop (PLL) is widely used in different applications, such as frequency synthesis, clock/data recovery, and clock de-skewing. Presently, the most designs of the PLL are digital PLLs which have analog loop filter and oscillator in their circuits, but with the advances in integrated circuit (IC) technology, the fabrication processes is more and more suitable for digital designs. A digital design is scalability and easy redesign with process changes or shrinks. Moreover designing an all-digital PLL can inherent noise immunity of digital circuits

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Hsu, Li-Fan, and 徐立凡. "ALL DIGITAL PHASE-LOCKED LOOP WITH HIGH RESOLUTION DIGITAL CONTROLLED OSCILLATOR." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/03532117016625588613.

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碩士<br>大同大學<br>通訊工程研究所<br>98<br>In this thesis, we implement an all digital phase locked loop (ADPLL) with high resolution digital controlled oscillator. We use time to digital converter to quantize phase error and use a high resolution ring oscillator to be the digital controlled oscillator in the circuit. Working frequency ranges for this ADPLL is about 212~366MHz. When reference signal is 5MHz and a multiplication factor of 64, the lock-in time is about 3.5 s. The feasibility and performance of the ADPLL is verified with the MATLAB Simulink.

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Chao, Kuan-Chieh, and 趙冠傑. "A Study of High-Resolution All-Digital Phase-Locked Loop." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10104992573991641021.

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碩士<br>中華大學<br>電機工程學系(所)<br>97<br>The quality of parallel synchronization signal in communication systems is very important. Therefore, Phase-Locked Loops (PLLs) are common circuits of modern circuit design. Traditionally, a Phase-Locked Loop is making up of an analog circuit. The analog-PLL (APLL) has good quality of phase noise and loop bandwidth. But, the APLL is sensitive to process, supply voltage and temperature. The current trend is towards All-Digital Phase-Locked Loop (ADPLL). In this study, we proposed an ADPLL. The minimum resolution of Digital Controlled Oscillator (DCO) is the ma

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Hsieh, Cheng-Che, and 謝承哲. "DESIGN AND IMPLEMENTATION OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/01242378694973792971.

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碩士<br>大同大學<br>電機工程學系(所)<br>98<br>A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a-chip (SoC) environment is challenging. In addition, the analog PLL is sensitive to process parameters. It is too hard to use the same analog PLL design in different process. On the other hand, the ADPLL has no off-chip components. It is made from standard cells found in most digital standard cell libraries. Therefore, the ADPLL has the higher immunit

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Wang, Kai-Pin, and 王凱平. "Investigation and Analysis of an All Digital Phase-Locked Loop." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/62181159818869755155.

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碩士<br>元智大學<br>通訊工程學系<br>92<br>The communication industry develops rapidly in recent years,making its related components also seemed to be the importance more.Among them,phase-locked loop（PLL）plays the most important role,the application of it's architecture is also too numerous to count up.Because of this,how to promote the PLL integrated performance becomes a vary important topic. In this thesis,a novel all digital phase-locked loop（ADPLL）based on the 74HC/HCT297 single-chip ADPLL.Two values of the K for the K counter are used and implemented.With a dynamical selection of the count

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Jan, Wei-Chan, and 鄭為全. "Analysis and Design of the All-Digital Phase-Locked Loop." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/19532210035147422505.

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碩士<br>國立臺灣大學<br>電機工程學系<br>85<br>Recently, phase-locked loop (PLL) has been widely used in the fields ofcomputers and communications. A PLL-based circuit can synchronize an outputsignal whose frequency is adjustable to satisfy the specification requirementswith a reference clock in frequency as well as in phase. In the traditional PLL, a low- pass filter (LPF) consisting of resistors andcapacitors is utilized to get rid of the high frequency signal generated by itscharge-pump circuit. Howev

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Su, Ming-Chiuan, and 蘇明銓. "All Digital Phase-Locked Loop for Spread-Spectrum Clock Generator." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/43743861319797682304.

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碩士<br>國立交通大學<br>電子工程系所<br>98<br>Abstract As SOC(System On Chip) works with increasing internal reference clocks, the spread-spectrum clocking technique is used to mitigate EMI(Electro-Magnetic Interference) effect. Conventional analog PLLs are likely to be affected by PVT (process/voltage/temperature) variations. Hence, when using deep-submicron CMOS process, PLLs are prone to all-digital design. All-digital PLL consists of bang-bang PFD, accumulator-based digital loop filter, differential DCO and divider. Bang-bang PFD generates phase compare signals to control accumulator-based digital loop

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Yang, E.-Ing, and 楊怡英. "The Implementation and Analysis of All Digital Phase-Locked Loop." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/65915664750386172130.

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碩士<br>國立中央大學<br>電機工程學系<br>85<br>In this thesis, an all digital phase-locked loop(ADPLL) is proposed. The architecture of the proposed ADPLL is based on the ADPLL proposed by Motorola in 1995, but some modifications are made. A digitally controlled oscillator form the core of the ADPLL. The DCO we used is a 3-stage ring oscillator with a 14-bit binary weighted control mechanism, and the operating frequency range of the DCO is from 280MHz~500MHz. Because we increase the bits of control word s

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Guo, Bo-Cheng, and 郭博誠. "An All-Digital Phase-locked Loop Based on Bang-bang Phase Detector." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/65697275653465004904.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>99<br>As the progress of CMOS technology, phase-locked loop has been widely implemented in many applications, such as mems, memory integrated chip and communication systems. It is used to generate the clock frequency and phase in a system. The traditional structure of a phase-locked loop could be classified into two kinds. One is analog phase-locked loop (APLL), the other is all-digital phase-locked loop (ADPLL). Although the former is usually adopted by conventional ic designer, ADPLL is more suggested in recently years because of its good tolerance to PVT variatio

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Su, Hung-Lung, and 蘇鴻隆. "The Implementation and Analysis of an All-digital Phase-Locked Loop." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/y84b7d.

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碩士<br>朝陽科技大學<br>資訊工程系碩士班<br>94<br>Abstract An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in deep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time. A

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Chang, Chia-Chen, and 張家甄. "Fast Locking All-Digital Phase-Locked Loop with Higher-Order Filter." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/rfcq33.

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碩士<br>國立交通大學<br>電子工程學系電子研究所<br>104<br>A stable clock signal plays an important role in a system. As the speed of internal reference clock in the System-on-Chip (SOC) increased and the scaling down of the process, the effect of noise is more significant to the SOC. Therefore, a fast locking all-digital phase-locked loop (ADPLL) with higher-order filter is proposed in the thesis. At the frequency acquisition mode, the locking time is 5 cycles of the reference clock period by using the method of linear interpolation. On the other hand, at the phase tracking mode, the proposed ADPLL can select th

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Cheng, Chi-Cheng, and 鄭吉成. "The Analysis and Design of All-Digital Phase-Locked Loop (ADPLL)." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/76306613951012057301.

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碩士<br>國立交通大學<br>電子工程系<br>89<br>In this thesis, we have presented the design of an all-digital phase-locked loop (ADPLL), which consists of a digitally controlled oscillator (DCO), a phase frequency detector (PFD), a control unit and some auxiliary logic circuits. By analyzing and designing each functional block in detail, we point out the important design parameters and discuss some design issues. The DCO consists of four paths, two modes, and a 5-bit controlled delay cell. The delay cell is a digitally controlled current-starved inverter. We adopt a D flip-flop as our PFD. The control unit pe

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Sung, Chuan-Yuan, and 宋權原. "USE FPGA TO DESIGN THE ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/47666718473594873911.

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碩士<br>大同大學<br>電機工程學系(所)<br>98<br>The phase- locked loop (PLL) has been widely used in different field such as computer, consumer electronics, and communication , etc. We have to overcome many complicated problems to integrate a analog PLL into the single chip system full of noise. The sensitive process change of analog PLL would result in much noise and other problems. Therefore, we have to redesign the parameters of analog components in different processer and it usually takes a lot of time. In order to solve all the issues, all-digital design is option. Because all-digital circuit means that

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Liu, Ta-Wei, and 劉大維. "Design and Analysis of a Novel All Digital Phase-Locked Loop." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/51110173758933390178.

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碩士<br>淡江大學<br>電機工程學系<br>90<br>Recently, phase-locked loop (PLL) has been widely used in the field of computers and communications systems applications such as frequency synthesizer, data recovery circuit, and delay de-skewing. In the tradition PLL scheme, a low-pass filter (LPF) consisting of resistors and capacitors is utilized to get rid of the high frequency signal generated by its charge-pump circuit. However, resistors and capacitors in the integrated circuits have great variation in their physical values. Hence, we proposed a novel architecture of All Digital Phase-Lock Loop t

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Wu, Hsu-Heng, and 吳旭珩. "Fractional Frequency Synthesizer Based on All Digital Phase-Locked Loop (ADPLL)." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/05658100710312003208.

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碩士<br>國立臺北科技大學<br>電腦通訊與控制研究所<br>90<br>The frequency synthesizer is used to generate more one frequency from an input reference source for the applications of accuracy clock requirement, such as clock generator and transceiver. With the rapidly growth of wireless communication system and the high performance in clock accuracy and stability, the frequency synthesizer have became more important. In this thesis, we proposed a fractional frequency synthesizer based on all digital phase-locked loop (ADPLL). A novel phase frequency detector (PFD) is developed for replacing the two independ

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Xie, Shan-yang, and 謝善揚. "Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/x7jt7e.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>106<br>This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as some control units. This all-digital phase-locked loop has the following characteristics: 1. The digitally controlled oscillator uses the low power schmitt trigger inverter as a delay element to reduce power consumption and reduce output jitter. 2. Resolution is divided into 6-bit coarse-tuning and 5-bit fine-tuning , coarse delay time range covers the fine delay time, thr

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Tseng, Fu-Hsiang, and 曾福祥. "An All Digital Phase-Locked Loop with Novel Phase and Frequency Error Compensation." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/51873907499729226395.

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碩士<br>國立臺灣科技大學<br>電機工程系<br>102<br>This thesis presents a phase-frequency error compensation mechanism for an all digital phase-locked loop (ADPLL). First, a novel digital-controlled oscillator (DCO) was designed. This DCO possesses 8 period vs. control code transfer curves with good linearity. When the system starts, the coarse frequency selector selects a proper DCO curve to which the desired frequency belongs. The phase error compensation mechanism changes the divisor of the divider to resolve the problem of phase error accumulation by calculating the cycle time difference between the positi

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Chuang, Yun-Chen, and 莊昀蓁. "An All-Digital Phase-Locked Loop with Dynamic Phase Control for Fast Locking." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/54243081322766241504.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>99<br>This thesis presents an all-digital phase-locked loop (ADPLL) featuring a dynamic phase compensation by a set of the auxiliary timing window. When frequency hopping occurs, the compensation scheme is implemented in both frequency and phase domain for fast settling. The detected phase error is continuously sent to the divider chain which changes the divider ratio, and directly modulates the frequency of the digital-controlled oscillator (DCO) through a digital feed-forward path at the same time. The proposed method allows the ADPLL maintaining a small phase err

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Yeh, Chi-Lung, and 葉啟龍. "A Novel Structure of Digitally Controlled Oscillator for All-Digital Phase-Locked Loop." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/14350903718844927363.

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碩士<br>國立中興大學<br>電機工程學系<br>91<br>This thesis describes the architecture and design of digitally controlled oscillator（DCO） for all-digital phase-locked loop（ADPLL）, which uses a novel structure to improve the drawback of the traditional DCO structure. The proposed DCO design has characteristics of superior linearity, better oscillatory waveform, smaller Jitter, and higher oscillatory frequency. The novel DCO has a 14-bit digitally controlled word and is implemented by the TSMC 0.35μm 1P4M technology. The supply voltage is 3V. The simulation results show 14-bit resolution of DCO. When

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Li, Ci, and 李琦. "Low Power All-Digital Phase-Locked Loop with Open loop Mechanism for MEMS Oscillator." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/73820810792344310455.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>101<br>This thesis illustrates the design and implementation of low power all-digital phase-locked loop with open loop mechanism for MEMS oscillator. The digital phase-locked loop performs 72MHz output with hundreds ppm level frequency accuracy for a wide temperature range, which is designed to calibrate frequency drift of MEMS oscillator under temperature change. With open loop mechanism, we reduce 20% power consumption of digital phase-locked loop circuit, and estimated save 70% system power. By using a standard TSMC 65-nm and 0.18-μm CMOS process, there are three

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Hsu, Terng-Yin, and 許騰尹. "The Study of All Digital Phase-Locked Loop (ADPLL) and its Applications." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/08268281986945879028.

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博士<br>國立交通大學<br>電子工程系<br>88<br>All digital phase-locked loop (ADPLL) has a good capacity of portable issues to reduce system-turnaround time during process migration. In order to make system more efficient and robust, new algorithms for ADPLL have been developed in this thesis. By period estimation of phase error and 2-stage frequency search, the proposed ADPLL solution can achieve better performance, compared to available PLL’s solutions, in terms of lock-in time, pull-in range, and system stability. Two digital frequency synthesizer (DFS), and two clock recovery circuits are explored to meet

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Chen, Chen-Han, and 陳貞翰. "Develop An All-Digital Phase-locked Loop Compiler In Nanometer CMOS Technologies." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/rfct5s.

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碩士<br>國立中正大學<br>資訊工程研究所<br>102<br>Phase-locked loop (PLLs) are widely used in a system-on-a-chip (SoC). In contrast to analog PLLs, all-digital phase-locked loops (ADPLLs) use digital design approaches which allows it to be easily integrated with other digital circuits into the systems in advanced CMOS process. In order to reduce the design time and design efforts when processes or specifications are changed, ADPLLs which implemented with standard cells have best portability and suitable for the SoC as compared with analog PLLs. Among the functional blocks of the ADPLL, digitally controlled os

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Zhao, Ke-Ching, and 趙可卿. "Supply Sensitivity Compensation Scheme of a 0.5V ALL-Digital Phase-Locked Loop." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/zf7ecr.

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碩士<br>國立交通大學<br>電機工程學系<br>102<br>This thesis proposes a supply sensitivity compensation scheme for a 0.5V all-digital phase-locked loop. This design includes an ADPLL, a 4-bit adjustable compensation circuit, and a digital detect circuit. The compensation scheme is designed for foreground execution, which means it detects and finds the best compensation value every time when the power is on. The scheme uses some components of the ADPLL to do jitter measure and follow the result to search the compensation value. After the search is complete, the detection circuit is shut sown to avoid unnecessa

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