Log in

Relevant bibliographies by topics / All digital phase locked loop / Journal articles

To see the other types of publications on this topic, follow the link: All digital phase locked loop.

Journal articles on the topic 'All digital phase locked loop'

Author: Grafiati

Published: 4 June 2021

Last updated: 27 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'All digital phase locked loop.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Staszewski, R. B., and P. T. Balsara. "Phase-domain all-digital phase-locked loop." IEEE Transactions on Circuits and Systems II: Express Briefs 52, no. 3 (2005): 159–63. http://dx.doi.org/10.1109/tcsii.2004.842067.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Anupama, Patil* Dr P.H.Tandel. "DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP." DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP 5, no. 5 (2016): 134–38. https://doi.org/10.5281/zenodo.51007.

Full text

Abstract:

The Phase Locked Loop (PLL) is an almost always used electronics circuit for communication systems like modulator, demodulator, frequency generator and frequency synthesizer etc. All-digital phase locked loop (ADPLL) is digital version of the PLL. In this paper, a novel Hilbert transform based phase detection system for all-digital phase locked loop (ADPLL) is presented. The digital discrete time components are used to realize the phase detector system reducing the complexity of the design. The Hilbert transform based phase detection system provides a definite advantage over conventional analo

APA, Harvard, Vancouver, ISO, and other styles

3

S C, Mrs Shyamala, Latish Patil, Srinivas Gowda K R, Yashwanth T, and Dhruva Kumar T R. "Realization of an All-Digital Phase-Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–7. https://doi.org/10.55041/ijsrem39448.

Full text

Abstract:

An all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs. The implementation of ADPLL utilizing a Xilinx Vivado tool and code is written in Verilog. Key Words: All Digital PLL, digitally controlled oscillator(DCO),Low Pass Filter(LPF),Increment-Decrement (ID)

APA, Harvard, Vancouver, ISO, and other styles

4

B R, Mr Chethan, Punith H D, Abhishek Gowda H A, Manoj B S, and Rahul H R. "Design of Phase Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39446.

Full text

Abstract:

A Phase-Locked Loop (PLL) is a crucial feedback control system used to synchronize the phase of an output signal with a reference signal. This paper explores the design, analysis, and applications of PLLs in modern communication systems, digital circuits, and power electronics. The study covers the fundamental components of a PLL—phase detector, low-pass filter, and voltage-controlled oscillator (VCO)—and their interactions in achieving phase synchronization. Key performance parameters such as lock time, jitter, stability, and noise sensitivity are examined in detail. Furthermore, the paper di

APA, Harvard, Vancouver, ISO, and other styles

5

Kumm, Martin, Harald Klingbeil, and Peter Zipf. "An FPGA-Based Linear All-Digital Phase-Locked Loop." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 9 (2010): 2487–97. http://dx.doi.org/10.1109/tcsi.2010.2046237.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Shayan, Y. R., and T. Le-Ngoc. "All digital phase-locked loop: concepts, design and applications." IEE Proceedings F Radar and Signal Processing 136, no. 1 (1989): 53. http://dx.doi.org/10.1049/ip-f-2.1989.0007.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

R, Swetha, J. Manjula, and A. Ruhan bevi. "Design of All Digital Phase Locked Loop for Wireless Applications." International Journal of Engineering & Technology 7, no. 3.12 (2018): 836. http://dx.doi.org/10.14419/ijet.v7i3.12.16513.

Full text

Abstract:

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

APA, Harvard, Vancouver, ISO, and other styles

8

Sun, Hua Fang, Xin Ning Liu, and Xin Chen. "Optimum Digital Filter for High-Performance All-Digital Phase-Locked Loop." Applied Mechanics and Materials 182-183 (June 2012): 587–92. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.587.

Full text

Abstract:

The effect of all-digital phase-locked loop (ADPLL) digital filter parameters on the jitter is investigated in time domain, and a systematic design procedure for ADPLL is presented. The pro-posed method not only estimates the output jitter of an ADPLL, but also finds the optimal filter pa-rameter minimizing the overall ADPLL timing jitter. To verify the theoretic analysis, an ADPLL behavior model in matlab is designed. The simulation shows significant performance improvement on the timing jitter.

APA, Harvard, Vancouver, ISO, and other styles

9

Park, Gun-Ho, Jae-Jin Lee, Seong-Jin Oh, and Kang-Yoon Lee. "Low-Power All Digital Delay Locked Loop with Dynamically Phase Error Tracking for a PVT Compensation Loop." Journal of Korean Institute of Electromagnetic Engineering and Science 31, no. 7 (2020): 571–76. http://dx.doi.org/10.5515/kjkiees.2020.31.7.571.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Jurgo, Marijan. "ALL DIGITAL PHASE-LOCKED LOOP / VISIŠKAI SKAITMENINĖ FAZĖS DERINIMO KILPA." Mokslas - Lietuvos ateitis 5, no. 2 (2013): 128–32. http://dx.doi.org/10.3846/mla.2013.24.

Full text

Abstract:

The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33

APA, Harvard, Vancouver, ISO, and other styles

11

Xu, Liangge, Saska Lindfors, Kari Stadius, and Jussi Ryynanen. "A 2.4-GHz Low-Power All-Digital Phase-Locked Loop." IEEE Journal of Solid-State Circuits 45, no. 8 (2010): 1513–21. http://dx.doi.org/10.1109/jssc.2010.2047453.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Patil, Anupama, and P. H. Tandel. "A Numerically controlled oscillator for all Digital Phase Locked Loop." International Journal of Engineering Trends and Technology 38, no. 4 (2016): 186–89. http://dx.doi.org/10.14445/22315381/ijett-v38p233.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Radhapuram, Saichandrateja, Jungnam Bae, Ikkyun Jo, Weimin Wang, and Toshimasa Matsuoka. "ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP." Far East Journal of Electronics and Communications 15, no. 1 (2015): 57–73. http://dx.doi.org/10.17654/fjecsep2015_057_073.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Gong, X. F., and Z. D. Cui. "An all-digital phase-locked loop demodulator based on FPGA." IOP Conference Series: Materials Science and Engineering 242 (September 2017): 012096. http://dx.doi.org/10.1088/1757-899x/242/1/012096.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Hikawa, Hiroomi, Nanning Zheng, and Shinsaku Moris. "All digital phase-locked loop with a wide locking range." Electronics and Communications in Japan (Part I: Communications) 70, no. 7 (1987): 70–77. http://dx.doi.org/10.1002/ecja.4410700708.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Ho, Yung-Hsiang, and Chia-Yu Yao. "A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 5 (2016): 1984–92. http://dx.doi.org/10.1109/tvlsi.2015.2470545.

Full text

APA, Harvard, Vancouver, ISO, and other styles

17

Kratyuk, Volodymyr, Pavan Kumar Hanumolu, Un-Ku Moon, and Kartikeya Mayaram. "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 3 (2007): 247–51. http://dx.doi.org/10.1109/tcsii.2006.889443.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

CHAU, YAWGENG A., and CHEN-FENG CHEN. "ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS." Journal of Circuits, Systems and Computers 20, no. 06 (2011): 1037–49. http://dx.doi.org/10.1142/s0218126611007748.

Full text

Abstract:

The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency

APA, Harvard, Vancouver, ISO, and other styles

19

Lin, Jung-Mao, and Ching-Yuan Yang. "A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 10 (2015): 2411–22. http://dx.doi.org/10.1109/tcsi.2015.2477575.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Panasiewicz, Jognes, Nisrine Arab, Fabien Destic, Gefeson M. Pacheco, and Angélique Rissons. "An All-Digital Optical Phase-Locked Loop Suitable for Satellite Downlinks." Photonics 10, no. 12 (2023): 1312. http://dx.doi.org/10.3390/photonics10121312.

Full text

Abstract:

The optical signal propagation used in satellite uplinks and downlinks is influenced by absorption, scattering, and changes in the atmospheric refractive index or turbulence, causing optical signal attenuation. A free space optics (FSO) communications system using coherent communication can improve the link sensitivity and reach higher distances. This article proposes a new architecture for the phase detector in an all-digital optical phase-locked loop (OPLL) for coherent optical detection. Firstly, the performance of the proposed phase detector is evaluated under Gaussian noise, where the bes

APA, Harvard, Vancouver, ISO, and other styles

21

Radhapuram, Saichandrateja, Takuya Yoshihara, and Toshimasa Matsuoka. "Design and Emulation of All-Digital Phase-Locked Loop on FPGA." Electronics 8, no. 11 (2019): 1307. http://dx.doi.org/10.3390/electronics8111307.

Full text

Abstract:

This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, whichis fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control andfractional tuning range using the DSM. The ring-DCO does not contain library-specific cells andcan be synthesized independently of the

APA, Harvard, Vancouver, ISO, and other styles

22

Cong, Haolin, and Massoud Pedram. "All-Digital Phase-Locked Loop in Single Flux Quantum Circuit Technology." IEEE Transactions on Applied Superconductivity 32, no. 3 (2022): 1–8. http://dx.doi.org/10.1109/tasc.2022.3151728.

Full text

APA, Harvard, Vancouver, ISO, and other styles

23

Ching-Che Chung and Chen-Yi Lee. "An all-digital phase-locked loop for high-speed clock generation." IEEE Journal of Solid-State Circuits 38, no. 2 (2003): 347–51. http://dx.doi.org/10.1109/jssc.2002.807398.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Koskin, Eugene, Pierre Bisiaux, Dimitri Galayko, and Elena Blokhina. "Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 1 (2021): 77–81. http://dx.doi.org/10.1109/tcsii.2020.3008069.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee. "An all-digital phase-locked loop (ADPLL)-based clock recovery circuit." IEEE Journal of Solid-State Circuits 34, no. 8 (1999): 1063–73. http://dx.doi.org/10.1109/4.777104.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Radhapuram, Saichandrateja, Jungnam Bae, Ikkyun Jo, Weimin Wang, and Toshimasa Matsuoka. "ERRATUM: ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP." Far East Journal of Electronics and Communications 16, no. 1 (2016): 199–201. http://dx.doi.org/10.17654/ec016010199.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Lu, Ping, and Henrik Sjöland. "A 5 GHz 90-nm CMOS all digital phase-locked loop." Analog Integrated Circuits and Signal Processing 66, no. 1 (2010): 49–59. http://dx.doi.org/10.1007/s10470-010-9501-9.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Martín-Segura, Guillermo, Pau Sala-Pérez, Coia Ferrater-Simón, Joaquim López-Mestre, Joan Bergas-Jané, and Daniel Montesinos-Miracle. "All-digital DSP-based phase-locked loop for induction heating applications." International Transactions on Electrical Energy Systems 23, no. 7 (2012): 1095–106. http://dx.doi.org/10.1002/etep.1640.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Namgoong, Won. "An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 3 (2016): 1025–35. http://dx.doi.org/10.1109/tvlsi.2015.2426878.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Yu, Guangming, Yu Wang, and Huazhong Yang. "A low power time-to-digital converter for all-digital phase-locked loop." Journal of Electronics (China) 28, no. 3 (2011): 402–8. http://dx.doi.org/10.1007/s11767-011-0720-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Kuang Yunfan, 匡云帆, 严高师 Yan Gaoshi, and 张心标 Zhang Xinbiao. "Control system of all-digital phase-locked loop for phase-shift laser ranging." High Power Laser and Particle Beams 24, no. 7 (2012): 1705–8. http://dx.doi.org/10.3788/hplpb20122407.1705.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Mendel, S., C. Vogel, and N. Da Dalt. "A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming." IEEE Transactions on Circuits and Systems II: Express Briefs 56, no. 11 (2009): 860–64. http://dx.doi.org/10.1109/tcsii.2009.2034079.

Full text

APA, Harvard, Vancouver, ISO, and other styles

33

Das, Abhishek, Suraj Dash, B. Chitti Babu, and A. K. Sahoo. "CORDIC Algorithm Based Novel Phase Detection System for All Digital Phase Locked Loop." Journal of Computational Intelligence and Electronic Systems 1, no. 1 (2012): 23–30. http://dx.doi.org/10.1166/jcies.2012.1002.

Full text

APA, Harvard, Vancouver, ISO, and other styles

34

Sayadi, Mohamad, and Ebrahim Farshidi. "A fast locked and low phase noise all-digital phase locked loop based on model predictive control." Analog Integrated Circuits and Signal Processing 88, no. 3 (2016): 401–14. http://dx.doi.org/10.1007/s10470-016-0794-1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Zhai, Bingcong. "Understanding of the Coherent Demodulation with Phase-Locked Loop." MATEC Web of Conferences 176 (2018): 01028. http://dx.doi.org/10.1051/matecconf/201817601028.

Full text

Abstract:

The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way. Therefore, more and more attentions have been paid to the research and application of all digital phase-locked loops. This paper serves as an introduction about the basic background of PLL, the basic characteristics and structure of PLL, and the basic principles of modulation and demodulation. It provides a concise application about the basic principle and

APA, Harvard, Vancouver, ISO, and other styles

36

Zhuang, Jingcheng, and Robert Bogdan Staszewski. "All-Digital RF Phase-Locked Loops Exploiting Phase Prediction." IPSJ Transactions on System LSI Design Methodology 7 (2014): 2–15. http://dx.doi.org/10.2197/ipsjtsldm.7.2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Balikai, Vikas, and Harish Kittur. "A CMOS implementation of controller based all digital phase locked loop (ADPLL)." Circuit World 47, no. 1 (2020): 71–85. http://dx.doi.org/10.1108/cw-11-2019-0184.

Full text

Abstract:

Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose o

APA, Harvard, Vancouver, ISO, and other styles

38

Ramaswami Palaniappan, Arjun, and Liter Siek. "A TDC-less all-digital phase locked loop for medical implant applications." Microprocessors and Microsystems 69 (September 2019): 168–78. http://dx.doi.org/10.1016/j.micpro.2019.06.008.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Vydehi, Nakkina, and A. S. Srinivasa Rao. "A Low Power VLSI Design of an All Digital Phase Locked Loop." International Journal of Engineering Trends and Technology 16, no. 6 (2014): 288–92. http://dx.doi.org/10.14445/22315381/ijett-v16p256.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Choi, Young-Ho, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park. "A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop." IEEE Transactions on Circuits and Systems II: Express Briefs 64, no. 3 (2017): 249–53. http://dx.doi.org/10.1109/tcsii.2016.2560340.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Yang, Jaehyeok, Joon-Yeong Lee, Sun-Jae Lim, and Hyeon-Min Bae. "Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 11 (2014): 880–84. http://dx.doi.org/10.1109/tcsii.2014.2356893.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Akram, Muhammad Abrar, Kyeong-Woo Kim, Jin-Hee Bae, and In-Chul Hwang. "All digital duty-cycle corrector for integrated phase noise improvement in phase-locked loop." Analog Integrated Circuits and Signal Processing 101, no. 3 (2019): 641–49. http://dx.doi.org/10.1007/s10470-019-01554-3.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Madoglio, P., M. Zanuso, S. Levantino, C. Samori, and A. L. Lacaita. "Quantization Effects in All-Digital Phase-Locked Loops." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 12 (2007): 1120–24. http://dx.doi.org/10.1109/tcsii.2007.906171.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Hung, Chao-Ching, and Shen-Iuan Liu. "A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm." IEEE Transactions on Circuits and Systems II: Express Briefs 58, no. 6 (2011): 321–25. http://dx.doi.org/10.1109/tcsii.2011.2149610.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Yu, Jia Xin, Qin Shi, Guo Ming Xia, An Ping Qiu, Xue Hao Yu, and Zhong Hai Pei. "The Analysis and Design of Closed-Loop Control System for MEMS Vibratory Gyroscopes." Applied Mechanics and Materials 868 (July 2017): 51–57. http://dx.doi.org/10.4028/www.scientific.net/amm.868.51.

Full text

Abstract:

A digital closed-loop control system with all digital phase locked loop (ADPLL) is designed and optimized, in order to improve the bias stability and transient response of the gyroscope. The nonlinear mathematical models for the closed-loop amplitude and phase control system are established. The linearization method is applied to analyze the nonlinear models. The control parameters of the drive loop are optimized. The experimental results show that the phase deviation between the demodulation reference signal of the drive loop and the sense signal is less than 0.25° in the temperature range fr

APA, Harvard, Vancouver, ISO, and other styles

46

Zhou, Duo, Jin Yi Zhang, and Bo Ye. "An Implementation of Wide-Range Digital Delay Locked Loop." Advanced Materials Research 945-949 (June 2014): 2226–29. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.2226.

Full text

Abstract:

This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. Th

APA, Harvard, Vancouver, ISO, and other styles

47

Ishak, S. N., J. Sampe, Z. Yusoff, and M. Faseehuddin. "ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW." Jurnal Teknologi 84, no. 1 (2021): 219–30. http://dx.doi.org/10.11113/jurnalteknologi.v84.17123.

Full text

Abstract:

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, th

APA, Harvard, Vancouver, ISO, and other styles

48

Jang, Taekwang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, and David Blaauw. "A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector." IEEE Journal of Solid-State Circuits 53, no. 1 (2018): 50–65. http://dx.doi.org/10.1109/jssc.2017.2776313.

Full text

APA, Harvard, Vancouver, ISO, and other styles

49

Kang, Byeongseok, Youngsik Kim, Hyunwoo Son, and Shinwoong Kim. "A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning." Electronics 13, no. 13 (2024): 2638. http://dx.doi.org/10.3390/electronics13132638.

Full text

Abstract:

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, d

APA, Harvard, Vancouver, ISO, and other styles

50

Cheng, Kuo-Hsing, Jen-Chieh Liu, and Hong-Yi Huang. "A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator." IEEE Transactions on Circuits and Systems II: Express Briefs 59, no. 12 (2012): 888–92. http://dx.doi.org/10.1109/tcsii.2012.2231021.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!