Bibliographies: 'Altera DE2-115'

1

Syed Abdul Mutalib Al Junid, Fadli Hamidi Rusli, Muhammad Hasif Aiman Mohd Sarwar Kamal Helal, et al. "Accelerating DNA Sequence Alignment using Altera DE2-115." Journal of Advanced Research in Applied Sciences and Engineering Technology 52, no. 1 (2024): 122–31. http://dx.doi.org/10.37934/araset.52.1.122131.

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DNA sequence alignment is a technique for discovering information between two base sequences which the Smith-Waterman algorithm is the accurate method that provides a precise result for alignment compared to others. However, the performance was influence by size of dataset and a long DNA base sequence which resulted the time required for the alignment process is much longer in relation to the number of DNA sequence samples. There are many ways to accelerate DNA sequence alignment, and Field Programmable Gate Array (FPGA) is a good choice due to its parallel processing and cost efficiency. Although FPGA acceleration approaches are not new, this work investigates a purely software-based FPGA acceleration using the Altera Cyclone IV EP4CE115F29C7N FPGA as the target device. The SW algorithm was developed using the C language in Quartus II version 18.1 and the Nios II software build tools for Eclipse. The development starts with setting up the Qsys architecture before developing the code in Eclipse to determine the computational performance. The result shows the computational timing and speed of the implementation, with the highest speed achieved being 198.76 cells per millisecond. To summarise, the computational performance ultimately depends on the maximum matrix size of the FPGA, which is also influenced by the DNA-based pair length and able to complete using low-cost FPGA.

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2

Ny, Virbora, Channareth Srun, Phok Chrin, Sokchea Am, Bunthern Kim, and Saran Meas. "Design of VHDL for MPPT Incremental Conductance on FPGA with Altera DE2-115 Development Board for Educational Purposes." ASEAN Journal of Science and Engineering Education 4, no. 1 (2022): 51–70. https://doi.org/10.17509/ajsee.v4i1.57991.

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In this paper, the design of VHDL for MPPT Incremental Conductance on an FPGA with the Altera DE2-115 Development Board is presented for educational purposes. The FPGA is programmed to control the MPPT tracking process by obtaining the maximum power from the solar panel. The Altera DE2-115 Development Board is used for the FPGA system design. The system is designed for individual blocks that are designed specifically to operate each step in the MPPT process. The system consists of five main parts: the solar panel, ADC, FPGA, PWM, and DC-DC Boost Converter. The solar panel provides the DC voltage and current. The ADC converts the solar panel's constantly changing voltage and current to a digital signal. The INC algorithm is started after the FPGA receives the digital signal from the ADC. The output PWM from the MPPT algorithm will drive the DC-DC Boost Converter circuit for the solar power tracking process. The experimental results show that the designed system can track the maximum power point of the solar panel.

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3

Sayudzi, Mohd Faris Izzwan Mohd, Irni Hamiza Hamzah, Azman Ab Malik, et al. "FPGA in hardware description language based digital clock alarm system with 24-hr format." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (2024): 244. http://dx.doi.org/10.11591/ijres.v13.i2.pp244-252.

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Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.

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4

Воронцов, В. І., та В. В. Лукашенко. "Модифікація сучасного RISC процесора шляхом реалізації спеціалізованих інструкцій". Problems of Informatization and Management 2, № 70 (2022): 19–23. http://dx.doi.org/10.18372/2073-4751.70.16842.

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Існують багато алгоритмів, які використовують одні й ті самі функції. Прикладом таких функцій є тригонометричні. Тригонометричні функції застосовуються в багатьох алгоритмах цифрової обробки сигналів, наприклад перетворення Хартлі, пе-ретворення Фур’є та у комп’ютерній графіці. Виконання даних операцій тільки при програмній реалізації відносно повільне. Якщо написати процесорні інструкції, що будуть сприйматися процесором як власні, тобто будуть в конвеєрі процесора, то швидкодія даних операцій зросте. Було розроблено апаратну реалізацію обрахування функції sin(x) на основі сучасного комерційного процесору MIPSfpga та протестованого на платі DE2-115.Це необхідно для задач, де обмежена потужність процесора, наприклад вбудовані системи. Це рішення не універсальне, а спеціалізоване. Вперше запропонована інструкція для обрахування функції sin(x) за допомогою полінома Тейлора, яка була впроваджена у процесорне ядро MIPSfpga, та протестована у пакеті ModelSim та на FPGA платі Altera DE2-115. Результати роботи можна використати для вивчення роботи процесора, ознайомлення з інструкціями користувача, покращення поточної реалізації, для модернізації існуючих інструкцій та реалізації нових процесорних інструкцій, використовуючи роз-роблені модулі.

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5

I., H. Hamzah, S. Z. Suhaimi M., A. Malik A., and F. A. Rahim A. "Design and implementation of HDL remote controller for smart home system." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 1 (2020): 117–24. https://doi.org/10.11591/ijeecs.v20.i1.pp117-124.

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This work presents a design and development of a remote controller application using an Altera DE2-115 board. A remote controller lighting provides smart technologies make it viable to monitor, control and support users in which can enhance the quality life and promote independent living. Nowadays, to turn on the electrical devices, a user will go to the located switch. It is difficult and required more time to switch on the devices instead of staying at certain location while controlling the switching mode of the devices. Implementing this system, users do not need to have numerous switches in their home to turn on the lights as they can do this digitally from a switchless control located in one place or using a remote controller. The Altera board is built with eighteen slide switches which act as inputs and at the same time it will display the outputs on seven segments, LEDs and LCD display character. As a conclusion, the remote controller lighting system provides convenience and energy efficiency in order to allow the users to control the lighting system using smart devices

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6

Esttaifan, Bashar Adel, and Mohammed Kasim Al-Haddad. "Implementation of a Proposed Load-Shedding System Using Altera DE2 FPGA." Journal of Engineering 23, no. 5 (2017): 76–93. http://dx.doi.org/10.31026/j.eng.2017.05.06.

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A load-shedding controller suitable for small to medium size loads is designed and implemented based on preprogrammed priorities and power consumption for individual loads. The main controller decides if a particular load can be switched ON or not according to the amount of available power generation, load consumption and loads priorities. When themaximum allowed power consumption is reached and the user want to deliver power to additional load, the controller will decide if this particular load should be denied receiving power if its priority is low. Otherwise, it can be granted to receive power if its priority is high and in this case lower priority loads are automatically switched OFF in order not to overload the power generation. The main idea of the proposed LS controller is to minimize the amount of the isolated load without overloading the power system. In this paper, three versions of load shedding controller were implemented using Altera DE2-115 FPGA; with number of loads equal 32, 64 and 128 for each controller.

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7

H. Hamzah, I., M. S. Z. Suhaimi, A. A. Malik, and A. F. A. Rahim. "Design and implementation of HDL remote controller for smart home system." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 1 (2020): 117. http://dx.doi.org/10.11591/ijeecs.v20.i1.pp117-124.

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<span>This work presents a design and development of a remote controller application using an Altera DE2-115 board. A remote controller lighting provides smart technologies make it viable to monitor, control and support users in which can enhance the quality life and promote independent living. Nowadays, to turn on the electrical devices, a user will go to the located switch. It is difficult and required more time to switch on the devices instead of staying at certain location while controlling the switching mode of the devices. Implementing this system, users do not need to have numerous switches in their home to turn on the lights as they can do this digitally from a switchless control located in one place or using a remote controller. The Altera board is built with eighteen slide switches which act as inputs and at the same time it will display the outputs on seven segments, LEDs and LCD display character. As a conclusion, the remote controller lighting system provides convenience and energy efficiency in order to allow the users to control the lighting system using smart devices. </span>

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8

de Andrade, Nicholas D., Ruben B. Godoy, Edson A. Batista, Moacyr A. G. de Brito, and Rafael L. R. Soares. "Embedded FPGA Controllers for Current Compensation Based on Modern Power Theories." Energies 15, no. 17 (2022): 6284. http://dx.doi.org/10.3390/en15176284.

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This work compares the performance of two embedded FPGA controllers that can be used in Active Parallel Power Filters (APPF). Both controllers are validated through the FPGA-in-the-loop (FIL) technique, the algorithm’s synthesis is accomplished using the Quartus II® platform, and the board used is from Altera®—Cyclone IV DE2-115. The main difference between the controllers resides in the power theories used to obtain the currents for compensation. The results confirm that the FPGA is a suitable digital device for the parallel operation of multiple compensators and calculation stages, being a viable solution for the requirements imposed in the control of APPF. Furthermore, the effectiveness of the FIL technique for validating the operation of digital circuits and control systems is also confirmed. Finally, a comparison between the processing costs of each of the implemented power theories is presented to guide novel proposals.

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9

Aminuddin, Zaim Zakwan, Irni Hamiza Binti Hamzah, Ahmad Asri Abd Samat, Mohaiyedin Idris, Alhan Farhanah Abd Rahim, and Zainal Hisham Che Soh. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205. http://dx.doi.org/10.11591/ijres.v11.i3.pp205-214.

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Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

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10

Zaim, Zakwan Aminuddin, Hamiza Hamzah Irni, Asri Abd Samat Ahmad, Idris Mohaiyedin, Farhanah Abd Rahim Alhan, and Hisham Che Soh Zainal. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205–14. https://doi.org/10.11591/ijres.v11.i3.pp205-214.

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Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

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