Journal articles: 'Altera DE2-115'

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Syed Abdul Mutalib Al Junid, Fadli Hamidi Rusli, Muhammad Hasif Aiman Mohd Sarwar Kamal Helal, et al. "Accelerating DNA Sequence Alignment using Altera DE2-115." Journal of Advanced Research in Applied Sciences and Engineering Technology 52, no. 1 (2024): 122–31. http://dx.doi.org/10.37934/araset.52.1.122131.

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DNA sequence alignment is a technique for discovering information between two base sequences which the Smith-Waterman algorithm is the accurate method that provides a precise result for alignment compared to others. However, the performance was influence by size of dataset and a long DNA base sequence which resulted the time required for the alignment process is much longer in relation to the number of DNA sequence samples. There are many ways to accelerate DNA sequence alignment, and Field Programmable Gate Array (FPGA) is a good choice due to its parallel processing and cost efficiency. Although FPGA acceleration approaches are not new, this work investigates a purely software-based FPGA acceleration using the Altera Cyclone IV EP4CE115F29C7N FPGA as the target device. The SW algorithm was developed using the C language in Quartus II version 18.1 and the Nios II software build tools for Eclipse. The development starts with setting up the Qsys architecture before developing the code in Eclipse to determine the computational performance. The result shows the computational timing and speed of the implementation, with the highest speed achieved being 198.76 cells per millisecond. To summarise, the computational performance ultimately depends on the maximum matrix size of the FPGA, which is also influenced by the DNA-based pair length and able to complete using low-cost FPGA.

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Ny, Virbora, Channareth Srun, Phok Chrin, Sokchea Am, Bunthern Kim, and Saran Meas. "Design of VHDL for MPPT Incremental Conductance on FPGA with Altera DE2-115 Development Board for Educational Purposes." ASEAN Journal of Science and Engineering Education 4, no. 1 (2022): 51–70. https://doi.org/10.17509/ajsee.v4i1.57991.

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In this paper, the design of VHDL for MPPT Incremental Conductance on an FPGA with the Altera DE2-115 Development Board is presented for educational purposes. The FPGA is programmed to control the MPPT tracking process by obtaining the maximum power from the solar panel. The Altera DE2-115 Development Board is used for the FPGA system design. The system is designed for individual blocks that are designed specifically to operate each step in the MPPT process. The system consists of five main parts: the solar panel, ADC, FPGA, PWM, and DC-DC Boost Converter. The solar panel provides the DC voltage and current. The ADC converts the solar panel's constantly changing voltage and current to a digital signal. The INC algorithm is started after the FPGA receives the digital signal from the ADC. The output PWM from the MPPT algorithm will drive the DC-DC Boost Converter circuit for the solar power tracking process. The experimental results show that the designed system can track the maximum power point of the solar panel.

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Sayudzi, Mohd Faris Izzwan Mohd, Irni Hamiza Hamzah, Azman Ab Malik, et al. "FPGA in hardware description language based digital clock alarm system with 24-hr format." International Journal of Reconfigurable and Embedded Systems (IJRES) 13, no. 2 (2024): 244. http://dx.doi.org/10.11591/ijres.v13.i2.pp244-252.

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Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.

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Воронцов, В. І., та В. В. Лукашенко. "Модифікація сучасного RISC процесора шляхом реалізації спеціалізованих інструкцій". Problems of Informatization and Management 2, № 70 (2022): 19–23. http://dx.doi.org/10.18372/2073-4751.70.16842.

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Існують багато алгоритмів, які використовують одні й ті самі функції. Прикладом таких функцій є тригонометричні. Тригонометричні функції застосовуються в багатьох алгоритмах цифрової обробки сигналів, наприклад перетворення Хартлі, пе-ретворення Фур’є та у комп’ютерній графіці. Виконання даних операцій тільки при програмній реалізації відносно повільне. Якщо написати процесорні інструкції, що будуть сприйматися процесором як власні, тобто будуть в конвеєрі процесора, то швидкодія даних операцій зросте. Було розроблено апаратну реалізацію обрахування функції sin(x) на основі сучасного комерційного процесору MIPSfpga та протестованого на платі DE2-115.Це необхідно для задач, де обмежена потужність процесора, наприклад вбудовані системи. Це рішення не універсальне, а спеціалізоване. Вперше запропонована інструкція для обрахування функції sin(x) за допомогою полінома Тейлора, яка була впроваджена у процесорне ядро MIPSfpga, та протестована у пакеті ModelSim та на FPGA платі Altera DE2-115. Результати роботи можна використати для вивчення роботи процесора, ознайомлення з інструкціями користувача, покращення поточної реалізації, для модернізації існуючих інструкцій та реалізації нових процесорних інструкцій, використовуючи роз-роблені модулі.

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I., H. Hamzah, S. Z. Suhaimi M., A. Malik A., and F. A. Rahim A. "Design and implementation of HDL remote controller for smart home system." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 1 (2020): 117–24. https://doi.org/10.11591/ijeecs.v20.i1.pp117-124.

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This work presents a design and development of a remote controller application using an Altera DE2-115 board. A remote controller lighting provides smart technologies make it viable to monitor, control and support users in which can enhance the quality life and promote independent living. Nowadays, to turn on the electrical devices, a user will go to the located switch. It is difficult and required more time to switch on the devices instead of staying at certain location while controlling the switching mode of the devices. Implementing this system, users do not need to have numerous switches in their home to turn on the lights as they can do this digitally from a switchless control located in one place or using a remote controller. The Altera board is built with eighteen slide switches which act as inputs and at the same time it will display the outputs on seven segments, LEDs and LCD display character. As a conclusion, the remote controller lighting system provides convenience and energy efficiency in order to allow the users to control the lighting system using smart devices

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Esttaifan, Bashar Adel, and Mohammed Kasim Al-Haddad. "Implementation of a Proposed Load-Shedding System Using Altera DE2 FPGA." Journal of Engineering 23, no. 5 (2017): 76–93. http://dx.doi.org/10.31026/j.eng.2017.05.06.

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A load-shedding controller suitable for small to medium size loads is designed and implemented based on preprogrammed priorities and power consumption for individual loads. The main controller decides if a particular load can be switched ON or not according to the amount of available power generation, load consumption and loads priorities. When themaximum allowed power consumption is reached and the user want to deliver power to additional load, the controller will decide if this particular load should be denied receiving power if its priority is low. Otherwise, it can be granted to receive power if its priority is high and in this case lower priority loads are automatically switched OFF in order not to overload the power generation. The main idea of the proposed LS controller is to minimize the amount of the isolated load without overloading the power system. In this paper, three versions of load shedding controller were implemented using Altera DE2-115 FPGA; with number of loads equal 32, 64 and 128 for each controller.

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H. Hamzah, I., M. S. Z. Suhaimi, A. A. Malik, and A. F. A. Rahim. "Design and implementation of HDL remote controller for smart home system." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 1 (2020): 117. http://dx.doi.org/10.11591/ijeecs.v20.i1.pp117-124.

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<span>This work presents a design and development of a remote controller application using an Altera DE2-115 board. A remote controller lighting provides smart technologies make it viable to monitor, control and support users in which can enhance the quality life and promote independent living. Nowadays, to turn on the electrical devices, a user will go to the located switch. It is difficult and required more time to switch on the devices instead of staying at certain location while controlling the switching mode of the devices. Implementing this system, users do not need to have numerous switches in their home to turn on the lights as they can do this digitally from a switchless control located in one place or using a remote controller. The Altera board is built with eighteen slide switches which act as inputs and at the same time it will display the outputs on seven segments, LEDs and LCD display character. As a conclusion, the remote controller lighting system provides convenience and energy efficiency in order to allow the users to control the lighting system using smart devices. </span>

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de Andrade, Nicholas D., Ruben B. Godoy, Edson A. Batista, Moacyr A. G. de Brito, and Rafael L. R. Soares. "Embedded FPGA Controllers for Current Compensation Based on Modern Power Theories." Energies 15, no. 17 (2022): 6284. http://dx.doi.org/10.3390/en15176284.

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This work compares the performance of two embedded FPGA controllers that can be used in Active Parallel Power Filters (APPF). Both controllers are validated through the FPGA-in-the-loop (FIL) technique, the algorithm’s synthesis is accomplished using the Quartus II® platform, and the board used is from Altera®—Cyclone IV DE2-115. The main difference between the controllers resides in the power theories used to obtain the currents for compensation. The results confirm that the FPGA is a suitable digital device for the parallel operation of multiple compensators and calculation stages, being a viable solution for the requirements imposed in the control of APPF. Furthermore, the effectiveness of the FIL technique for validating the operation of digital circuits and control systems is also confirmed. Finally, a comparison between the processing costs of each of the implemented power theories is presented to guide novel proposals.

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Aminuddin, Zaim Zakwan, Irni Hamiza Binti Hamzah, Ahmad Asri Abd Samat, Mohaiyedin Idris, Alhan Farhanah Abd Rahim, and Zainal Hisham Che Soh. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205. http://dx.doi.org/10.11591/ijres.v11.i3.pp205-214.

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Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

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Zaim, Zakwan Aminuddin, Hamiza Hamzah Irni, Asri Abd Samat Ahmad, Idris Mohaiyedin, Farhanah Abd Rahim Alhan, and Hisham Che Soh Zainal. "An FPGA application of home security code using verilog." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 3 (2022): 205–14. https://doi.org/10.11591/ijres.v11.i3.pp205-214.

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Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

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Mohamad, Hadis Nor Shahanim, Samihah Abdullah, Sukor Muhammad Ameerul Syafiqie Abdul, et al. "Design and implementation of smart traffic light controller with emergency vehicle detection on FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 48–59. https://doi.org/10.11591/ijres.v14.i1.pp48-59.

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Increased traffic volumes resulting from urbanization, industrialization, and population growth have given rise to complex issues, including congestion, accidents, and traffic violations at intersections. In the absence of a functional smart traffic light system, traffic congestion occurs due to imbalanced traffic flow at intersections. Current traffic management lacks provisions for ensuring the unobstructed movement of emergency vehicles, even a small delay for which can have significant consequences. This paper presents a smart traffic light controller developed using Verilog hardware description language (HDL) in Quartus Prime 21.1 and Questa Intel field programmable gate array (FPGA) Starter Edition 2021.2, and implemented on an Altera DE2-115 FPGA. The controller is designed specifically to detect emergency vehicle at four-way intersections for inputs radio frequency identification (RFID) readers and infrared (IR) sensors. The RFID readers and IR sensors are managed through slide switches on the FPGA board. The smart traffic light controller contains three sub-modules: clock division, counter, and finite state machine (FSM) operation, enabling it to manage traffic in scenarios with emergency vehicles, high traffic density, and low traffic density. This proposed system can alleviate intersection congestion by controlling access and allocating time effectively. In conclusion, the project ensures the smooth passage of emergency vehicles by continuously monitoring their presence and giving them priority in traffic flow.

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Mohamad Hadis, Nor Shahanim, Samihah Abdullah, Muhammad Ameerul Syafiqie Abdul Sukor, et al. "Design and implementation of smart traffic light controller with emergency vehicle detection on FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 1 (2025): 48. https://doi.org/10.11591/ijres.v14.i1.pp48-59.

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Increased traffic volumes resulting from urbanization, industrialization, and population growth have given rise to complex issues, including congestion, accidents, and traffic violations at intersections. In the absence of a functional smart traffic light system, traffic congestion occurs due to imbalanced traffic flow at intersections. Current traffic management lacks provisions for ensuring the unobstructed movement of emergency vehicles, even a small delay for which can have significant consequences. This paper presents a smart traffic light controller developed using Verilog hardware description language (HDL) in Quartus Prime 21.1 and Questa Intel field programmable gate array (FPGA) Starter Edition 2021.2, and implemented on an Altera DE2-115 FPGA. The controller is designed specifically to detect emergency vehicle at four-way intersections for inputs radio frequency identification (RFID) readers and infrared (IR) sensors. The RFID readers and IR sensors are managed through slide switches on the FPGA board. The smart traffic light controller contains three sub-modules: clock division, counter, and finite state machine (FSM) operation, enabling it to manage traffic in scenarios with emergency vehicles, high traffic density, and low traffic density. This proposed system can alleviate intersection congestion by controlling access and allocating time effectively. In conclusion, the project ensures the smooth passage of emergency vehicles by continuously monitoring their presence and giving them priority in traffic flow.

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Zhou, Zhen, Debiao He, Zhe Liu, Min Luo, and Kim-Kwang Raymond Choo. "A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme." ACM Transactions on Reconfigurable Technology and Systems 14, no. 2 (2021): 1–21. http://dx.doi.org/10.1145/3447812.

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As quantum computers become more affordable and commonplace, existing security systems that are based on classical cryptographic primitives, such as RSA and Elliptic Curve Cryptography ( ECC ), will no longer be secure. Hence, there has been interest in designing post-quantum cryptographic ( PQC ) schemes, such as those based on lattice-based cryptography ( LBC ). The potential of LBC schemes is evidenced by the number of such schemes passing the selection of NIST PQC Standardization Process Round-3. One such scheme is the Crystals-Dilithium signature scheme, which is based on the hard module-lattice problem. However, there is no efficient implementation of the Crystals-Dilithium signature scheme. Hence, in this article, we present a compact hardware architecture containing elaborate modular multiplication units using the Karatsuba algorithm along with smart generators of address sequence and twiddle factors for NTT, which can complete polynomial addition/multiplication with the parameter setting of Dilithium in a short clock period. Also, we propose a fast software/hardware co-design implementation on Field Programmable Gate Array ( FPGA ) for the Dilithium scheme with a tradeoff between speed and resource utilization. Our co-design implementation outperforms a pure C implementation on a Nios-II processor of the platform Altera DE2-115, in the sense that our implementation is 11.2 and 7.4 times faster for signature and verification, respectively. In addition, we also achieve approximately 51% and 31% speed improvement for signature and verification, in comparison to the pure C implementation on processor ARM Cortex-A9 of ZYNQ-7020 platform.

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Suhaili, Shamsiah, and Norhuzaimin Julai. "FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation." Pertanika Journal of Science and Technology 30, no. 1 (2022): 581–603. http://dx.doi.org/10.47836/pjst.30.1.32.

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Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA-256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA-256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design.

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Saleh, Shukur Bin, Sulaiman Bin Mazlan, Nik Iskandar Bin Hamzah, et al. "Smart Home Security Access System Using Field Programmable Gate Arrays." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 152. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp152-160.

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Nowadays, the rapid growth of burglary and theft cases over the world has been threatening to the vulnerability of traditional home security systems. Therefore the development home security with intelligent control wherein focus to enhance conventional technique to theadvanced digital security systemand to be more interestinginhome or building owner for preventing intruders in smart home implementation. However, using avariety of type conventional lock doors for security purposes and analog intruder sensor with individual function system is not secure enoughin order to protect the person or company properties. That why the emergence of new technology such as integrated circuit network will apply in Smart Home system for abetter security solution to prevent the houses from theintruder and hazardous fire incident. Therefore, this project is done to design and build a smart system with consist of digital security entry for automatic lock doors and also for activating or deactivate all security sensor in houses which is function for detecting the irregular movement and hot temperature (fire incident) in-house for the domestic residential sector. This product includeswith doors automatic lock system using servo motor and detect irregular movement intruder using PIR motion sensor (HC-SR501) and also measure hot temperature using temperature sensor (LM35). The sensor will transmit theanalog signal to Field Programmable Gate Array (FPGA) the Altera DE2-115 board to be processed and which will then display the status entry after key-in password and activation security system on the LED seven segment displays. The entry login controller will use apush button or switchesavailable on FPGA board that are used to login password for automatic door accessand also able maintained for control home smart security system.

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Yii, Bryna Ngieng Sing, Nabihah Ahmad, Mohd Helmy Abd Wahab, Warsuzarina Mat Jubadi, Chessda Uttraphan, and Syed Zulkarnain Syed Idrus. "Integration of Home Automation and Security System Controller with FPGA Implementation." Annals of Emerging Technologies in Computing 7, no. 5 (2023): 1–10. http://dx.doi.org/10.33166/aetic.2023.05.001.

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A home automation system is essential for promoting a safe and comfortable living environment and notable energy conservation for the user. However, the system’s favour had been obstructed by cost, power usage, inadequate security, complexity, and no emergency backup power. Current home automation systems with controllers were limited by their number of ports, fixed architecture, non-durable and non-parallel executions. Keeping this in view, integration of home comfort system, security system, and the automatic load transfer switch features are proposed using the base of Cyclone IV E: EP4CE115F29C7 FPGA Board (DE2-115). The top-level module is developed via Verilog Hardware Descriptive Language (HDL) with the bottom-up technique and used test bench for functional verification via ModelSim-Altera. The PWM method was applied to the lighting system to control the dimming of light through its digital signals via a maximum 500000 counter to improve energy efficiency for the proposed design. In this project, 200Hz pulses are successfully simulated to prevent visible flickering of lights in duty cycle generation. The light intensity of 40% and 100% are verified and successfully generated according to the inputs provided by the status of the LDR sensor and IR sensor. The proposed controller gives correct corresponding outputs to the 13 actuators based on the detected input stimuli. The proposed design utilized a total of 162 (<1%) logic elements, 32 registers, and total pins of 74 (14%). The proposed design successfully integrated the three-sub module and provided control on comfort and security system operations to prevent service failure during power blackout conditions at the top-level and utilized a low ratio of the FPGA.

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Shukur, Bin Saleh, Bin Mazlan Sulaiman, Iskandar Bin Hamzah Nik, et al. "Smart Home Security Access System Using Field Programmable Gate Arrays." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 152–60. https://doi.org/10.11591/ijeecs.v11.i1.pp152-160.

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Nowadays, the rapid growth of burglary and theft cases over the world has been threatening to the vulnerability of traditional home security systems. Therefore the development home security with intelligent control wherein focus to enhance conventional technique to theadvanced digital security systemand to be more interestinginhome or building owner for preventing intruders in smart home implementation. However, using avariety of type conventional lock doors for security purposes and analog intruder sensor with individual function system is not secure enoughin order to protect the person or company properties. That why the emergence of new technology such as integrated circuit network will apply in Smart Home system for abetter security solution to prevent the houses from theintruder and hazardous fire incident. Therefore, this project is done to design and build a smart system with consist of digital security entry for automatic lock doors and also for activating or deactivate all security sensor in houses which is function for detecting the irregular movement and hot temperature (fire incident) in-house for the domestic residential sector. This product includeswith doors automatic lock system using servo motor and detect irregular movement intruder using PIR motion sensor (HC-SR501) and also measure hot temperature using temperature sensor (LM35). The sensor will transmit theanalog signal to Field Programmable Gate Array (FPGA) the Altera DE2-115 board to be processed and which will then display the status entry after key-in password and activation security system on the LED seven segment displays. The entry login controller will use apush button or switchesavailable on FPGA board that are used to login password for automatic door accessand also able maintained for control home smart security system.

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Adiono, Trio Adiono, Kevin Shidqi, Christoporus Deo, Bramantio Yuwono, and Syifaul Fuada. "HOG-AdaBoost Implementation for Human Detection Employing FPGA ALTERA DE2-115." International Journal of Advanced Computer Science and Applications 9, no. 10 (2018). http://dx.doi.org/10.14569/ijacsa.2018.091042.

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Amjad, A. A. "Modeling 16-QAM in MATLAB and its implementation on Altera DE2-115." Politechnical student journal, no. 61 (September 2021). http://dx.doi.org/10.18698/2541-8009-2021-8-727.

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Amjad, A. A. "Modeling an SDR receiver in MATLAB and its implementation on Altera DE2-115." Politechnical student journal, no. 57 (April 2021). http://dx.doi.org/10.18698/2541-8009-2021-4-686.

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"FPGA Seven-Segment-Display by Using Altera DE2-115 Board with Practice and Implementation." International Journal of Advanced Trends in Computer Science and Engineering 10, no. 3 (2021): 2337–40. http://dx.doi.org/10.30534/ijatcse/2021/1181032021.

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This paper presents a simple implementation of Seven-Segment Displays in very simple way by using “Altera DE2-115 Board” to understand the idea for those students who are not in the field of Electrical and computer science field. Seven-Segment Displays are used to display input data on FPGA Device. The main focused of this paper is to implement and practice Seven-Segment Displays by using Verilog file in which we must write code in C++ and execution simulations on innumerable counter designs and implement designs on FPGA device utilizing Seven-Segment Displays and Switches. The control consumption and the delay of unit is predictable using the synthesizer “Quartus Prime” and get simulation result by using “ModelSim”.

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Hashim, Muhammad Amin, Yuan Wen Hau, and Rabia Baktheri. "EFFICIENT QRS COMPLEX DETECTION ALGORITHM IMPLEMENTATION ON SOC-BASED EMBEDDED SYSTEM." Jurnal Teknologi 78, no. 7-5 (2016). http://dx.doi.org/10.11113/jt.v78.9450.

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This paper studies two different Electrocardiography (ECG) preprocessing algorithms, namely Pan and Tompkins (PT) and Derivative Based (DB) algorithm, which is crucial of QRS complex detection in cardiovascular disease detection. Both algorithms are compared in terms of QRS detection accuracy and computation timing performance, with implementation on System-on-Chip (SoC) based embedded system that prototype on Altera DE2-115 Field Programmable Gate Array (FPGA) platform as embedded software. Both algorithms are tested with 30 minutes ECG data from each of 48 different patient records obtain from MIT-BIH arrhythmia database. Results show that PT algorithm achieve 98.15% accuracy with 56.33 seconds computation while DB algorithm achieve 96.74% with only 22.14 seconds processing time. Based on the study, an optimized PT algorithm with improvement on Moving Windows Integrator (MWI) has been proposed to accelerate its computation. Result shows that the proposed optimized Moving Windows Integrator algorithm achieves 9.5 times speed up than original MWI while retaining its QRS detection accuracy.

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Journal articles on the topic 'Altera DE2-115'

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