Dissertations / Theses: 'Analog and digital spaces'

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Godzina, Mark Kenneth. "A clockwork architecture digital minds in analog spaces /." PDF viewer required Home page for entire collection, 2007. http://archives.udmercy.edu:8080/dspace/handle/10429/64.

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Hickok, Tom. "Space Communication Channel Emulation Using Digital and Analog Signal Processing." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/398.

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New communication protocols intended for large distances, including low orbit and deep space, can be inherently difficult to evaluate since trial implementations are often impractical. In order to accurately measure the performance of a new protocol, it is important to evaluate it in an environment that most closely matchs that in which it will be used. This thesis demonstrates the ability to emulate a space communications channel through digitizing a transmission centered at an intermediate frequency of 70 MHz with a bandwidth of 24 MHz, digitally introducing the characteristics of a transmission through space, and reconstructing the digital data to its analog counterpart. Delay, Doppler shift, Gaussian noise, and fading are among the most prevalent characteristics of such a channel, and thus were the focus of this thesis. Special care was given to the design of each digital and analog component to maintain the integrity of the original signal by minimizing all undesired noise introduced. The final design can accurately produce a given dynamic transmission signature or continually output a static set of channel characteristic parameters to test new communication protocols.

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Romagnino, Silvana Diana Carleton University Dissertation Engineering Electrical. "Automatic behavioral design of mixed analog-digital ASICs : design space exploration." Ottawa, 1990.

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Souza, Junior Adao Antonio de. "Digital approach for the design of statistical analog data acquisition on SoCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/11491.

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With the current demand for mixed-signal SoCs, an increasing number of designers are looking for ADC architectures that can be easily implemented over digital substrates. Since ADC performance is strongly dependent upon physical and electrical features, it gets more difficult for them to benefit from more recent technologies, where these features are more variable. This way, analog signal acquisition is not allowed to follow an evolutionary trend compatible with Moore’s Law. In fact, such trend shall get worst, since newer technologies are expected to have more variable characteristics. Also, for a matter of economy of scale, many times a mixed-signal SoC presents a good amount of idle processing power. In such systems it is advantageous to employ more costly digital signal processing provided that it allows a reduction in the analog area demanded or the use of less expensive analog blocks, able to cope with process variations and uncertainty. Besides the technological concerns, other factors that impact the cost of the design also advise to transfer problems from the analog to the digital domain whenever possible: design automation and self-test requirements, for instance. Recent surveys indicate that the total cost in designer hours for the analog blocks of a mixed-signal system can be up to three times the cost of the digital ones. This manuscript explores the concept of bottom-up analog acquisition design, using statistical sampling as a way to reduce the analog area demanded in the design of ADCs within mixed-signal systems. More particularly, it investigates the possibility of using digital modeling and digital compensation of non-idealities to ease the design of ADCs. The work is developed around three axes: the definition of target applications, the development of digital compensation algorithms and the exploration of architectural possibilities. New methods and architectures are defined and validated. The main notions behind the proposal are analyzed and it is shown that the approach is feasible, opening new paths of future research. Keywords:

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Östlund, Anton, Viktor Eidhagen, and Marcus Nilsson. "Synaesthetica : Relationen mellan ljud, bild och kropp genom Kinesonisk interaktion." Thesis, Blekinge Tekniska Högskola, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18321.

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Under flera generationer har människan försökt tolka relationen mellan bild och ljud. Finns det en vetenskaplig koppling mellan ljusets frekvens och ljudets frekvens? Kan man uppleva båda modaliteter samtidigt? En liten procent av jordens befolkning kan uppleva denna symbios av modaliteter, en sinnenas union där hjärnan korskopplar två eller flera sinnen, denna funktionsvariation kallas för synestesi. Den digitala utvecklingen har möjliggjort denna korskoppling där man med nummer som material kan gestalta synestesi och skapa och uppleva flera modaliteter i symbios. Detta kandidatarbete syftar på att med hjälp av kinesonisk interaktion undersöka relationen mellan kropp, bild och ljud, hur man med kroppen som verktyg kan sammanväva och skapa bild och ljud samtidigt på ett naturligt och organiskt sätt. Genom etnografiska observationer, fokusgrupper och frågeformulär har vi undersökt olika funktioner som kan bidra till känslan av att ljudet känns naturligt till kroppsliga rörelser och visuell stimuli. Genom agentiell realism har vi sedan förankrat vår kunskap och de beslut vi tagit som designers för att presentera det ramverk vi föreslår för att skapa en multimodal upplevelse där kropp, ljud och bild möts.
For generations humans have strived to interpret the relationships between picture and sound. Is there a scientific connection between the lightwave-spectrum and the sound-frequency domain? Is it possible to experience both modalities at once? A fraction of the population can experience a symbiosis of these modalities, a union of the senses where the brain cross connects two or more, seemingly unrelated senses. This variation of sensory function is known as synesthesia. The rapid development in digital media has enabled this cross connection through numbers, creating a form of art where sound triggers or generates visual elements or vice versa. This bachelor thesis is aimed towards examining the relationship between picture, sound, bodily interaction and how we can weave these modalities together to create visual and sonic elements in real time in a natural and organic fashion through the concept of kinesonic interaction. We have through ethnographic observation, focus groups and questionnaires examined various functions which contributes to the sensation of embodied sound, retaining a natural feeling towards the body movements and visual cues. We’ve anchored our research, knowledge and decisions as designers in agential realism to present a framework which we suggest creates an intertwining multimodal experience where body, sound and picture meet.

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Saucier, Scott. "Multiband Analog-to-Digital Conversion." Fogler Library, University of Maine, 2002. http://www.library.umaine.edu/theses/pdf/SaucierS2002.pdf.

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Aldana, Rafael. "Photoelectronic analog to digital conversion /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Zahabi, Mohammad Reza. "Analog approaches in digital receivers." Limoges, 2008. https://aurore.unilim.fr/theses/nxfile/default/42bc3667-aba8-4a87-9fbc-b35358105335/blobholder:0/2008LIMO4009.pdf.

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Modern digital receivers need computationally demanding processes that leads to prohibitive complexity and power consumption. The idea of lending analog blocks for realization of digital algorithms can sometimes relaxes the complexity and high power consumption of digital receivers. The issue of analog approaches in digital receivers is studied in this dissertation by concentrating on two areas; analog decoding and front-end processing. For analog decoding, the realizations of some efficient decoders are presented along which our contribution in this area in conjunction with graph theory is proposed. In addition, analog realization of a fast Viterbi decoder is considered. It is shown that there is a very nice analog solution for realization of Add-Compare- Select that plays the central rule in Viterbi algorithm. In order to justify the proposed analog decoders, Cadence package is used. For front-end processing, a novel mixed-signal programmable filter is designed and investigated. The filter is suitable for high-rate communication systems. The proposed filter has analog input and analog sampled outputs. The filter is based on simple CMOS inverter and thus can be integrated efficiently with digital parts
Cette thèse propose d’utiliser des circuits analogiques pour réaliser des algorithmes numériques. Le but étant de diminuer la complexité et la puissance consommée et augmenter la vitesse. Deux applications gourmandes en temps de calcul ont été considérées dans cette thèse : le décodeur et le filtre RIF. On propose une structure analogique CMOS très efficace pour un décodeur Viterbi et pour un décodeur sur les graphes de Tanner. Les structures proposées ont été implantées et testées sous l’outil Cadence et démontre la validité de notre démarche. Quant au traitement de signal à l’entrée de décodeurs, un filtre RIF programmable utilisant la technologie CMOS a été étudié, conçu et implanté. La structure proposée est bien adapté aux systèmes de communications haut-débits. Le filtre possède une entrée analogique et une sortie échantillonnée, basée sur un simple inverseur CMOS et peut donc être intégré de manière efficace avec les parties numériques sur une seule puce

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Tarnoff, David. "Episode 1.2 – Analog vs. Digital." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/4.

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In this episode, we make the distinction between analog (real-world) values and the values that a computer uses, i.e., digital. We discuss the benefits of digital over analog and describe a simple system to capture analog values.

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Sætre, Gard Wold. "Digital signalrekonstruksjon for tidsmultipleksa analog-til-digital konvertere." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-19626.

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Siden digital kommunikasjon krever raskere og raskere systemer for å kunne håndtere økende behov for båndbredde og samplingsrate, kan systemer med èn ADC være utilstrekkelig. En løsning på dette problemet er å bruke TIADC systemer, som kan eliminere nødvendigheten til å stadig utvikle raskere og mer nøyaktige ADCer. Dette siden den totale hastigheten til et TIADC system er lik summen av de individuelle ADCene.I denne oppgaven har signalrekonstruksjon av et båndbegrenset signal fra et 2-TIADC og et 4-TIADC system, med antakelsene ikke-uniform periodisk sampling og kjent tidsforskyvning blitt vist. Den valgte metoden er basert på multirate filterbanker, hvor filterkoeffisientene blir funnet via interpolasjoen med en raised cosine funksjon. Det valgte inngangssignalet er et sinus signal med frekvens på 350 MHz, og samplingsfrekvensen ble valgt til 1 GHz. Lengden på de digitale filtrene blir bestemt av k og intervallet definert som [-2k-1,2k].Simuleringsresultatene viste at inngangssignalet fra 2-TIADC systemet kan, med $k$ valgt mellom 10 til 45 avhengig av roll-off faktoren, rekonstrueres med feil innen den satte feilgrensen på -100dB (MSE). Resultatene for 4-TIADC systemet viste seg å ha større feil, og for å kunne oppnå en rekonstruksjon innen feilgrensen, må k økes til mellom 15 og 50 avhengig av roll-off faktoren.Systemet for 2-TIADC ble også testet for å se hvordan metoden håndterte en økende tidsforskyvning. Tidsforskyvningen varierte fra 0.1-0.99% av Ts, og verdiene av k som ble testet var 25, 50 og 100. Resultatene viste at inngangssignalet kan rekonstrueres med en tidsforskyvning på henholdsvis 0.7, 0.85 og 0.95 Ts med en feil innen den valgte grensen.

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Jordan, Trevor P. "Digital Craft: Refabricating Digital to Analog Design Methodologies." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1337718599.

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Perbet, Lucas. "Optimisation de blocs constitutifs d'un convertisseur A/N pipeline entechnologie CMOS 0.18 µm pour utilisation en environnement spatial." Thesis, Toulouse, INPT, 2017. http://www.theses.fr/2017INPT0037/document.

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L’imagerie constitue un axe majeur de l’exploration de l’univers et de la Terre depuis l’espace, que l’on se trouve dans le domaine du visible ou non. Ainsi dans le domaine spatial, les données sont le plus souvent récupérées par un capteur CCD (Charge-Coupled Device, ou Dispositif à Transfert de Charge (DTC)) qui fournit des tensions analogiques vers un convertisseur analogique-numérique (CAN), dont la sortie sera transmise à une chaîne de traitement, puis envoyée sur terre. Ainsi, les CAN sont des éléments clés dans l’imagerie par satellite. De leur précision et de leur vitesse va dépendre la qualité de la représentativité de la chaîne de signaux binaires. Il est donc crucial de réaliser une conversion de données de grande qualité (vitesse, précision) tout en s’assurant de la résistance du CAN à l’environnement radiatif. L’objectif de cette thèse est d’améliorer la robustesse à l’environnement spatial, tout en optimisant les performances, de plusieurs fonctions élémentaires d’un convertisseur analogique-numérique de type pipeline 14bits,5MS/s, réalisées en technologie XFAB 0,18µm. Les trois fonctions ciblées sont les interrupteurs (notamment la résolution des problèmes liés au phénomène d’injection de charges en environnement spatial), les comparateurs (durcissement) et l’amplificateur à capacités commutées (amélioration du gain par une technique prédictive sans pénaliser la puissance consommée)
Imaging is a major issue in the observation of the Universe and the Earth from space, whether in the visible domain or not. Thus, in the spatial field, data is often gathered by a CCD (charge-Coupled Device) sensor, that supplies analog voltages to an Analog-to-Digital Converter (ADC), which outputs will be delivered to a processing chain, and then sent to earth. Consequently, ADCs are key elements in satellite imaging. Their precision and speed will indeed define the quality and the representativeness of the binary signal. It is then crucial to perform a high quality (speed & precision) conversion of the data, while making sure that the ADC can cope with the harsh irradiative environment. The purpose of this thesis is to improve the robustness to the space environment (hardening), while optimizing the performances, of several elementary devices that compose a 14 bits, 5MS/s pipeline ADC, made with the XFAB 180nm technology. The three targeted functions are the switches (especially the problems linked to coping with the charge injection problems in a space environment), the comparators (hardening) and the switched-capacitor amplifier (gain boosting through a predictive architecture with no penalty on the power consumption)

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Tsai, Tsung-Heng. "Time-interleaved analog-to-digital converters for digital communications /." For electronic version search Digital dissertations database. Restricted to UC campuses. Access is free to UC campus dissertations, 2005. http://uclibs.org/PID/11984.

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Grimes, Todd S. "Adaptive Power Analog-to-Digital Interface for Digital Systems." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1483366560887816.

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Esparza, Jorge A. "An analog preprocessing architecture for high-speed analog-to-digital conversion." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA276737.

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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1993.
Thesis advisor(s): Phillip E. Pace ; Douglas J. Fouts. "December 1993." Bibliography: p. 154. Also available online.

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Borkowski, Peter (Peter Joseph) 1963 Carleton University Dissertation Engineering Electrical. "Gallium arsenide analog circuits for high-speed analog-to-digital conversion." Ottawa.:, 1989.

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Hawrysh, Evan M. (Evan Mark). "Digital architectures for analog signal generation." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24058.

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Analog and mixed-signal testing is far more complex than its digital equivalent. This thesis will identify the analog test requirements through an extensive analysis of integrated circuit testing, possible error sources, and the different levels of test hierarchy. The results will show that analog testing requires spectrally pure, high-quality predictable test signals. These signals are most robust when reproduced through digital techniques such as direct digital frequency synthesis. Delta-sigma ($ Delta Sigma$) modulation is perhaps the most versatile technique, as it can precisely encode arbitrary analog waveforms into a pulse-density modulated (PDM), infinite-length, single bit-wide pattern. The noise-shaping characteristics of the $ Delta Sigma$ modulator also allow for simple reconstruction of the embedded signal. Unfortunately, on-chip signal generation using this method is currently hindered by the high area overhead and limited programmability of $ Delta Sigma$ modulation oscillators. We will introduce the concept of forcing the PDM pattern to be finite in length and thus periodic. Although other periodic encoding algorithms exist, forced-periodic PDM patterns will be shown to be far superior for their precise control over signal amplitude, frequency, phase, and also for their ability to encode an arbitrary waveform. Its effectiveness will be demonstrated with several experiments of single- and multi-tone waveforms of varying degrees of complexity. By creating a fixed-length pattern, we can take advantage of many common digital built-in self-test (BIST) concepts such as scan and RAMBIST, found on most digital and mixed-signal integrated circuits, to supply the necessary hardware. We will show how analog signal generation can be integrated into digital ICs using any or all of the IEEE 1149.1-1990 standard, embedded RAMs, and scan chains. These applications will indeed prove that with very little additional hardware, on-chip, high-quality analog signal gene

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Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.

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This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.

The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.

In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.

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Khilo, Anatol. "Integrated optical analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/43035.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. [133]-137).
An optically-sampled frequency-demultiplexed wideband analog-to-digital converter (ADC) which has potential to exceed the performance of electronic ADCs by orders of magnitude is studied analytically and numerically. The accuracy of the ADC as a function of its parameters is analyzed and impact of various imperfections of ADC components on its operation is evaluated. A universal error compensation algorithm for improving the conversion accuracy is proposed. On the way to implementation of the integrated optical ADC, two of its critical components - ring resonator filter bank and fiber-to-chip coupler -are designed. A novel coupler from a standard single mode fiber to a strongly confining silicon waveguide is proposed. The results of characterization of the filter bank and fiber-to-chip coupler fabricated on the silicon-on-insulator platform are presented and analyzed.
by Anatol Khilo.
S.M.

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Barron, Richard J. (Richard John). "Systematic hybrid analog/digital signal coding." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/46273.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (p. 201-206).
This thesis develops low-latency, low-complexity signal processing solutions for systematic source coding, or source coding with side information at the decoder. We consider an analog source signal transmitted through a hybrid channel that is the composition of two channels: a noisy analog channel through which the source is sent unprocessed and a secondary rate-constrained digital channel; the source is processed prior to transmission through the digital channel. The challenge is to design a digital encoder and decoder that provide a minimum-distortion reconstruction of the source at the decoder, which has observations of analog and digital channel outputs. The methods described in this thesis have importance to a wide array of applications. For example, in the case of in-band on-channel (IBOC) digital audio broadcast (DAB), an existing noisy analog communications infrastructure may be augmented by a low-bandwidth digital side channel for improved fidelity, while compatibility with existing analog receivers is preserved. Another application is a source coding scheme which devotes a fraction of available bandwidth to the analog source and the rest of the bandwidth to a digital representation. This scheme is applicable in a wireless communications environment (or any environment with unknown SNR), where analog transmission has the advantage of a gentle roll-off of fidelity with SNR. A very general paradigm for low-latency, low-complexity source coding is composed of three basic cascaded elements: 1) a space rotation, or transformation, 2) quantization, and 3) lossless bitstream coding. The paradigm has been applied with great success to conventional source coding, and it applies equally well to systematic source coding. Focusing on the case involving a Gaussian source, Gaussian channel and mean-squared distortion, we determine optimal or near-optimal components for each of the three elements, each of which has analogous components in conventional source coding. The space rotation can take many forms such as linear block transforms, lapped transforms, or subband decomposition, all for which we derive conditions of optimality. For a very general case we develop algorithms for the design of locally optimal quantizers. For the Gaussian case, we describe a low-complexity scalar quantizer, the nested lattice scalar quantizer, that has performance very near that of the optimal systematic scalar quantizer. Analogous to entropy coding for conventional source coding, Slepian-Wolf coding is shown to be an effective lossless bitstream coding stage for systematic source coding.
by Richard J. Barron.
Ph.D.

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Khilo, Anatol (Anatol M. ). "Integrated photonic analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68490.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 161-172).
Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits and 52 dBc spur-free dynamic range (SFDR) using a discrete-component photonic ADC. This corresponds to 15 fs jitter, a 4-5 times improvement over the jitter of the best electronic ADCs, and an order of magnitude improvement over the jitter of electronic ADCs operating above 10 GHz. The feasibility of a practical photonic ADC is demonstrated by creating an integrated ADC with a modulator, filters, and photodetectors fabricated on a single silicon chip and using it to sample a 10 GHz signal with 3.5 effective bits and 39 dBc SFDR. In both experiments, a sample rate of 2.1 GSa/s was obtained by interleaving two 1.05 GSa/s channels; higher sample rates can be achieved by increasing the channel count. A key component of a multi-channel ADC - a dual multi-channel high-performance filter bank - is successfully implemented. A concept for broadband linearization of the silicon modulator, which is another critical component of the photonic ADC, is proposed. Nonlinear phenomena in silicon microring filters and their impact on ADC performance are analyzed, and methods to reduce this impact are proposed. The results presented in the thesis suggest that a practical integrated photonic ADC, which successfully overcomes the electronic jitter bottleneck, is possible today.
by Anatol Khilo.
Ph.D.

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Luschas, Susan 1975. "Radio frequency digital to analog converter." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/28277.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 124-126).
Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (f), where k>l. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrow-band sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse.
by Susan Luschas.
Ph.D.

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Paul, Susanne A. (Susanne Anita). "Pipelined oversampling analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/7981.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 223-226).
Oversampling and noise-shaping techniques, such as [delta sigma] modulation, are widely used in analog-to-digital conversion to achieve accuracy that exceeds that of integrated-circuit components. Such converters have an inherent tradeoff between accuracy and speed, whereby resolution in amplitude is achieved at the expense of resolution in time. Although much attention has been focused on improving the speed and power of [delta sigma] analog-to-digital converters, data rates remain limited to less than a few MHz and are not easily extended. A pipelined oversampling architecture is described that circumvents the speed-resolution tradeoff of conventional oversampling converters by performing spatial, rather than temporal, oversampling. It combines high-resolution capabilities of [delta sigma] techniques with the high speed of pipelined architectures so that both of these attributes are achievable. The architecture also differs from conventional oversampling in that it performs Nyquist-rate sampling. Power is improved as a result of a charge-domain implementation, reduced sensitivity to thermal noise, simplified decimation, and reduced circuit speed, which permits voltage scaling and use of low-power technologies. Circuit techniques for implementation of a pipelined oversampling converter are also presented. Although CCDs are not essential to the concept, such converters are most practically built using a combination of CCD and CMOS circuits. CCDs make analog pipelines with hundreds of stages feasible by providing fully-depleted operations which are highly accurate, low power, simple, and compact. Other operations are performed using nondepleted circuits.
(cont.) A circuit technique, referred to as dynamic double sampling, is presented, which provides improved linearity and speed over existing techniques and forms a core circuit element for these nondepleted operations. Two prototype converters have been demonstrated. They were built in standard CMOS processes and show that moderate to high performance is possible from CCD circuits and can be achieved without custom processing. The first prototype uses a 1.2-[mu]m process and operates at an 18-MHz data rate. It achieves 78-dB SFDR, DNL < ±0.15 LSB at 13 bits, 74-dB SNR over a 9-MHz bandwidth, and 324 mW power dissipation. The second prototype uses a 0.6-[mu]m design rule and operates at a 30-MHz data rate. It achieves 70-dB SFDR and 66-dB SNR over a 15-MHz bandwidth.
by Susanne A. Paul.
Ph.D.

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Stanojević, Srdjan. "Pedro Meyer - From Analog To Digital." Master's thesis, Akademie múzických umění v Praze. Filmová a televizní fakulta AMU. Knihovna, 2007. http://www.nusl.cz/ntk/nusl-78826.

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Pedro Meyer je vizuální umělec, který jako jeden z prvních přivedl fotografii do nové technologické éry. V době, kdy počítače a digitální fotografie byly pro většinu lidí z oboru velkou neznámou, vyměnil Meyer tradiční fotoaparát, temnou komoru a film za nové technologické postupy. Pomocí počítače Meyer kombinoval části a detaily z různých fotografií a vytvořil tak nové a celistvější zobrazení. Uprovování fotografií ovládal do takové míry, že se tak zrodil jeho vlastní způsob vyjadřování. Kombinováním nejzajímavějších aspektů různých fotografií mohl Meyer zhodnotit jejich nejpůsobivější části a přeměnit je v nové obrazy vypovídající širší příběh. Myšlenku pozměňování fotografie, která byla do té doby tabu, etabloval například v projektech "I Photograph to Remember? ( Fotografuji, abych nezapomněl) a " Truths and Fictions? ( Skutečnosti a fikce). Meyerova jasnozřivá myšlenka, že fotografie musí pracovat s novými technologiemi, aby byla schopná přežít, stále ovlivňuje nové fotografy a fotografické školy po celém světě. Jeho přístup nicméně vznáší otázky morálnosti, autentičnosti a autorských práv; otázky, jenž se skrývají za myšlenkou pozměňování a přetváření fotografií za účelem vyjádření svých vlastních představ.

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Worden, Alexander. "Emergent Explorations: Analog and Digital Scripting." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/32543.

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This book documents an exploration of emergent and linear modes of defining space, form, and structure. The thesis highlights a dialog between analog and digital modeling techniques, in concept and project development. It identifies that analog modeling techniques, coupled with judgment, can be used to develop complex forms. The thesis project employs critical judgment and the textile techniques of crochet as a vehicle generate form. Crochet lends itself to this investigation because it is a serial process of fabrication that allows for the introduction of specific non-linear modifications. The resulting emergent forms produced by this mode of working can be precisely described by digital modeling techniques. These analog crochet models are translated into the digital through the employment of advanced digital modeling tools. This translation enables the visualization, development, testing, and execution of an architectural space, form, and structure.
Master of Architecture

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Hicks, William T. "DIGITAL FILTERING OF MULTIPLE ANALOG CHANNELS." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/608360.

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International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California
The traditional use of active RC-type filters to provide anti-aliasing filters in Pulse Code Modulation (PCM) systems is being replaced by the use of Digital Signal Processing (DSP). This is especially true when performance requirements are stringent and require operation over a wide environmental temperature range. This paper describes the design of a multi channel digital filtering card that incorporates up to 100 unique digitally implemented cutoff frequencies. Any combination of these frequencies can be independently assigned to any of the input channels.

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Melin, Erik. "Digital Geometry and Khalimsky Spaces." Doctoral thesis, Uppsala University, Department of Mathematics, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-8419.

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Digital geometry is the geometry of digital images. Compared to Euclid’s geometry, which has been studied for more than two thousand years, this field is very young.

Efim Khalimsky’s topology on the integers, invented in the 1970s, is a digital counterpart of the Euclidean topology on the real line. The Khalimsky topology became widely known to researchers in digital geometry and computer imagery during the early 1990s.

Suppose that a continuous function is defined on a subspace of an n-dimensional Khalimsky space. One question to ask is whether this function can be extended to a continuous function defined on the whole space. We solve this problem. A related problem is to characterize the subspaces on which every continuous function can be extended. Also this problem is solved.

We generalize and solve the extension problem for integer-valued, Khalimsky-continuous functions defined on arbitrary smallest-neighborhood spaces, also called Alexandrov spaces.

The notion of a digital straight line was clarified in 1974 by Azriel Rosenfeld. We introduce another type of digital straight line, a line that respects the Khalimsky topology in the sense that a line is a topological embedding of the Khalimsky line into the Khalimsky plane.

In higher dimensions, we generalize this construction to digital Khalimsky hyperplanes, surfaces and curves by digitization of real objects. In particular we study approximation properties and topological separation properties.

The last paper is about Khalimsky manifolds, spaces that are locally homeomorphic to n-dimensional Khalimsky space. We study different definitions and address basic questions such as uniqueness of dimension and existence of certain manifolds.

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Ljungström, Mattias. "Remarks on digital play spaces." Universität Potsdam, 2008. http://opus.kobv.de/ubp/volltexte/2008/2460/.

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Most play spaces support completely different actions than we normally would think of when moving through real space, out of play. This paper therefore discusses the relationship between selected game rules and game spaces in connection to the behaviors, or possible behaviors, of the player. Space will be seen as a modifier or catalyst of player behavior. Six categories of game space are covered: Joy of movement, exploration, tactical, social, performative, and creative spaces. Joy of movement is examined in detail, with a briefer explanation of the other categories.

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Wu, Yang 1974. "Monolithic nyquist rate analog to digital converter with digital calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29549.

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Nyquist rate analog to digital converter have always been an essential component in complex systems ranging from digital oscilloscope, radar, to modern telecommunication equipments. The fast-paced development in these complex systems has necessitated methods to improve resolution and power consumption of the analog to digital converters. The aim of this thesis is to offer one such method. The method involves the application of a digital DC reference source. The digital reference source will be proposed and used to remove mismatch, reduce comparator offset, thus improving the resolution of both flash and pipeline ADCs, while consuming no static power. The design of pipeline ADCs is also the emphasis of this work.
The digital reference source consists of flip-flops and RC low-pass filters. By programming flip-flops with appropriate digital bit streams, accurate DC reference levels can be generated. The generated DC reference levels replace the need for reference ladder in Flash ADCs. Furthermore, with programmability provided by the digital reference source, the generated reference levels can be modified to reduce comparator offset. The comparator offset reduction algorithm is also applied to pipeline ADCs to reduce non-linear distortion.
The design details of pipeline ADC is also discussed in this work. Quantitative analyses have been provided in determining design parameters in various subsystems. The analyses ensure that a 10-bit resolution is achieved for the pipeline ADC. Both Flash ADC and pipeline ADC were implemented in a 0.25 mum and 0.18 mum CMOS process respectively, and results demonstrating their successful operation are presented.

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Law, Waisiu. "Digital calibration of non-ideal pipelined analog-to-digital converters /." Thesis, Connect to this title online; UW restricted, 2003. http://hdl.handle.net/1773/5846.

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Savla, Anup. "Digital calibration algorithms for nyquist-rate analog to digital converters." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1087588301.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xxi, 246 p.; also includes graphics. Includes bibliographical references (p. 211-214).

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Gong, Pu, and Hua Guo. "Post-Correction of Analog to Digital Converters." Thesis, University of Gävle, Department of Technology and Built Environment, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-805.

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As the rapid development of the wireless communication system and mobile video devices, the integrated chip with low power consuming and high conversion efficiency is widely needed. ADC and DAC are playing an important role in these applications.

The aim of this thesis is to verify a post-correction method which is used for improving the performance of ADC. First of all, this report introduces the development and present status of ADC, and expatiate its important parameters from two different classes (static performance and dynamic performance). Based on the fundamental principle, the report then focuses on the dynamic integral non-linearity modeling of ADC. Refer to this model, one post-correction method is described and verified.

Upon the face of post-correction, this method is to modify the output signals which have been converted from analog to digital format by adding a correction term. Improvement made by the post-correction needs to be checked out. Thus the performance analysis mainly relay on the measures of total harmonic distortion and signal to noise and distortion ratio is also included in this thesis.

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Lundin, Henrik. "Post-correction of analog-to-digital converters." Licentiate thesis, KTH, Signals, Sensors and Systems, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-1587.

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This thesis deals with digital post-correction ofanalog-to-digital converters (ADCs). The performance ofpractical ADCs is deteriorated by nonidealities and flaws inthe converter. Methods for mitigating these errors by applyingdigital signal processing to the output of the converter havebeen proposed in the past. These methods are often referred toas postcorrection methods. This work is mainly concerned withpost-correction methods based on look-up tables.

Practical ADCs often exhibit dynamical error behavior,meaning that the error is dependent on the dynamics of theinput signal. In this thesis an extension of previouslyproposed post-correction methods is proposed. The method usesthe present sample in conjunction with a number of past samplesto form the table index. In order to reduce the number of indexbits, and thereby the size of the table, the method comprises abit mask, which selects a subset of the availablebits to be used in the index. Evaluations using experimentalADC data show that the proposed method improves the converterperformance, but also that the choice of index bits has asignificant impact on the outcome of the correction. Theincorporation of a bit mask enables an analysis of the effectof different bit masks. The analysis results in a framework forcomparing different correction tables.

The framework is then applied in an optimization problem.The goal is to find the best allocation of a fixed number ofindex bits. Two different criterions are applied: minimizationof the total harmonic distortion and maximization of thesignal-to-noise and distortion ratio. The results of theoptimization, performed with experimental data, show that theoptimal bit allocation is different depending on whichcriterion is used. Moreover, the performance of a correctionscheme deteriorates only slowly with decreasing table size, ifappropriate index bits are selected.

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Wikner, J. Jacob. "Studies on CMOS digital-to-analog converters /." Linköping : Univ, 2001. http://www.bibl.liu.se/liupubl/disp/disp2001/tek667s.pdf.

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Zareba, Grzegorz Szczepan. "Behavioral simulation of analog to digital converters." Diss., The University of Arizona, 2005. http://hdl.handle.net/10150/290152.

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The design of high-speed and high-resolution data converters is very difficult due to complexity of architectures used for converting analog signals into their digital representation. Since the introduction of the simplest conversion technique called parallel or flash technique numerous other architectures have been developed, for example n-stage pipeline, reference feed-forward architecture, folding and interpolating technique. The variety of A/D converter architectures additionally complicates design process due to fact that there is no available behavioral simulator, which can be utilized to support verification of particular converter's design. Many effects and imperfections present in A/D converters influence their performance, for example: switching imperfections, finite gain, clock jitter, and switching and coupling (Electro-Magnetic and substrate perturbations). In most cases several simulation tools have to be used to very performance of designed A/D converter. In this work a new methodology for behavioral simulation of A/D converters has been presented. Novel approach in behavioral modeling of A/D converters is based on utilization of Dynamic Linked Libraries (DLLs) to encapsulate behavior of basic modules of A/D converters. Predefined Basic Building Modules (BBMs) of A/D converters such as comparators, folding circuits, analog switches, binary encoders and many others are used to form a behavioral model of various types of A/D converters. Imperfections of BBMs are separated from the simulator framework and included into behavioral description of BBMs kept in DLL modules. Utilization of DLL modules gives a very convenient way for modifying BBMs independently from the simulator framework, and because DLL modules are executable files simulation time is significantly reduced (no translation or interpretation of simulation language commands is needed). Developed Behavioral Simulator of A/D converters is implemented in Visual C++ language and is partially based on an event driven simulation scheme and a data flow technique. The data flow technique was introduced into the simulator architecture to reduce number of events generated during simulation process, which additionally reduces simulation time. Several BBMs have been defined and constructed as DLL modules to support simulation of various types of A/D converters including flash, multi-stage, pipelined, and folding A/D converters.

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Danesh, Seyed Amir Ali. "Time interleaved counter analog to digital converters." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5790.

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The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration.

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Velazquez, Scott Richard. "Hybrid filter banks for analog/digital conversion." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/10436.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
Includes bibliographical references (leaves 288-291).
by Scott Richard Velazquez.
Ph.D.

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Dacy, Susan (Susan Mary) 1975. "Analog to digital converters for CMOS imagers." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46276.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (leaves 80-82).
A/D converters for single chip CMOS imagers have often been designed using the column-parallel approach, employing a slow A/D converter for each column of the sensor array. This thesis investigates a serial approach utilizing a single fast A/D converter to process all of the imager pixels. If power scales linearly with frequency in a given A/D architecture, power dissipation for the two approaches should be comparable. However, the serial approach should occupy less area since only the cost of one A/D converter is incurred. A figure of merit 1/power*area is introduced to verify this theory by comparing previously reported A/D approaches after appropriate technology, speed, and supply scaling. Camera system specifications require a single serial A/D converter to have 10b resolution at a 3MHz sampling rate for a CIF (352x288) imager array running at 30 frames/second Area minimization, power minimization, and the ability to build the A/D in a standard CMOS process are extremely important for consumer product applications. A single slope A/D architecture with a subnanosecond time digitizer shows promise for optimizing figure of merit over pipelined and folding interpolating approaches. This work focuses on the design issues of the 3MHz single-slope based A/D converter. Architectures appropriate for extending this A/D converter to 12MHz for four times CIF image arrays (704x576) are discussed. The 3MHz converter was designed, simulated, and laid out in a 0.35um CMOS technology. At 3.3V supply, 25°C and nominal process conditions, the converter dissipates 29 mW while occupying 0.3 mm2 . A 12MHz trislope extension of this converter is estimated to dissipate 37 mW in 0.4 mm2.
by Susan Dacy.
M.Eng.

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Yahalom, Gilad. "Analog-digital co-existence in 3D-IC." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/103677.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 231-246).
Ubiquitous mobile communication creates an increasing demand for high data rates, complex modulation schemes and low power design. The cost and performance benefits of conventional lithographic scaling are diminishing as process cost increases exponentially. 3D integration has the potential to keep driving performance forward while keeping cost down. The possibility to integrate separate dies with low-parasitic, dense interconnect and shorter routing provides area and power benefits. However, new challenges must be addressed in order to enable design in this new dimension and provide system level improvements. This thesis explores the impact, challenges and advantages of using 3D integration for combining digital and analog circuits for RF applications. The use of a vertical solenoid inductor in a Voltage Controlled Oscillator (VCO) is proposed. The inductor design utilizes the through-silicon-vias of the 3D stack as part of its geometry. The solenoid inductor exhibits a 28%larger inductance and a 6 dB higher quality factor compared to a conventional planar inductor occupying the same area. The VCO circuit phase noise is improved by 6 dB and exhibits an improved immunity to coupling from adjacent digital clock lines routed on the bottom tier of the 3D stack. An efficient hardware implementation is presented for an LTE uplink channel. The proposed design processes input data for cellular transmission. The core of the computation includes a variable-length, high-order, mixed-radix FFT and IFFT blocks. The use of energy efficient circuits and algorithms enables achieving an energy efficiency of up to 95 pJ/Sample and additional power savings of up to 24% for different operation modes. Both designs are combined along with digital-to-analog conversion to create a partial cellular transmitter in 3D-IC. Highly flexible and configurable design allows for various partitioning of the system. The 3D design has a digital link energy efficiency of up to 0.37 pJ/bit, compared to the 33.3 pJ/bit consumed in a multiple die partitioning and 0.83 pJ/bit for a 2.5D interposer emulated design. The use of the solenoid VCO along with digital-analog partitioning between the die tiers enables high immunity to noise and reduction of spurs at the VCO output.
by Gilad Yahalom.
Ph. D.

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Shen, Shumin. "A floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26772.

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This thesis studies the floating-point analog-to-digital converter (FP-ADC). The first attempt is to analyze the parallel architecture of the floating-point converter, which is our research base. The characteristics and specifications of the floating-point AID converter are described. Simulations of the parallel architecture of the floating-point A/D converter were conceived, run and presented here to support the theoretically derived FP-ADC transfer characteristics. After analyzing the parallel architecture of the floating-point A/D converter, the following work is to provide a way of minimizing the conversion time as well as keeping the precision of the floating point A/D converter (FP-ADC) by implementing the parallel architecture with Field Programmable Gate Arrays (FPGA). The thesis presents the design and practical implementation of the parallel FP-ADC, based on a FPGA and other hybrid components-of-the-shelf. The correctness of the design was verified by computer simulation, while the functionality of the implemented FP-ADC was tested on a test bench controlled by a PC. (Abstract shortened by UMI.)

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Delic-Ibukic, Alma. "Digital Background Calibration Techniques for High-Resolution, Wide Bandwidth Analog-to-Digital Converters." Fogler Library, University of Maine, 2008. http://www.library.umaine.edu/theses/pdf/Delic-IbukicA2008.pdf.

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Cartina, Dragos. "Characterization and digital correction of multi-stage analog-to-digital converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0012/MQ27012.pdf.

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Cartina, Dragos Carleton University Dissertation Engineering Electronics. "Characterization and digital correction of multi-stage analog-to- digital converters." Ottawa, 1997.

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Eliasson, Viktor. "Digital videoregistrering." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89823.

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This Bachelor thesis examines the possibility of replacing an outdated, analog video recording system to a digital counterpart. It is key that the video and audio signals remain synchronized, generator locked and time stamped. It is up to nine different video sources and a number of audio sources to be recorded and treated in such a manner which enables synchronized playback. The different video sources do not always follow a universal standard, and differ from format as well as resolution. This thesis aims to compare a number of state of the art commercial of the shelf solutions with proprietary hardware. Great emphasis is placed on giving a functional view over the system features and to evaluate different compression methods. The report also discusses different transmission, storage and playback options. The report culminates in a series of proposed solutions to sub problems which are solved and treated separately, leading to a final proposal from the author. The final draft set how well the system meets pre-set requirements to price.

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Li, Yan Ph D. Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science. "Digital assistance design for analog systems : digital baseband for outphasing power amplifiers." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82353.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 145-150).
Digital assistance is among many aspects that can be leveraged to help analog/mixed-signal designers keep up with the technology scaling. It usually takes the form of predistorter or compensator in an analog/mixed-signal system and helps compensate the nonidealities in the system. Digital assistance takes advantage of the process scaling with faster speed and a higher level of integration. When a digital system is co-optimized with system modeling techniques, digital assistance usually becomes a key enabling block for the high performance of the overall system. This thesis presents the design of digital assistances through the digital baseband design for outphasing power amplifiers. In the digital baseband design, this thesis conveys two major points: the importance of the use of the reduced-complexity system modeling techniques, and the communications between hardware design and system modeling. These points greatly help the success in the design of the energy-efficient baseband. The first part of the baseband design is to realize the nonlinear signal processing unit required by the modulation scheme. Conventional approaches of implementing this functionality do not scale well to meet the throughput, area and energy-efficiency targets. We propose a novel fixed-point piece-wise linear approximation technique for the nonlinear function computations involved in the signal processing unit. The new technique allows us to achieve an energy and area-efficient design with a throughput of 3.4Gsamples/s. Compared to the projected previous designs, our design shows 2x improvement in energy-efficiency and 25x in area-efficiency. The second part of the baseband design devotes to the nonlinear compensator design, aiming to improve the linearity performance of the outphasing power amplifier. We first explore the feasibility of a working compensator by use of an off-line iterative solving scheme. With the confirmation that a compensator does exist, we analyze the structure of the nonlinear baseband-equivalent PA system and create a dynamical real-time compensator model. The resulting compensator provides the overall PA system with around 10dB improvement in ACPR and up to 2.5% in EVM.
by Yan Li.
Ph.D.

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Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.

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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

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Sherkat, Mohammad Reza. "Co-design of analog to digital interface and digital signal processing architecture /." The Ohio State University, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=osu1488202678774616.

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Xia, Bo. "Analog-to-digital interface design in wireless receivers." Texas A&M University, 2004. http://hdl.handle.net/1969.1/3260.

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As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35Âµm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modiﬁcation improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a conﬁgurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25Âµm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.

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Björsell, Niclas. "Modeling Analog to Digital Converters at Radio Frequency." Doctoral thesis, KTH, Signalbehandling, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4523.

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Abstract:

Det här arbetet handlar om att ta fram beteendemodeller av analog till digital omvandlare avsedda för tillämpningar i radiofrekvensområdet. Det gäller tillämpningar inom telekommunikation men även in test- och mätinstrument där omvandlingen från analoga till digitala signaler ofta är en prestandamässig flaskhals. Modellerna är avsedda att användas för att efterbehandla utdata från omvandlaren och på så sätt förbättra prestanda på den digitala signalen. Genom att skapa modeller av verkliga omvandlare och hur dessa avviker från ett idealt beteende kan ofullständigheter korrigeras genom så kallad postkorrigering. Beteendemodeller innebär att genererar en lämplig insignal, mäta utdata och beräkna en modell. För omvandlare i radiofrekvensområdet ställs höga krav på instrumentering. Den testutrustningen som används är baserad på moderna högprestanda instrument som har kompletterats med specialbyggd utrustning för signalkonditionering och datainsamling. I avhandlingen har även olika insignaler utvärderats med såväl teoretisk som experimentell analys. Det finns ett flertal olika varianter av modeller för att modulera ett olinjär, dynamisk system. För att få en parametereffektiv modell har utgångspunkten varit att utgå från en Volterramodell som på ett optimalt sätt beskriver svagt olinjära dynamiska system, så som analog till digital omvandlare, men som är alltför omfattande i antal parametrar. Volterramodellens har sedan reducerats till en mindre parameterintensiv, modellerstruktur på så sätt att Volterrakärnans symmetriegenskaper jämförts med symmetrierna hos andra modeller. En alternativ metod är att använda en Kautz-Volterramodell. Den har samma generella egenskaper som Volterramodellen, men är inte lika parameterkrävande. I den här avhandlingen redovisas experimentella resultat av Kautz-Volterramodellen som i framtiden kommer att vara intressanta att använda för postkorrigeringen. För att kunna beskriva beteenden som en dynamiska olinjära modellen inte klarar av har modellen kompletterats med en statisk styckvis linjär modellkomponent. I avhandlingen presenteras en sluten lösning för att identifiera samtliga paramervärden i modellen. Vidare har det i avhandlingen genomförs en analys av hur respektive komponent påverkar prestanda på utsignalen. Därigenom erhålls ett mått på den maximala prestandaförbättring som kan uppnås om felet kan elimineras.
This work considers behavior modeling of analog to digital converters with applications in the radio frequency range, including the field of telecommunication as well as test and measurement instrumentation, where the conversion from analog to digital signals often is a bottleneck in performance. The models are intended to post-process output data from the converter and thereby improve the performance of the digital signal. By building a model of practical converters and the way in which they deviate from ideal, imperfections can be corrected using post-correction methods. Behavior modeling implies generation of a suitable stimulus, capturing the output data, and characterizing a model. The demands on the test setup are high for converters in the radio frequency range. The test-bed used in this thesis is composed of commercial state-of-the-art instruments and components designed for signal conditioning and signal capture. Further, in this thesis, different stimuli are evaluated, theoretically as well as experimentally. There are a large number of available model structures for dynamic nonlinear systems. In order to achieve a parameter efficient model structure, a Volterra model was used as a starting-point, which can describe any weak nonlinear system with fading memory, such as analog to digital converters. However, it requires a large number of coefficients; for this reason the Volterra model was reduced to a model structure with fewer parameters, by comparing the symmetry properties of the Volterra kernels with the symmetries from other models. An alternative method is the Kautz-Volterra model, which has the same general properties as the Volterra model, but with fewer parameters. This thesis gives experimental results of the Kautz-Volterra model, which will be interesting to apply in a post-correction algorithm in the future. To cover behavior not explained by the dynamic nonlinear model, a complementary piecewise linear model component is added. In this thesis, a closed form solution to the estimation problem for both these model components is given. By gradually correcting for each component the performance will improve step by step. In this thesis, the relation between a given component and the performance of the converter is given, as well as potential for improvement of an optimal post-correction.
QC 20100629

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50

Breevoort, Cornelius Marius. "A 9-bit, pipelined GaAs analog-digital converter." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15036.

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Dissertations / Theses on the topic 'Analog and digital spaces'

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